ICS9179BF-01LFT [IDT]
Low Skew Clock Driver, 9179 Series, 18 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48;型号: | ICS9179BF-01LFT |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Low Skew Clock Driver, 9179 Series, 18 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48 光电二极管 |
文件: | 总9页 (文件大小:276K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICS9179B-01
Integrated
Circuit
Systems, Inc.
Low Skew Buffers
General Description
Features
•
High speed, low noise non-inverting (0:17) buffer for
SDRAM clock buffer applications.
Supports up to four SDRAM DIMMS
Synchronous clocks skew matched to 250ps
window on SDRAM.
The ICS9179B-01 generates SDRAM clock buffers
required for high speed RISC or CISC microprocessor
systems such as Intel PentiumPro or Pentium II. An
output enable is provided for testability.
•
•
The device is a buffer with low output to output skew.This
is a Fanout buffer device, not using an internal PLL.This
buffer can also be a feedback to an external PLL stage for
phase synchronization to a master clock.
•
I2C Serial Configuration interface to allow individual
clocks to be stopped.
•
•
•
•
•
Multiple VDD, VSS pins for noise reduction
Tri-state pin for testing
Custom configurations available
3.0V – 3.7V supply range
48-pin SSOP package
The individual clock outputs are addressable through I2C
to be enabled, or stopped in a low state for reduced EMI
when the lines are not needed.
Block Diagram
Pin Configuration
48-Pin SSOP
PentiumPro is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
0256D—05/02/02
ICS9179B-01
Pin Descriptions
PIN NUMBER
4, 5, 8, 9
13, 14, 17, 18
PIN NAME
SDRAM (0:3)
SDRAM (4:7)
TYPE DESCRIPTION
OUT SDRAM Byte 0 clock outputs1
OUT SDRAM Byte 1 clock outputs1
31, 32, 35, 36 SDRAM (8:11) OUT SDRAM Byte 2 clock outputs1
40, 41, 44, 45 SDRAM (12:15) OUT SDRAM Byte 3 clock outputs1
21, 28
11
SDRAM (16:17) OUT SDRAM clock outputs useable for feedback.1
BUF_IN
IN Input for buffers
Tri-states all outputs when held LOW. Has internal
38
OE
IN
pull-up.2
24
25
SDATA
SCLK
I/O Data pin for I2C circuitry3
I/O Clock pin for I2C circuitry3
3, 7, 12, 16,
20, 29, 33, 37,
42, 46
6, 10, 15, 19,
22, 27, 30, 34,
39, 43
VDD
GND
PWR 3.3V Power supply for SDRAM buffer
PWR Ground for SDRAM buffer
23
26
VDDS
GNDS
N/C
PWR 3.3V Power supply for I2C circuitry
PWR Ground for I2C circuitry
1, 2, 47, 48
-
Pins are not internally connected
Notes:
1.
2.
3.
At power up all eighteen SDRAM outputs are enabled and active.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well
for complete platform flexibility.
Power Groups
VDD = Power supply for SDRAM buffer
VDDS = Power supply for I2C circuitry
Ground Groups
GND = Ground for SDRAM buffer
GNDS = Ground for I2C circuitry
2
ICS9179B-01
Technical Pin Function Descriptions
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for
SDRAM(0:17).
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from
Ground to this level. For the actual guaranteed high and
low voltage levels for the Clocks, please consult the DC
parameter table in this data sheet.
GND
This is the power supply ground (common or negative)
return pin for the internal core logic and all the output
buffers.
SDRAM(0:17)
These Output Clocks are use to drive Dynamic RAM’s
and are low skew copies of the CPU Clocks. The voltage
swing of the SDRAM’s output is controlled by the supply
voltage that is applied toVDD of the device, operates at
3.3 volts.
I2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in
the I2C protocol. It will allow read-back of the registers.
See configuration map for register functions. The I2C
specification in Philips I2C Peripherals Data Handbook
(1996) should be followed.
BUF_IN
Input for Fanout buffers (SDRAM 0:17).
OE
OE tristates all outputs when held low.
VDDS
This is the power supply to I2C circuitry.
GNDS
This is the ground to I2C circuitry.
3
ICS9179B-01
General I2C serial interface information
A.
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start
sequence, with an acknowledge bit between each byte.
Clock Generator
Address (7 bits)
+ 8 bits
dummy
command
code
+ 8 bits
dummy Byte ACK
count
Then Byte 0, 1, 2, etc in
sequence until STOP.
ACK
ACK
A(6:0) & R/W#
D2(H)
B.
Theclockgeneratorisaslave/receiverI2Ccomponent. Itcan"readback"(inPhilipsI2Cprotocol) thedatastored
in the latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet
the Intel SMB PIIX4 protocol.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D3(H)
Byte 0, 1, 2, etc in sequence until STOP.
Byte 0
ACK
Byte 1
ACK
ACK
C.
D.
E.
F.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller.The
bytesmustbeaccessedinsequentialorderfromlowesttohighestbytewiththeabilitytostopafteranycomplete
bytehasbeentransferred. TheCommandcodeandBytecountshownabovemustbesent, butthedataisignored
for those two bytes. The data is loaded until a Stop sequence is issued.
G.
H.
Inthepowerdownmode(PWR_DWN#Low), theSDATAandSCLKpinsaretristatedandtheinternaldatalatches
maintain all prior programming information.
At power-on, all registers are set to a default condition. Bytes 0 through 2 default to a 1 (Enabled output state).
Serial Configuration Command Bitmaps
Byte0:SDRAMClockRegister
BIT
PIN# PWD
DESCRIPTION
Bit7
18
17
14
13
9
1
1
1
1
1
1
1
1
SDRAM7
(Act/Inact)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDRAM6
(Act/Inact)
SDRAM5
(Act/Inact)
SDRAM4
(Act/Inact)
SDRAM3
(Act/Inact)
SDRAM2
(Act/Inact)
SDRAM1
(Act/Inact)
SDRAM0
(Act/Inact)
8
5
4
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
4
ICS9179B-01
Functionality
SDRAM
(12:15)
SDRAM
(16:17)
OE#
SDRAM (0:3)
SDRAM (4:7) SDRAM (8:11)
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1 X BUF_IN
1 X BUF_IN
1 X BUF_IN
1 X BUF_IN
1 X BUF_IN
Byte1:SDRAMClockRegister
Byte2:PCICLKClockRegister
BIT PIN# PWD DESCRIPTION
BIT PIN# PWD
DESCRIPTION
SDRAM15
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
45
44
41
40
36
35
32
31
1
1
1
1
1
1
1
1
(Act/Inact)
SDRAM17
(Act/Inact)
SDRAM16
(Act/Inact)
Bit 7 28
Bit 6 21
1
1
SDRAM14
(Act/Inact)
SDRAM13
(Act/Inact)
SDRAM12
(Act/Inact)
SDRAM11
(Act/Inact))
SDRAM10
(Act/Inact)
SDRAM9
(Act/Inact)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SDRAM8
(Act/Inact))
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Notes: 1 = Enabled; 0 = Disabled, outputs held low
ICS9179B-01 Power Management
The values below are estimates of target specifications.
Max 3.3V supply consumption
Max discrete cap loads
Condition
VDD = 3.465V
All static inputs = VDD or GND
No Clock Mode
(BUF_IN - VDD1 or
GND)
3mA
I2C Circuitry Active
Active 66MHz
115mA
180mA
(BUF_IN = 66.66MHz)
Active 100MHz
(BUF_IN = 100.00MHz)
5
ICS9179B-01
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
IIH
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
uA
IIL
-5
uA
Input Low Current
IIL
VIN = 0 V; Inputs with 100K pull-up resisto -60
CL = 0 pF; FIN @ 66M
-33
80
uA
IDD1
IDD2
IDD3
IDD4
IDD5
Fi1
120
180
260
360
500
150
5
mA
mA
mA
mA
µA
CL = 0 pF; FIN @ 100M
120
180
240
Operating Supply
Current
CL = 30 pF; RS=33W; FIN @ 66M
CL = 30 pF; RS=33W; FIN @ 100M
Stopped, input at 0 or VDD
Input frequency
VDD = 3.3 V; All Outputs Loaded
Logic Inputs
10
MHz
pF
1
Input Capacitance
CIN
1Guaranteed by design, not 100% tested in production.
6
ICS9179B-01
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
RDSP
RDSN
VOH
VOL
IOH
CONDITIONS
VO = VDD*(0.5)
MIN
10
TYP
MAX UNITS
24
24
W
W
VO = VDD*(0.5)
IOH = -36 mA
10
2.4
3
V
IOL = 23 mA
0.27
-115
57
0.4
-54
V
VOH = 2.0 V
mA
mA
ns
ns
%
IOL
VOL = 0.8 V
40
0.5
0.5
45
Tr
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.95
0.95
51
1.33
1.33
55
250
6
Fall Time1
Duty Cycle1
Tf
Dt
Skew1
Tsk
VT = 1.5 V
110
5
ps
ns
ns
ns
TPROP
VT = 1.5 V
1
1
1
Propagation1
TPROPEN VT = 1.5 V
TPROPDIS VT = 1.5 V
8
8
1Guarenteed by design, not 100% tested in production.
7
ICS9179B-01
GeneralLayoutPrecautions:
1) Use a ground plane on the top
layer of the PCB in all areas not
used by traces.
2)Makeallpowertracesandviasas
wide as possible to lower
inductance.
Notes:
1
All clock outputs should have
series terminating resistor. Not
shown in all places to improve
readibility of diagram
2 Optional EMI capacitor should be
usedonallCPU, SDRAM, andPCI
outputs.
CapacitorValues:
All unmarked capacitors are 0.01µF ceramic
8
ICS9179B-01
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
See Variations
.296
MAX.
.110
.016
.092
.0135
.010
MIN. NOM. MAX.
.620 .625 .630
A
A1
A2
B
C
D
E
AC
48
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
L
.032
N
µ
See Variations
5°
0°
8°
X
.085
.093
.100
Ordering Information
ICS9179BF-01
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
9
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