ICS9212YF-03-T [IDT]
Processor Specific Clock Generator, 400MHz, PDSO24, 0.150 INCH, MO-137, SSOP-24;型号: | ICS9212YF-03-T |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Processor Specific Clock Generator, 400MHz, PDSO24, 0.150 INCH, MO-137, SSOP-24 光电二极管 |
文件: | 总7页 (文件大小:133K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICS9212-03
Integrated
Circuit
Systems, Inc.
Direct Rambus™ Clock Generator
General Description
Features
•
•
Compatible with all Direct Rambus™ based IC s
Up to 400 MHz differential clock source for direct
Rambus™ memory system
Cycle to cycle jitter is less than 50ps
3.3 + 5% supply
Synchronization flexibility: Supports Systems that
need clock domains of Rambus channel to
synchronize with system or processor clock, or
systems that do not require synchronization of the
Rambus clock to another system clock
The ICS9212-03 is a High-speed clock generator providing
400 MHz differential clock source for direct Rambus™
memory system. It includes DDLL (Distributed Delay
locked loop) and phase detection mechanism to
synchronize the direct Rambus™ channel clock to an
external system clock. ICS9212-03 provides a solution for
a broad range of Direct Rambus memory applications.The
device works in conjunction with the ICS9250-09.
•
•
•
The ICS9212-03 power management support system
turns “off” the Rambus™ channel clock to minimize power
consumption for mobile and other power –sensitive
applications. In “clock off” mode the device remains “on”
while the output is disabled, allowing fast transitions
between clock-off and clock –on states. In “power down”
mode it completely powers down for minimum power
dissipation.
•
•
Excellent power management support
REFCLK input is from the ICS9250-09.
TheICS9212-03meetstherequirementsforinputfrequency
tracking when the input frequency clock is using Spread
Spectrum clocking and also the optimum bandwidth is
maintained while attenuating the jitter of the reference
signal.
Block Diagram
Pin Configuration
VDDREF
REFCLK
VDD1
GND1
GND3
PCLK/M
SYNCLK/N
GND2
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
FS0
FS1
BUSCLK_STOP#
VDD-OUT
GND-OUT
BUSCLKT
N/C
BUSCLKC
GND-OUT
VDD-OUT
MULTI0
MULTI1
GND3
PD#
FS(0:1)
Test MUX
Bypass MUX
GND
Bypclk
PLLclk
PLL
VDD2
VDDPD
BUSCLK_STOP#
PD#
Refclk
B
A
BUSCLKT
BUSCLKC
Phase
Aligner
10
11
12
PAclk
GND
Phase
Detector
Multi(0:1)
24-Pin 150 Mil SSOP
2
Pclk/M
Synclk/N
0270G—05/24/05
ICS9212-03
Pin Descriptions
Pin #
Name
Type
Description
1
VDDREF
REFV
Reference voltage for refclk, to be connected to CK133
2
3
4
REFCLK
VDD1
GND1
IN
Reference clock, to be connected to CK133
3.3 V power supply used for PLL
Ground for PLL
PWR
PWR
PWR
5, 13
GND3
Ground for control inputs
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
Ground for phase aligner
3.3 V power supply used for phase aligner
Reference voltage for phase detector inputs connected
to the controller
6,7
PCLK/M, SYNCLK/N
IN
8
9
GND2
VDD2
PWR
PWR
10
11
12
VDDPD
BUSCLK_ STOP#
PD#
REFV
IN
Active low output enable/disable
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
3.3V CMOS PLL Multiplier select, logic for selecting
the multiply ratio for the PLL from the input REFCLK
3.3V supply for clock out puts
IN
14,15
MULTI (0:1)
IN
16
17
VDD_OUT
GND_OUT
PWR
PWR
Ground for clock outputs
Out put clock connected to the Rambus channel. This
output is the complement of BUSCLK
NOT USED
Out put clock connected to the Rambus channel. This
output is the true component of BUSCLK
Ground for clock outputs
18
19
20
BUSCLKC
N/C
OUT
N/C
BUSCLKT
OUT
21
22
GND_OUT
VDD_OUT
PWR
PWR
3.3V supply for clock out puts
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
24, 23
FS(0:1)
IN
0270G—05/24/05
2
ICS9212-03
PLL Divider Selection and PLL Values (PLLCLK = REFCLK*A/B)
Mult0
Mult1
A
4
6
16
8
B
1
1
3
1
PLLCLK for REFCLK=50MHz
PLLCLK for REFCLK=66.67MHz
0
0
1
1
0
1
0
1
200
300
266.7
400
266.68
400.02
355.57
Reserved
Bypass and Test Mode Selections
Mode
FS0
FS1
Bypclk (int.)
Gnd
BusClk
PAclk
BusClkB
Normal
0
0
PAclkB
PLLclkB
RefclkB
Bypass
Test
1
0
PLLclk
Refclk
PLLclk
Refclk
1
1
Power Management Modes
State
PwrDnB
StopB
NORMAL
Clk Off
Powerdown
1
1
0
1
0
X
0270G—05/24/05
3
ICS9212-03
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics-input/supply/Outputs
Parameters
Symbol
Min
Max
Unit
Supply Voltage
VDD
3.15
3.45
V
Refclk Input cycle time
tCYCLE,IN
tJ,IN
10
-
40
250
60%
33
ns
ps
Input cycle-to-cycle Jitter
Input Duty cycle over 10k cycles
Input frequency of modulation
40%
30
DCIN
Fm,in
tCYCLE
KHz
Modulation index
Phase detector input cycle time at PDclk/M & Synclk/N
Initial phase error at phase detector inputs
PM,IN
tCYCLE,PD
Terr,init
0.25
30
-0.5
0.5
100
0.5
%
ns
tCYCLE,PD
Phase detector input duty cycle over 10k cycles
Input rise & fall times ( measured at 20%-80% of input voltage) for
PDCLK/M & SYNCLK/N,&REfCLK
DCIN,PD
25%
75%
tCYCLE,PD
TIR,TIF
-
1
ns
Input capacitance at PDCLK/M,Synclk/N,&REFCLK
CIN,PD
DCIN,PD
CIN,CMOS
VIL
-
-
-
7
0.5
10
0.3
-
pF
pF
pF
Input Capacitance matching at PCLK/M & SYNCLK/N
Input capacitance at CMOS pins
Input (CMOS) signal low voltage
-
Vdd
Vdd
Input (CMOS) signal high voltage
VIH
0.7
REFCLK input low voltage
VIL,R
VIH,R
-
0.3
-
0.3
-
Vddi,R
Vddi,R
Vddi,PD
Vddi,PD
V
REFCLK input high voltage
0.7
-
Input signal low voltage for PD inputs and STOP
Input signal high voltage for PD inputs and STOP
Input supply referance for REFCLK
Input supply referance vfor PD inputs
VIL,PD
VIH,PD
VDD,IR
VDDI,PD
0.7
1.3
1.3
3.3
3.3
V
Phase detector phase error for distributed loop measured at
PDCLK/M & SYNCLK/N(rising
tERR,PD
-100
100
ps
Cycle cycle time
tCYCLE
tJ
2.5
3.75
50
ns
ps
ps
Cycle-to-cycle jitter at Busclk/BUSCLKB
Total jitter over 2,3, or 4clock cycles
-
-
tJ
100
Phase aligner, phase step size (BSCLK/BUSCLKB)
PLL out put phase error when tracking SSC
tSTEP
1
-
ps
ps
tERR,SSC
-100
100
Out put crossing-point voltage
Output voltage swing
VX
1.3
0.4
1.8
0.6
V
V
VCOS
Output high voltage
VH
-
40%
-
2
V
tCYCLE
ps
Out put duty cycle over 10k cycle
DC
60%
50
Output cycle -to-cycle duty cycle error
Output rise & fall times ( measured at 20%-80% of output voltage)
tDC,ERR
tCR,tCF
300
500
psd
Difference between rise and fall times on a single device(20%-80%)
tCR,CF
-
100
ps
0270G—05/24/05
4
ICS9212-03
General Layout Precautions:
1) Use a ground plane on the top layer of
the PCB in all areas not used by traces.
2) Make all power traces and vias as wide
as possible to lower inductance.
Capacitor Values:
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
0270G—05/24/05
5
ICS9212-03
150 mil SSOP (QSOP)
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
1.35
0.10
--
0.20
0.18
MAX
1.75
0.25
1.50
0.30
0.25
MIN
.053
.004
--
.008
.007
MAX
.069
.010
.059
.012
.010
A
A1
A2
b
c
D
SEE VARIATIONS
SEE VARIATIONS
E
E1
e
5.80
3.80
0.635 BASIC
6.20
4.00
.228
.150
0.025 BASIC
.244
.157
L
0.40
1.27
.016
.050
N
α
SEE VARIATIONS
0° 8°
SEE VARIATIONS
0° 8°
ZD
SEE VARIATIONS
SEE VARIATIONS
VARIATIONS
D mm.
ZD
(Ref)
0.84
D (inch) ZD
N
MIN
8.55
MAX
8.75
MIN
.337
MAX
.344
(Ref)
.033
24
Reference Doc.: JEDEC Publication 95, MO-137
10-0032
Ordering Information
ICS9212yF-03LF-T
Example:
ICS XXXX y F - PP LF - T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
0270G—05/24/05
6
ICS9212-03
Revision History
Rev.
F
Issue Date Description
Page #
5/20/2005 Added LF Ordering Information.
5/24/2005 Corrected LF Ordering Information.
6
6
G
0270G—05/24/05
7
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