ICS9248YF-136LF-T [IDT]
Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | ICS9248YF-136LF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-136
Integrated
Circuit
Systems, Inc.
Advance Information
Frequency Generator & Integrated Buffers for K7 Processor
Recommended Application:
Single chip clock solution for SIS 730S K7 chipset.
Pin Configuration
VDDA
(AGPSEL)REF1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDCPU
1
*
CPUCLKT0
CPUCLKC0
CPUCLKT1
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
Output Features:
1
*(FS3)REF0
GND
X1
X2
•
1 - Differential pair open drain CPU clock
•
•
1 - Single-ended open drain CPU clock
13 - SDRAM @ 3.3V
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
•
•
•
•
6- PCI @3.3V,
2 - AGP @ 3.3V
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
VDDAGP
AGPCLK0
AGPCLK1
GND
•
2- REF @3.3V, 14.318MHz.
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
Features:
•
•
•
Up to 166MHz frequency support
SDATA
SCLK
Support FS0-FS3 trapping status bit for I2C read back.
Support power management: CPU, PCI, SDRAM stop
and Power down Mode from I2C programming.
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
•
•
Spread spectrum for EMI control (0 to -0.5%, 0.25%).
Uses external 14.318MHz crystal
Skew Specifications:
•
•
•
•
•
CPU - CPU: < 175ps
SDRAM - SDRAM < 250ps
PCI - PCI: < 500ps
CPU - SDRAM: < 500ps
CPU (early) - PCI: 1-4ns (typ. 2ns)
Functionality
Block Diagram
AGP
AGP
FS3 FS2 FS1 FS0 CPU SDRAM PCICLK
SEL = 0 SEL = 1
PLL2
48MHz
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
100.00 100.00
100.00 133.33
100.00 150.00
100.00 66.67
33.33
33.33
30.00
33.33
66.67
66.67
60.00
66.67
50.00
50.00
50.00
50.00
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF (1:0)
2
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
112.00 112.00
125.00 100.00
124.00 124.00
133.33 100.00
133.33 133.33
33.60
31.25
31.00
33.33
33.33
67.20
62.50
62.00
66.67
66.67
56.00
50.00
46.50
50.00
50.00
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLKC0
CPUCLKT (1:0)
2
SDRAM
DIVDER
Stop
SDRAM (12:0)
13
1
0
0
1
150.00 150.00
30.00
60.00
50.00
SDATA
SCLK
Control
Logic
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
111.11 166.67
110.00 165.00
166.67 166.67
33.33
33.00
33.33
30.00
32.00
30.00
66.67
66.00
66.67
60.00
64.00
60.00
55.56
55.00
55.56
45.00
48.00
45.00
PCI
DIVDER
Stop
PCICLK (4:0)
PCICLK_F
AGP (1:0)
5
2
FS (3:0)
PD#
AGP
DIVDER
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
90.00
48.00
45.00
90.00
48.00
60.00
Config.
Reg.
AGP_SEL
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
9248-136 Rev - 03/29/01
Third party brands and names are the property of their respective owners.
ICS9248-136
Advance Information
Pin Configuration
PIN NUMBER
1, 7, 15, 22, 25,
35, 43, 48
PIN NAME
TYPE
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
VDD
PWR
AGPSEL
REF1
FS3
IN
2
3
OUT
IN
14.318 MHz reference clock.
Frequency select pin.
REF0
OUT
14.318 MHz reference clock.
4, 14, 18, 19, 29,
GND
PWR
Ground pin for 3V outputs.
32, 39, 44
5
6
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
OUT
IN
FS1
8
9
PCICLK_F
FS2
OUT
IN
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCICLK0
PCICLK (4:1)
AGPCLK (1:0)
FS0
OUT
OUT
OUT
IN
PCI clock output.
13, 12, 11, 10
17, 16
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
20
48MHz
OUT
48MHz output clock
Pin 27, 28, 30, & 31 function select pin
0=Desktop 1=Mobile mode
MODE
IN
21
24_48MHz
SDATA
SCLK
OUT
I/O
Clock output for super I/O/USB default is 24MHz
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Stops all CPUCLKs clocks at logic 0 level, when input low
(when MODE active).
23
24
IN
CPU_STOP#
SDRAM11
IN
OUT
IN
27
28
30
SDRAM clock output
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low (when MODE active).
SDRAM clock output
PCI_STOP#
SDRAM10
OUT
IN
Stops all SDRAM clocks at logic 0 level, when input low
(when MODE active)
SDRAM clock output
SDRAM_STOP#
SDRAM9
OUT
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms. (when
MODE active)
PD#
IN
31
SDRAM8
OUT
OUT
SDRAM clock output
26, 33, 34, 36, 37,
38, 40, 41, 42
SDRAM (12, 7:0)
SDRAM clock outputs
Complementory"" clocks of differential pair CPU outputs. These clocks are
180° out of phase with SDRAM clocks. These open drain outputs need an
external 1.5V pull-up.
46
CPUCLKC0
OUT
OUT
"True" clocks of differential pair CPU outputs. These clocks are in phase with
SDRAM clocks. These open drain outputs need an external 1.5V pull-up.
45, 47
CPUCLKT (1:0)
Third party brands and names are the property of their respective owners.
2
ICS9248-136
Advance Information
General Description
The ICS9248-136 is the single chip clock solution for Desktop/Notebook designs using the SIS 630S style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-136
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDD48 = 48MHz, 24MHz, fixed PLL
VDDA = Core, PLL, X1, X2
VDDAGP=AGP, REF
MODE Pin Power Management Control Input
MODE
Pin 21
Pin 27
Pin 28
Pin 30
SDRAM9
Pin 31
SDRAM8
PD#
0
SDRAM11
CPU_STOP#
SDRAM10
PCI_STOP#
1
SDRAM_STOP#
Third party brands and names are the property of their respective owners.
3
ICS9248-136
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
Bit 7 Bit 6 Bit 5 Bit 4
FS3 FS2 FS1 FS0
AGP
AGP
Bit 2
CPU
SDRAM
PCI
Spread Precentage
SEL = 0 SEL = 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00
100.00
100.00
100.00
112.00
125.00
124.00
133.33
133.33
150.00
111.11
110.00
166.67
90.00
100.00
133.33
150.00
66.67
33.33
33.33
30.00
33.33
33.60
31.25
31.00
33.33
33.33
30.00
33.33
33.00
33.33
30.00
32.00
30.00
33.43
33.43
31.50
33.43
33.00
34.33
34.33
33.43
33.43
35.00
34.33
34.33
35.00
34.58
33.33
34.75
66.67
66.67
60.00
66.67
67.20
62.50
62.00
66.67
66.67
60.00
66.67
66.00
66.67
60.00
64.00
60.00
66.87
66.87
63.00
66.87
66.00
68.67
68.67
66.87
66.87
70.00
68.67
68.67
70.00
69.17
66.67
69.50
50.00
50.00
50.00
50.00
56.00
50.00
46.50
50.00
50.00
50.00
55.56
55.00
55.56
45.00
48.00
45.00
50.15
50.15
52.50
50.15
55.00
51.50
51.50
50.15
50.15
52.50
51.50
51.50
52.50
51.88
50.00
52.13
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
112.00
100.00
124.00
100.00
133.33
150.00
166.67
165.00
166.67
90.00
48.00
60.00
100.30
133.73
157.50
66.87
110.00
103.00
137.33
100.30
133.73
140.00
103.00
137.33
105.00
138.33
200.00
139.00
00000
Note1
48.00
45.00
Bit 2
Bit 7:4
100.30
100.30
105.00
100.30
110.00
103.00
103.00
133.73
133.73
140.00
137.33
137.33
105.00
138.33
200.00
104.25
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit , 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Bit 3
Bit 1
Bit 0
0
0
0
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
4
ICS9248-136
Advance Information
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
BIT
PIN# PWD
DESCRIPTION
Sel24_48
(1:24MHz, 0:48MHz)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Bit 7
-
1
-
Reserved
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
Reserved
13
12
11
10
9
Reserved
-
Reserved
47
46
45
-
CPUCLKT0
CPUCLKC0
CPUCLKT1
Reserved
8
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Reserved
24_48MHz
48MHz
33
34
36
37
38
40
41
42
1
1
1
1
1
1
1
1
21
20
26
27
28
30
31
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
X
X
X
1
FS3 (Readback)
FS2 (Readback)
FS1 (Readback)
FS0 (Readback)
REF1
-
-
3
2
1
REF0
17
16
1
AGPCLK1
AGPCLK0
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
ICS9248-136
Advance Information
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
REF strength 0=1X, 1=2X
Bit7
2,3
0
CPUCLKT1 - Stop - Control
0=CPU_STOP# will control CPUCLKT1,
1=CPUCLKT1 is free running even if CPU_STOP# is low
Bit6
45
0
Bit5
Bit4
Bit3
Bit2
Bit1
-
-
-
-
-
X
X
X
X
X
AGPSEL (Readback)
MODE (Readback)
CPU_STOP# (Readback)
PCI_STOP# (Readback)
SDRAM_STOP# (Readback)
AGP Speed Toggle
0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Bit0
-
1
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
1
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Third party brands and names are the property of their respective owners.
6
ICS9248-136
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
0.8
V
V
VIL
VSS-0.3
IDD
CL = 0 pF; Select @ 66M
180
mA
mA
MHz
pF
Supply Current
Input frequency
IDDL
30
Fi
VDD = 3.3 V;
CIN
Logic Inputs
5
45
3
Input Capacitance1
CINX
Ttrans
Ts
X1 & X2 pins
27
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V;
ms
ms
ms
ms
ps
TSTAB
TCPU-PCI
3
1.0
4.0
Skew1
TCPU-SPREAD VT = 1.5 V;
500.0
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-136
Advance Information
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
ZO
CONDITIONS
VO = VX
MIN
TYP
MAX
UNITS
Output Impedance
Ω
Termination to
Vpull-up(external)
Termination to
Vpull-up(external)
VOL = 0.3 V
Output High Voltage
Output Low Voltage
VOH2B
VOL2B
1
1.2
0.4
V
V
Output Low Current
Rise Time1
Fall Time1
IOL2B
tr2B
18
mA
ns
VOL = 0.3 V, VOH = 1.2 V
VOH = 1.2 V, VOL = 0.3 V
0.9
0.9
tf2B
ns
V
Vpullup(external)
+ 0.6
Differential voltage-AC1
Differential voltage-DC1
VDIF
Note 2
Note 2
Note 3
0.4
0.2
Vpullup(external)
+ 0.6
VDIF
VX
V
Differential Crossover
Voltage1
Duty Cycle1
Skew1
Jitter, Cycle-to-cycle1
Jitter, Absolute1
Notes:
550
45
1100
mV
dt2B
tsk2B
tjcyc-cyc2B
tjabs2B
VT = 50%
VT = 50%
VT = VX
55
200
250
+250
%
ps
ps
ps
VT = 50%
-250
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
Electrical Characteristics - 24M, 48M, REF, AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1
Output Impedance
RDSP 5
VO = VDD*(0.5)
20
60
60
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN5
VO = VDD*(0.5)
IOH = -14 mA
IOL = 6.0 mA
VOH = 2.0 V
VOL = 0.8 V
20
Ω
V
VOH5
VOL5
IOH5
IOL5
2.4
0.4
-20
V
mA
mA
10
1
Rise Time
Fall Time
Duty Cycle
Jitter
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4.0
4.0
ns
ns
%
1
tf5
1
dt5
45.0
55.0
500
1
tj1s5
VT = 1.5 V
ps
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-136
Advance Information
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
12
TYP
MAX UNITS
1
RDSP1
55
55
Ω
Ω
1
RDSN1
VO = VDD*(0.5)
IOH = -18 mA
12
VOH1
VOL1
IOH1
2.4
V
IOL = 9.4 mA
0.4
-22
V
VOH = 2.0 V
mA
mA
ns
ns
%
IOL1
VOL = 0.8 V
25
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.0
2.0
1
Fall Time
tf1
1
Duty Cycle
dt1
45.0
55.0
250
150
1
Skew Window
Jitter
tsk1
VT = 1.5 V
ps
ps
1
tj1s1
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD =VDDL 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
10
TYP
MAX UNITS
1
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP2A
20
20
Ω
Ω
1
RDSN2A
VO = VDD*(0.5)
IOH = -28 mA
10
VOH2A
VOL2A
IOH2A
IOL2A
2.4
V
IOL = 19 mA
0.4
-42
V
VOH = 2.0 V
mA
mA
ns
ns
%
VOL = 0.8 V
33
0.5
0.5
45
1
Rise Time
Fall Time
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.0
2
1
tf2A
1
Duty Cycle
dt2A
55
1
Skew Window ( output to output )
Jitter1
tsk2A
VT = 1.5 V
250
250.0
ps
ps
tcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
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9
ICS9248-136
Advance Information
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock sends first byte (Byte 0) through byte 7
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address
Address
D3(H)
D2(H)
ACK
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
Dummy Byte Count
Byte 0
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
Stop Bit
Byte 7
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
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10
ICS9248-136
Advance Information
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9248-
136 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
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11
ICS9248-136
Advance Information
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-136. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PD# (High)
CPUCLKT
CPUCLKC
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-136.
3. All other clocks continue to run undisturbed.
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12
ICS9248-136
Advance Information
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-136. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-136 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-136 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-136.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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13
ICS9248-136
Advance Information
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation.
SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-136. All other clocks will continue to run
while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner
that guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to the
SDRAM clocks inside the ICS9248-136.
3. All other clocks continue to run undisturbed.
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14
ICS9248-136
Advance Information
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-136 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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15
ICS9248-136
Advance Information
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEEVARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEEVARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
9.652
28
34
48
56
64
9.398
11.303
15.748
18.288
20.828
.370
.445
.620
.720
.820
.380
.455
.630
.730
.830
11.557
16.002
18.542
21.082
Ordering Information
ICS9248yF-136-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
16
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ICS9248YF-146-T
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Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48
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