ICS9250YF-27LF-T [IDT]
Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56;
| 型号： | ICS9250YF-27LF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-27
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Pin Configuration
Recommended Application:
810/810E and 815 type chipset.
*FS2//REF0
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
IOAPIC0
IOAPIC1
VDDL
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL
X1
X2
GND
GND
3V66-0
3V66-1
3V66-2
VDD
Output Features:
•
3 CPU (2.5V) (up to 133MHz achievable through I2C)
•
9 SDRAM (3.3V) (up to 133MHz achievable
through I2C)
GND
•
•
•
•
•
7 PCI (3.3 V) @33.3MHz
2 IOAPIC (2.5V) @ 33.3 MHz
3 Hublink clocks (3.3 V) @ 66.6 MHz
2 (3.3V) @ 48 MHz (Non spread spectrum)
1 REF (3.3V) @ 14.318 MHz
VDD
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
GND
SDRAM_F
VDD
PD#
SCLK
SDATA
FS1
PCICLK_F
PCICLK0
GND
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDD
Features:
VDD
GND
GND
•
Supports spread spectrum modulation,
0 to -0.5% down spread.
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Alternate frequency selections available through I2C
control.
48MHz_0
48MHz_1
VDD
•
•
•
•
FS0
56-Pin 300mil SSOP
* This input has a 50KΩ pull-down to GND.
Block Diagram
Functionality
FS2
FS1
FS0
Function
X1
X2
XTAL
OSC
REF0
X
X
0
0
0
1
Tristate
Test
PLL1
Spread
Spectrum
Active CPU = 66MHz
SDRAM = 100MHz
0
0
1
1
1
1
1
1
0
1
0
1
/2
/3
VDDL
Active CPU = 100MHz
SDRAM = 100MHz
CPU66/100/133 (2:0)
3
3
8
3V66 (2:0)
FS (2:0)
PD#
Active CPU = 133MHz
SDRAM = 133MHz
Control
Logic
SDRAM (7:0)
SDRAM_F
Active CPU = 133MHz
SDRAM = 100MHz
SDATA
SCLK
PCICLK (5:0)
PCICLK_F
/2
6
2
Config
Reg
IOAPIC (1:0)
VDDL
/2
Power Groups
AVDD = Pin 22 Analog power for PLL
AGND = Pin 23 Analog ground
VDD48 = Pin 27 Analog power for 48MHz PLL
GND = Pin 24 Analog ground for 48MHz PLL
PLL2
48MHz (1:0)
2
0395D—10/25/05
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9250-27
General Description
The ICS9250-27 is a single chip clock solution for 810/810E and 815 type chipset. It provides all necessary clock
signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-
27 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Pin Configuration
PIN NUMBER PIN NAME
TYPE
DESCRIPTION
FS2
IN
Function Select pin. Determines CPU frequency, all output functionality
1
REF0
OUT 3.3V, 14.318MHz reference clock output.
Crystal input, has internal load cap (33pF) and feedback
3
X1
X2
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
4
OUT
5, 6, 14, 17, 23,
24, 35, 41, 47, GND
48, 56
PWR Ground pins for 3.3V supply
9, 8, 7
3V66 (2:0)
OUT 3.3V Fixed 66MHz clock outputs for HUB
PWR 3.3V power supply
2, 10, 11, 21,
22, 27, 33, 38, 44
VDD
12
PCICLK_F
OUT Free running 3.3V PCI clock output
OUT 3.3V PCI clock outputs
20, 19, 18, 16,
15, 13
PCICLK (5:0)
48MHz_0
48MHz_1
FS (1:0)
25
26
OUT 3.3V Fixed 48MHz clock outputs for USB
3.3V fixed 48MHz clock output. Stronger output for graphics/video
interface (minimum 1V/ns edge rate)
OUT
Function Select pins. Determines CPU frequency, all output functionality.
Please refer to Functionality table on page 3.
29, 28
30
IN
SDATA
I/O
IN
Data pin for I2C circuitry 5V tolerant
31
SCLK
Clock pin of I2C circuitry 5V tolerant
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
32
PD#
IN
36, 37, 39, 40,
42, 43, 45, 46
3.3V output running 100MHz. All SDRAM outputs can be turned off
through I2C
SDRAM (7:0)
SDRAM_F
OUT
34
OUT 3.3V free running 100MHz SDRAM, cannot be turned off through I2C
2.5V Host bus clock output. 66MHz, 100MHz or 133MHz depending
on FS pins.
49, 50, 52
CPUCLK (2:0) OUT
51, 53
54, 55
VDDL
PWR 2.5V power suypply for CPU & IOAPIC
OUT 2.5V clock outputs running at 33.3MHz.
IOAPIC (1:0)
0395D—10/25/05
2
ICS9250-27
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
815
Condition
All static inputs = Vddq3 or GND All static inputs = Vddq3 or GND
Powerdown Mode
10mA
70mA
100mA
10mA
280mA
280mA
(PWRDWN# = 0
Full Active 66MHz
FS[2:0] = 010
Full Active 100MHz
FS[2:0] = 011
Full Active 133MHz
FS[2:0] = 111
Clock Enable Configuration
REF,
48MHz
PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK
Osc VCOs
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
0395D—10/25/05
3
ICS9250-27
Truth Table
FS2 FS1 FS0
CPU
SDRAM
Tristate
3V66
Tristate
TCLK/3
PCI
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
IOAPIC
Tristate
TCLK/6
X
X
0
0
0
1
1
1
1
0
1
0
1
0
1
Tristate
Tristate
TCLK/6
Tristate
TCLK
TCLK/2
66.6 MHz
100 MHz
133 MHz
133 MHz
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
66.6 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
14.318 MHz 33.3 MHz
0
1
1
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved ID
Reserved ID
Reserved ID
Reserved ID
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
0
SpreadSpectrum
(1=On/0=Off)
Bit 3
1
(Active/Inactive)
Bit 2
Bit 1
Bit 0
26
25
49
48MHz 1
48MHz 0
CPUCLK2
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Note: Reserved ID bits must be wirtten as "0".
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
36
37
39
40
42
43
45
46
Name
SDRAM7
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
0395D—10/25/05
4
ICS9250-27
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
9
Name
3V66-2 (AGP)
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Undefined bit
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
X
20
19
18
16
15
13
-
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Desctiption
PWD
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
Undefined bit (Note 3)
0
0
0
0
0
X
X
Undefined bit (Note 3)
CPUCLK SDRAM 3V66 PCICLK IOAPIC
Bit 0
FS0
FS1
MHz
MHz
100.0
100.0
133.32
100.0
100.0
100.0
133.32
133.32
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
66.66
100.0
133.32
133.32
66.66
0
Bit 0
Note 1
100.0
133.32
133.32
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always with
SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to
1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the
133MHz FSB speed as shown in this table. The CPU, 3v66, PCI, and IOAPIC clocks will be glitch free during this
transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "O".
Note3: Undefined bits can be written either as "1 or 0"
0395D—10/25/05
5
ICS9250-27
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 5: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Group Timing Relationship Table1
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset
2.5ns
7.5ns
0.0ns
Tolerance
500ps
Offset
5.0ns
5.0ns
0.0ns
Tolerance
500ps
Offset
0.0ns
0.0ns
0.0ns
Tolerance
500ps
Offset
3.75ns
0.0ns
Tolerance
500ps
CPU to SDRAM
CPU to 3V66
500ps
500ps
500ps
500ps
SDRAM to 3V66
500ps
500ps
500ps
3.75ns
500ps
3V66 to PCI
IOAPIC to PCI
USB & DOT
1.5-3.5ns
0.0ns
N/A
1.0ns
N/A
1.5-3.5ns
0.0ns
N/A
1.0ns
N/A
1.5-3.5ns
0.0ns
N/A
1.0ns
N/A
1.5 -3.5ns
0.0ns
N/A
1.0ns
N/A
Asynch
Asynch
Asynch
Asynch
0395D—10/25/05
6
ICS9250-27
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
VIL
VSS-0.3
-5
V
IIH
VIN = VDD
5
µA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66 MHz
-5
2
-100
97
Input Low Current
µA
IIL2
-200
115
110
165
330
320
395
19
CL = 0 pF; Select @ 100 MHz
91
mA
CL = 0 pF; Select @ 133 MHz
100
295
280
300
16
IDD3.3OP
CL = Max loads; Select @ 66 MHz
CL = Max loads; Select @ 100 MHz
CL = Max loads; Select @ 133 MHz
CL = 0 pF; Select @ 66 MHz
mA
mA
Operating Supply
Current
CL = 0 pF; Select @ 100 MHz
25
35
CL = 0 pF; Select @ 133 MHz
26
40
IDD2.5OP
CL = Max loads; Select @ 66 MHz
CL = Max loads; Select @ 100 MHz
19
30
34
50
mA
CL = Max loads; Select @ 133 MHz
CL = Max loads
40
220
<1
14.318
7
70
400
10
IDD3.3PD
IDD.25PD
Fi
Powerdown Current
µA
Input address VDD or GND
VDD = 3.3 V
Input Frequency
Pin Inductance
12
27
16
MHz
nH
pF
Lpin
CIN
Logic Inputs
5
Input Capacitance1
COUT
CINX
Ttrans
Ts
Output pin capacitance
X1 & X2 pins
6
pF
45
5
pF
Transition time1
Settling time1
Clk Stabilization1
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
ms
ms
5
TSTAB
From VDD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
5
ms
ns
ns
t
PZH,tPZL
PHZ,tPLZ
1
1
10
10
Delay1
t
1Guaranteed by design, not 100% tested in production.
0395D—10/25/05
7
ICS9250-27
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
13.5
TYP
22
MAX UNITS
1
Output Impedance
RDSP2B
VO = VDD*(0.5)
45
45
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
RDSN2B
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
13.5
2
23
Ω
V
V
VOH2B
VOL2B
0.4
-27
VOH @ MIN = 1.0 V
VOH @ MAX = 2.375 V
VOL @ MIN = 1.2 V
VOL @ MAX = 0.3 V
-27
27
-68
-9
IOH2B
IOL2B
Output High Current
mA
mA
54
11
Output Low Current
30
1.6
1.6
Rise Time1
Fall Time1
tr2B
tf2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
0.4
0.4
1.1
1.1
ns
ns
VT = 1.25 V, 66, 100 MHz
VT = 1.25 V, 133 MHz
45
45
50
53
55
55
Duty Cycle1
dt2B
%
Skew window1
Jitter, Cycle-to-cycle1
tsk2B
VT = 1.25 V
118
148
175
250
ps
ps
tjcyc-cyc2B VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
17
MAX UNITS
1
Output Impedance
RDSP1
VO = VDD*(0.5)
55
55
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
RDSN1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
18
Ω
V
V
VOH1
VOL1
2.4
0.55
-33
V
V
V
V
OH @ MIN = 1.0 V
-33
30
-108
-9
IOH1
Output High Current
mA
mA
OH @ MAX = 3.135 V
OL @ MIN = 1.95 V
OL @ MAX = 0.4 V
95
IOL1
tr1
Output Low Current
29
38
1.8
1.8
55
Rise Time1
Fall Time1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.2
1.3
50
ns
ns
%
ps
ps
tf1
Duty Cycle1
dt1
Skew window1
tsk1
VT = 1.5 V
82
175
500
Jitter, Cycle-to-cycle1
tjcyc-cyc1
VT = 1.5 V
123
1Guaranteed by design, not 100% tested in production.
0395D—10/25/05
8
ICS9250-27
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
9
TYP
MAX UNITS
1
Output Impedance
RDSP4B
VO = VDD*(0.5)
21.5
23
30
30
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
RDSN4B
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
9
2
Ω
V
V
VOH4B
VOL4B
0.4
-27
VOH @ MIN = 1.0 V
VOH @ MAX = 2.375 V
VOL @ MIN = 1.2 V
VOL @ MAX = 0.3 V
-27
27
-68
-9
IOH4B
Output High Current
mA
mA
54
11
IOL4B
tr4B
Output Low Current
30
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Jitter, Cycle-to-cycle1
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
1.1
1.1
50
ns
ns
%
ps
tf4B
dt4B
tjcyc-cyc4B VT = 1.25 V
123
500
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
14
MAX UNITS
1
Output Impedance
RDSP3
VO = VDD*(0.5)
24
24
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
RDSN3
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
10
18
Ω
V
V
VOH3
VOL3
2.4
0.4
-46
V
V
V
V
OH @ MIN = 2.0 V
-54
54
-92
-16
68
IOH3
Output High Current
mA
mA
OH @ MAX = 3.135 V
OL @ MIN = 1.0 V
OL @ MAX = 0.4 V
IOL3
tr3
Output Low Current
29
53
1.6
1.6
55
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1
ns
ns
%
ps
tf3
1.5
52
dt3
tsk3
VT = 1.5 V
164
250
Jitter, Cycle-to-cycle1
tjcyc-cyc3
VT = 1.5 V, 66, 100 MHz
180
250
ps
1Guaranteed by design, not 100% tested in production.
0395D—10/25/05
9
ICS9250-27
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
14
MAX UNITS
1
Output Impedance
RDSP1
VO = VDD*(0.5)
55
55
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
RDSN1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
18
Ω
V
V
VOH1
VOL1
2.4
0.55
-33
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
-33
30
-106
-14
94
IOH1
Output High Current
mA
mA
IOL1
tr1
Output Low Current
29
38
2
Rise Time1
Fall Time1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.3
1.4
52
ns
ns
%
ps
ps
tf1
2
Duty Cycle1
dt1
55
500
500
Skew window1
tsk1
VT = 1.5 V
304
170
Jitter, Cycle-to-cycle1
tjcyc-cyc1
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
20
TYP
32.6
31
MAX UNITS
1
Output Impedance
RDSP5
VO = VDD*(0.5)
60
60
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
RDSN5
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
Ω
V
V
VOH15
VOL5
2.4
0.55
-23
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
-29
29
-54
-11
54
IOH5
Output High Current
mA
mA
IOL5
tr5
Output Low Current
16
27
4
Rise Time1
Fall Time1
Duty Cycle1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.4
0.4
45
1.4
1.7
53
ns
ns
%
ps
ps
tf5
4
dt5
55
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle1
tjcyc-cyc5
tjcyc-cyc5
VT = 1.5 V, Fixed clocks
VT = 1.5 V, Ref clocks
215
930
500
1000
1Guaranteed by design, not 100% tested in production.
0395D—10/25/05
10
ICS9250-27
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-15 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
MAX UNITS
1
Output Impedance
RDSP3
VO = VDD*(0.5)
16.7
18.4
24
24
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
RDSN3
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
10
Ω
V
V
VOH3
VOL3
2.4
0.55
-46
V
V
V
V
OH @ MIN = 2.0 V
-54
54
-82
-20
95
IOH3
Output High Current
mA
OH @ MAX = 3.135 V
OL @ MIN = 1.0 V
OL @ MAX = 0.4 V
IOL3
tr3
Output Low Current
mA
ns
28
53
Rise Time1
Fall Time1
Duty Cycle1
VOL = 0.4 V, VOH = 2.4 V
0.4
0.4
45
1.1
1.6
tf3
dt3
tsk3
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.1
51
1.6
55
ns
%
ps
Skew
Jitter, Cycle-to-cycle1
VT = 1.5 V
116
250
tjcyc-cyc3B VT = 1.5 V
196
500
ps
1Guaranteed by design, not 100% tested in production.
0395D—10/25/05
11
ICS9250-27
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.3V 66MHz
PCI 33MHz
IOAPIC 33MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
0395D—10/25/05
12
ICS9250-27
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Address
Controller (Host)
ICS (Slave/Receiver)
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0395D—10/25/05
13
ICS9250-27
56-Lead, 300 mil Body, 25 mil, SSOP
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SYMBOL
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
56
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS9250yF-27LF-T
Example:
ICS XXXX y F - PPP LF - T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
0395D—10/25/05
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
14
ICS9250-27
Revision History
Rev.
Issue Date Description
8/17/2005 Added LF Ordering Information
Page #
C
14
D
10/25/2005 Removed "Contact ICS for an I2C programming application" note reference.
13
0395D—10/25/05
15
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