ICS93V847AG [IDT]
PLL Based Clock Driver, 93V Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 0.173 INCH, MO-153, TSSOP-24;
| 型号： | ICS93V847AG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 93V Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 0.173 INCH, MO-153, TSSOP-24 光电二极管 |
| 文件： | 总10页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS93V847
Integrated
Circuit
Systems,Inc.
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
RecommendedApplications:
Pin Configuration
•
•
Zero Delay Board Fan Out
Provides complete DDR logic solution with
ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852
GND
CLKC0
CLKT0
GND
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
CLKT4
CLKC4
CLKC3
CLKT3
VDD
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT2
CLKC2
GND
ProductDescription/Features:
VDD
•
•
•
•
Low skew, low jitter PLL clock driver
CLK_INT
CLK_INC
AVDD
AGND
CLKC1
CLKT1
VDD
1 to 5 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
10
11
12
SwitchingCharacteristics:
•
•
•
•
•
•
Period jitter (>66MHz):<40ps
CYCLE - CYCLE jitter (66MHz): <120ps
CYCLE - CYCLE jitter (>100MHz): <65ps
OUTPUT - OUTPUT skew: <60ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
24-Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
Functionality
Block Diagram
INPUTS
OUTPUTS
PLL State
FB_OUTT
FB_OUTC
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND
GND
L
H
L
L
H
L
L
H
L
Bypassed/off
Bypassed/off
CLKT0
CLKC0
FB_INT
FB_INC
H
H
H
PLL
CLK_INC
CLK_INT
2.5V
(nom)
CLKT1
CLKC1
L
H
L
L
H
L
L
H
L
on
on
2.5V
(nom)
CLKT2
CLKC2
H
H
H
CLKT3
CLKC3
CLKT4
CLKC4
0611C—06/18/03
ICS93V847
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
5, 12, 20
VDD
GND
PWR Power supply 2.5V
PWR Ground
1, 4, 13
8
9
AVDD
AGND
PWR Analog power supply, 2.5V
PWR Analog ground.
24, 21, 15, 11, 3 CLKT(4:0)
23, 22, 14, 10, 2 CLKC(4:0)
OUT
OUT
IN
"True" Clock of differential pair outputs.
"Complementary" clocks of differential pair outputs.
"True" reference clock input
6
7
CLK_INT
CLK_INC
IN
"Complementary" reference clock input
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
16
17
FB_OUTT
FB_OUTC
OUT
OUT
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
19
18
FB_INT
FB_INC
IN
IN
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
ICS93V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential
pairofclockoutputs(CLKT(4:0), CLKC(4:0))andonedifferentialpairfeedbackclockoutput(FB_OUT, FB_OUTC).The
clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC) and the
Analog Power input (AVDD).When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in ICS93V847 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC)toprovidehigh-performance, low-skew, low-jitteroutputdifferentialclocks(CLKT(4:0), CLKC(4:0)). ICS93V847
is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS93V847 is characterized for operation from 0°C to 85°C.
0611C—06/18/03
2
ICS93V847
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VDD + 0.5V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +85°C
StorageTemperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
SYMBOL
CONDITIONS
VI = VDD or GND
VI = VDD or GND
MIN
5
TYP
MAX
UNITS
µA
µA
mA
mA
V
IIH
IIL
5
Operating Supply
Current
IDD2.5 CL = 0pf @ 100MHz
IDDPD CL = 0pf
146
161
65
182
90
Input Clamp Voltage
VIK
VDDQ = 2.3V Iin = -18mA
-1.2
High-level output
voltage
I
I
I
I
OH = -1 mA
OH = -12 mA
OL=1 mA
VDD - 0.1
1.7
2.45
2.10
0.05
0.35
3
V
VOH
V
0.1
0.6
V
Low-level output voltage
VOL
OL=12 mA
V
Input Capacitance1
Output Capacitance1
1Guaranteed by design at 233MHz, not 100% tested in production.
CIN
VI = GND or VDD
pF
pF
COUT
VOUT = GND or VDD
3
0611C—06/18/03
3
ICS93V847
Recommended Operating Condition
(see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
DDQ, AVDD
CONDITIONS
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
V
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
CLK_INT, CLK_INC, FB_INC,
FB_INT
Low level input voltage
High level input voltage
VIL
0.4
2.1
V
DD/2 - 0.18
V
V
V
V
V
V
V
VIH
VIN
V
DD/2 + 0.18
-0.3
DC input signal voltage
(note 2)
VDD + 0.3
VDD + 0.6
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.36
Differential input signal
voltage (note 3)
VID
0.7
V
DD + 0.6
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
VOX
VIX
VDD/2 - 0.15
VDD/2 + 0.15
VDD/2 - 0.2 VDD/2 VDD/2 + 0.2
High level output current
IOH
IOL
-12
12
mA
mA
Low level output current
High Impedance
Output Current
Operating free-air
temperature
IOZ
TA
VDD=2.7V, VOUT=VDD or GND
0.1
±10
85
mA
°C
0
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDD and is the
voltage at which the differential signal must be crossing.
0611C—06/18/03
4
ICS93V847
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
freqop
MIN
33
MAX UNITS
2.5V+0.2V @ 25oC
Max clock frequency
233
170
60
MHz
MHz
%
Application Frequency
Range
freqApp
dtin
60
40
2.5V+0.2V @ 25oC
Input clock duty cycle
CLK stabilization
TSTAB
100
µs
Switching Characteristics
PARAMETER
Low-to high level
propagation delay time
High-to low level propagation
delay time
SYMBOL
CONDITION
MIN
TYP
5.5
MAX UNITS
ns
1
CLK_IN to any output
tPLH
1
CLK_IN to any output
5.5
ns
tPHL
tjit (per)
tjit(hper)
tsl(I)
tsl(o)
Period jitter
66/100/125/133/167MHz
100 to <170MHz
≥170MHz to 233MHz
-40
-100
-120
1
40
100
50
4
ps
ps
ps
Half-period jitter
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter1
Phase error
v/ns
v/ns
66/100/133/167MHz
1
2
tcyc-tcyc
66/100/125/133/167MHz
60
50
ps
ps
ps
ps
4
-50
0
t(phase error)
tskew
Output to Output Skew
Rise Time, Fall Time
40
60
tr, tf
Load = 120Ω/16pF
650
800
950
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, were
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0611C—06/18/03
5
ICS93V847
Parameter Measurement Information
V
DD
V
(CLKC)
R = 60Ω
V
DD
/2
R = 60Ω
V
(CLKC)
ICS93V847
GND
Figure 1. IBIS Model Output Load
VDD/2
C = 14 pF
ICS93V847
-VDD/2
SCOPE
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 60Ω
R = 50Ω
(TT)
V
R = 10Ω
Z = 50Ω
R = 50Ω
C = 14 pF
-VDD/2
V
(TT)
-VDD/2
NOTE: V
(TT) = GND
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
t
t
c(n+1)
c(n)
t
= t
± t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
0611C—06/18/03
6
ICS93V847
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
( ) n
( ) n+1
n = N
t
1
( ) n
t
=
( )
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(skew)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
tC(n)
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
fO
t(jit_per) tc(n)
=
-
Figure 6. Period Jitter
0611C—06/18/03
7
ICS93V847
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
jit(hper_n+1)
jit(hper_n)
1
f
o
tjit(hper) = tjit(hper_n)
1
2xfO
-
Figure 7. Half-Period Jitter
80%
80%
V , V
ID OD
20%
20%
Clock Inputs
and Outputs
t
t
slf
slr
Figure 8. Input and Output Slew Rates
0611C—06/18/03
8
ICS93V847
c
N
L
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
E1
E
MIN
--
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
MAX
.047
.006
.041
.012
.008
INDEX
AREA
A
A1
A2
b
0.05
0.80
0.19
0.09
.002
.032
.007
.0035
1
2
c
α
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
D
E1
e
4.30
4.50
.169
.177
0.65 BASIC
0.0256 BASIC
L
N
0.45
0.75
.018
.030
A
SEE VARIATIONS
SEE VARIATIONS
A2
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A1
- CC --
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
b
N
MIN
7.70
MAX
7.90
MIN
.303
MAX
.311
aaa
C
24
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256Inch)
(173 mil)
Ordering Information
ICS93V847yG-T
Example:
ICS XXXX y G - T
Designation for tape and reel packaging
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0611C—06/18/03
9
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93V847A (DDR PLL)
Description
Market Group
DIMM
Additional Info
Related Orderable Parts
Attributes
93V847AG
93V847AGLF
93V847AGLFT
93V847AGT
TSSOP 24 (PG24)
TSSOP 24 (PGG24)
TSSOP 24 (PGG24)
TSSOP 24 (PG24)
Package
Speed
NA
C
NA
C
NA
C
NA
C
Temperature
Voltage
2.5 V
Active
No
2.5 V
Active
No
2.5 V
Active
No
2.5 V
Active
No
Status
Sample
372
62
372
62
2500
2500
2500
2500
Minimum Order Quantity
Factory Order Increment
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