ICS951704YFT [IDT]
Processor Specific Clock Generator, 166MHz, PDSO48, 0.300 INCH, MO-118, SSOP-48;
| 型号： | ICS951704YFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 166MHz, PDSO48, 0.300 INCH, MO-118, SSOP-48 光电二极管 |
| 文件： | 总19页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS951704
Integrated
Circuit
Systems, Inc.
Advance Information
Programmable System Clock Chip for PIII™ Processor
Recommended Application:
ALI1644 style mobile chipset
Pin Configuration
Output Features:
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CPUCLKC0
CPUCLKT0
VDDCPU
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
IREF
GND
CPUCLK
VDDL
•
•
•
•
•
•
•
•
1 - CPU clocks @ 2.5V
1 - Pair of differential CPU clocks @ 3.3V
2 - AGPCLK @ 3.3V
9 - SDRAM @ 3.3V
7 - PCI @3.3V
AVDD
X1
X2
SDATA
SDRAM_STOP#*
SDRAM0
SDRAM1
SDRAM2
SDRAM3
VDD
**FS0/REF0
VDDREF
**FS1/REF1
GND
1 - 48MHz, @3.3V
GND
1 - 24/48MHz @ 3.3V
AGPCLK0
AGPCLK1
VDDAGP
*FS2/PCICLK_F
*FS3/PCICLK0
PCICLK1
GND
GND
3 - REF @3.3V, (selectable strength) through I2C
SDRAM4
SDRAM5
SDRAM6
SDRAM7
GND
Features:
•
•
•
•
•
Programmable ouput frequency
Programmable ouput rise/fall time
Programmable CPU, SDRAM, and PCI skew
Real time system reset output
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
VDD
VDDPCI
PCI_STOP#*
CPU_STOP#*
PD#/Vtt_PWRGD#*
SCLK
PCICLK2
PCICLK3
AVDD48
**MULTSEL/24_48MHz
GND
•
Watchdog timer technology to reset system
if over-clocking causes malfunction
Uses external 14.318MHz crystal
48-Pin 300mil SSOP
Notes:
•
REF0 can be 1X or 2X strength controlled by I2C.
Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down of 120K to GND
Skew Specifications:
*
•
•
•
•
•
CPU - CPU: <250ps
PCI - PCI: <500ps
SDRAM - SDRAM: <250ps
CPU - SDRAM:<350ps
CPU - PCI: <3ns
Functionality
CPU SDRAM AGPCLK PCICLK
FS3 FS2 FS1 FS0
Block Diagram
(MHz) (MHz)
(MHz)
66.6
66.6
75
(MHz)
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.2
32.1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.6
100.0
150.0
133.3
66.8
100.0
100.0
133.3
66.8
97.0
70.0
95.0
95.0
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
97.0
105.0
95.0
126.7
112.0
129.3
96.2
PLL2
48MHz
24_48MHz
66.6
66.8
66.6
75
66.6
66.8
64.6
70
63.4
63.4
74.6
64.4
64
/ 2
X1
X2
XTAL
OSC
REF(2:0)
3
PLL1
Spread
Spectrum
CPUCLKT0
CPUCLKC0
CPU
DIVDER
Stop
CPUCLK
SDRAM
DIVDER
Stop
Control
Logic
SDRAM (9:0)
SDATA
SCLK
FS(3:0)
PD#
10
PCI
DIVDER
Stop
PCICLK (3:0)
PCICLK_F
4
Config.
Reg.
PCI_STOP#
CPU_STOP#
MODE
112.0
97.0
96.2
AGP
DIVDER
AGPCLK (1:0)
2
MULTSEL
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
951704 Rev - 09/14/01
Third party brands and names are the property of their respective owners.
ICS951704
Advance Information
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
"Complementary" clocks of differential pair CPU outputs. These clocks are
180° out of phase with SDRAM clocks. These open drain outputs need an
external 1.5V pull-up.
1
CPUCLKC0
CPUCLKT0
OUT
"True" clocks of differential pair CPU outputs. These clocks are in phase with
SDRAM clocks. These open drain outputs need an external 1.5V pull-up.
2
OUT
3, 9, 15, 20, 30,
VDD
GND
PWR
PWR
Power supply pins, nominal 3.3V
Ground pins
37
4, 11, 12, 19, 25,
31, 36, 46, 48
5, 23
AVDD
X1
PWR
IN
Analog power supply for 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
6
7
X2
FS02, 3
REF0
FS12, 3
REF1
OUT
IN
8
OUT
IN
14.318 MHz reference clock.
Frequency select pin.
10
OUT
OUT
OUT
14.318 MHz reference clock.
11
REF2
AGPCLK(1:0)
14.318 MHz reference clock.
AGP outputs defined as 2X PCI. These may not be stopped.
14, 13
FS21, 2
PCICLK_F
FS31, 2
PCICLK0
IN
OUT
IN
Frequency select pin.
16
Free running PCICLK not stoped by PCI_STOP#
Frequency select pin.
17
22, 21, 18
24
OUT
OUT
IN
PCI clock output.
PCICLK(3:1)
MULTSEL2, 3
24_48MHz
PCI clock outputs.
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Selectable 48 or 24MHz output
Clock input of I2C input, 5V tolerant input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms. This pin
will be activiated when
OUT
IN
26
SCLK
PD#1
IN
27
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS
and MULTISEL0 inputs are valid and are ready to be sampled (active low)
VttPWRGD#
CPU_STOP#1
IN
IN
This asynchronous input halts CPU, SDRAM, and AGP clocks at logic "0"
level when driven low, the stop selection can be programmed through I2C.
28
29
Stops all PCICLKsbesides the PCICLK_F clocks at logic 0 level,
when input low
PCI_STOP#1
SDRAM ( 7:0 )
IN
OUT
IN
32, 33, 34, 35, 38,
39, 40, 41
SDRAM clock outputs.
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when
input low
42
SDRAM_STOP#1
Data input for I2C serial input, 5V tolerant input
Power supply pins, nominal 2.5V
2.5V CPU clock
43
44
45
SDATA
VDDL
IN
PWR
OUT
CPUCLK
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
3: Internal Pull-down resistor of 120K to GND on indicated inputs.
Third party brands and names are the property of their respective owners.
2
ICS951704
Advance Information
General Description
The ICS951704 is a main clock synthesizer chip for PIII based systems with ALI 1651 style chipset. This provides all clocks
required for such a system.
The ICS951704 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C
interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring
output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks.
This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system
become unstable from over clocking.
Reference R,
Board Target
Trace/Term Z
Output
Current
MULTISEL0
Iref =
Voh @ Z
V
DD/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
0
1
50 ohms
50 ohms
Ioh = 4* I REF 1.0V @ 50
Ioh = 6* I REF 0.7V @ 50
Rr = 475 1%,
Iref = 2.32mA
Third party brands and names are the property of their respective owners.
3
ICS951704
Advance Information
General I2C serial interface information for the ICS951704
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock sends Byte 0 through byte 8 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3(H)
Address D2(H)
ACK
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
If 7H has been written to B8
ACK
Byte 7
Byte 6
Byte 18
Byte 19
Byte 20
Stop Bit
ACK
ACK
ACK
If 12H has been written to B8
ACK
Byte18
Byte 19
Byte 20
If 13H has been written to B8
ACK
If 14H has been written to B8
ACK
Stop Bit
*See notes on the following page.
Third party brands and names are the property of their respective owners.
4
ICS951704
Advance Information
Brief I2C registers description for ICS951704
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Functionality & Frequency
Select Register
See individual
byte description
0
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Output Control Registers
1-6
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
Vendor ID & Revision ID
Registers
See individual
byte description
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00H to this byte.
Byte Count
Read Back Register
8
9
08H
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
Watchdog Timer
Count Register
10H
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
Watchdog Control Registers 10 Bit [6:0]
000,0000
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
VCO Control Selection Bit
10 Bit [7]
0
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
VCO Frequency Control
Registers
11-12
13-14
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
These registers control the spread
percentage amount.
Group Skews Control
Registers
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
15-16
17-20
Output Rise/Fall Time
Select Registers
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is
defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3.
4.
5.
6.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
5
ICS951704
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
SDRAM
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
PWD
Bit7 Bit2 Bit6 Bit5 Bit4
CPU
66.6
AGP
66.6
66.6
75
PCI
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.3
32.1
33.4
33.4
27.7
33.4
37.5
31.3
35.0
33.4
36.8
38.3
30.0
34.5
35.0
36.3
36.9
26.7
SS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 to-0.5%
0 to-0.5%
±0.25%
0 to-0.5%
0 to-0.5%
0 to-0.5%
±0.25%
0 to-0.5%
±0.25%
0 to-0.5%
±0.25%
±0.25%
±0.25%
±0.25%
0 to-0.5%
0 to-0.5%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
100.0
150.0
133.3
66.8
66.6
66.8
66.6
75
100.0
100.0
133.3
66.8
66.6
66.8
64.6
70
97.0
97.0
70.0
105.0
95.0
95.0
63.4
63.4
74.6
64.6
64.2
66.8
66.8
55.4
66.8
75
95.0
126.7
112.0
129.3
96.2
112.0
97.0
00010
Note1
96.2
Bit 7, 2,
Bit 6:4
66.8
100.2
100.2
110.7
133.6
100.0
125.0
140.0
133.6
147.0
153.3
120.0
138.0
140.0
145.0
147.5
160.0
100.2
166.0
100.2
75.0
83.3
62.6
70
105.0
133.6
110.3
115.0
120.0
138.0
140.0
145.0
147.5
160.0
66.8
73.6
76.6
60
69
70
72.6
73.8
53.4
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 7, 2, 6:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
Bit 3
Bit 1
Bit 0
0
1
0
1- Tristate all outputs
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I2C readback for Bits 7, 2, 6:4 indicate the revision code.
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
6
ICS951704
Advance Information
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
(Reserved)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PIN# PWD
DESCRIPTION
-
X
X
1
-
14
10
-
X
1
FS3#
-
(Reserved)
PCICLK3
PCICLK2
(Reserved)
PCICLK1
PCICLK0
PCICLK_F
AGPCLK1
REF1
22
21
-
1
1
X
1
(Reserved)
REF0
X
1
8
18
17
16
REF(1:0) 1X, 2X
default = 1=1X
Bit 2
10, 8
1
1
Bit 1
Bit 0
13
1
1
AGPCLK0
1
1, 2
CPUCLKT/C0
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
(Reserved)
-
-
X
X
X
1
FS0#
FS1#
FS2#
-
1
1
1
1
1
1
1
1
-
(Reserved)
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
-
41
40
39
38
35
34
33
32
-
SDRAM6
SDRAM7
(Reserved)
CPUCLK
24_48MHz
1
1
45
24
1
1
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit 7
-
1
(Reserved)
24_48MHz
select: 0=48MHz, 1=24MHz
Bit 6
-
1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
1
1
1
1
0
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
7
ICS951704
Advance Information
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
X
X
X
X
X
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Byte 9: Watchdog Timer Count Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these
8 bits correspond to how many
290ms the watchdog timer will wait
before it goes to alarm mode and
reset the frequency to the safe
setting. Default at power up is
16X 290ms = 4.64 seconds.
Note: FS values in bit (0:4) will correspond to Byte 0 FS
values. Default safe frequency is same as 00000 entry in
byte0.
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
Bit
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
Note: The decimal representation of these 9 bits (Byte 12
bit (7:0) & Byte 11 bit (7) ) + 8 is equal to the VCO divider
value. For example if VCO divider value of 36 is desired,
user need to program 36 - 8 = 28, namely, 0, 00011100 into
byte 12 bit & byte 11 bit 7.
Note: The decimal representation of these 7 bits
(Byte 11 (6:0)) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
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8
ICS951704
Advance Information
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Spread Spectrum Bit7
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
PWD
0
0
0
0
X
X
X
X
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
0
1
1
0
0
(Reserved)
PCICLK (3:0, F) Skew Control
CPUCLK Skew Control
(Reserved)
(Reserved)
SDRAM (7:0) Skew Control
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit
PWD
Description
Bit
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
1
0
1
0
1
0
(Reserved)
(Reserved)
SDRAM (7:0) Slew Control
AGPCLK(1:0) Slew Control
24_48MHz Slew Rate Control
CPUCLK Slew Rate Control
PCICLK_F Slew Rate Control
PCICLK (5:0) Slew Rate Control
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS(4:0)) or I2C (Byte 0 bit (1:7)) setting. Be sure
to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
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ICS951704
Advance Information
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these are
unused registers writing to these registers will not
affect device performance or functinality.
VCOProgrammingConstrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
UsefulFormula
VCOFrequency=14.31818xVCO/REFdividervalue
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
ToprogramtheVCOfrequencyforover-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to
byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate.
7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed
again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation
programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLLcould be unstable if VCO frequency is too fast or too slow.
Use14.31818MHzxVCO/REFdividervaluestocalculatetheVCOfrequency(MHz).
4. ICS recommends users, to utilize the software utility provided by ICSApplication Engineering to program theVCO frequency.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired.
See Application note for software support.
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10
ICS951704
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3V, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
77
100
16
5
mA
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
12
27
MHz
pF
CIN
Logic Inputs
CINX
X1 & X2 pins
45
3
pF
Clk Stabilization1
TSTAB
From VDD = 3.3 V to 1% target Freq.
ms
1Guaranteed by design, not 100% tested in production.
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11
ICS951704
Advance Information
Electrical Characteristics - CPUCLKT/C
TA = 0 - 70º C; VDD = 3.3 V +/-5%; (unless otherwise stated)
PARAMETER
Current Source
Output Impedance
Output High Voltage
SYMBOL
ZO
CONDITIONS
MIN
TYP
MAX UNITS
VO = VX
3000
Ω
VOH
IOH
tr
0.71
1.2
V
mA
ps
VR = 475W +1%; IREF = 2.32mA; IOH = 6*IREF
Output High Current
Rise Time1
Differential Crossover
Voltage1
-13.92
VOL = 20%, VOH = 80%
Note 3
175
45
700
55
VX
%
Duty Cycle1
Jitter, Cycle-to-cycle1
dt
VT = 50%
VT = VX
45
55
%
tjcyc-cyc
150
ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.6
1.6
55
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
%
1
tjcyc-cyc2B
VT = 1.25 V
Jitter, Cycle-to-cycle
250
ps
1Guaranteed by design, not 100% tested in production.
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12
ICS951704
Advance Information
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
IOH = -1 mA
IOL = 1 mA
VOL1
0.55
-33
38
V
mA
mA
ns
IOH1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
IOL1
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
ns
1
Duty Cycle
dt1
55
%
1
Skew
tsk1
VT = 1.5 V
500
500
ps
1
tjcyc-cyc
VT = 1.5 V
Jitter
ps
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH3
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
VOL3
0.4
-54
V
mA
mA
ns
IOH3
IOL3
41
45
1
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
2
1
Fall Time
Tf3
ns
1
Duty Cycle
Dt3
55
250
%
Skew1
Tsk1
VT = 1.5 V
ps
1Guarenteed by design, not 100% tested in production.
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13
ICS951704
Advance Information
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
2
ns
ns
%
ns
ns
dt5
45
-1
55
0.5
1
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
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14
ICS951704
Advance Information
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
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15
ICS951704
Advance Information
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS951704. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS951704 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high
pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PCICLK
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS951704 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS951704.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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16
ICS951704
Advance Information
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS951704 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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17
ICS951704
Advance Information
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS951704. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PD# (High)
CPUCLK
PCI_STOP# (High)
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS951704.
3. All other clocks continue to run undisturbed.
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18
ICS951704
Advance Information
c
N
In Millimeters
In Inches
L
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
E1
E
INDEX
AREA
A
A1
b
c
1
2
D
E
E1
e
SEE VARIATIONS
10.03
7.40
SEE VARIATIONS
.395
.291
a
hh xx 4455°°
10.68
7.60
.420
.299
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
A
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A1
- CC --
VARIATIONS
D mm.
e
SEATING
PLANE
D (inch)
b
N
MIN
15.75
MAX
16.00
MIN
.620
MAX
.630
.10 (.004)
C
48
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS951704yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
Third party brands and names are the property of their respective owners.
19
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