ICS97U877YHLF-T [IDT]
PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52, BGA-52;
| 型号： | ICS97U877YHLF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52, BGA-52 驱动 输出元件 逻辑集成电路 |
| 文件： | 总13页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS97U877
Advance Information
Integrated
Circuit
Systems,Inc.
1.8V Wide Range Frequency Clock Driver
RecommendedApplication:
Pin Configuration
•
•
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864
1
2
3
4
5
6
A
B
C
D
E
F
ProductDescription/Features:
•
•
•
•
•
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
G
H
J
Auto PD when input signal is at a certain logic state
K
SwitchingCharacteristics:
52-Ball BGA
•
•
•
•
Period jitter:40ps
Half-period jitter: 60ps
CYCLE - CYCLE jitter 40ps
OUTPUT - OUTPUT skew: 40ps
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
CLKT1
CLKC1
CLKC2
CLKT2
CLK_INT
CLK_INC
AGND
AVDD
CLKT3
CLKC3
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
CLKC0
GND
NB
CLKC5
GND
NB
CLKT5
GND
GND
OS
CLKT6
CLKC6
CLKC7
CLKT7
VDDQ
NB
VDDQ
NB
VDDQ
OE
VDDQ
GND
GND
CLKC9
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
NB
NB
VDDQ
NB
VDDQ
NB
GND
CLKC4
GND
CLKT4
GND
CLKT9
K
CLKC8
Block Diagram
CLKT0
CLKC0
LD* or OE
OE
Powerdown
Control and
Test Logic
CLKT1
CLKC1
LD*, OS or OE
OS
AVDD
CLKT2
CLKC2
40
31
PLL bypass
LD*
CLKT3
CLKC3
30
1
VDDQ
CLKC2
CLKT2
CLK_INT
CLK_INC
VDDQ
AGND
AVDD
VDDQ
CLKC7
CLKT7
VDDQ
FB_INT
FB_INC
FB_OUTC
FB_OUTT
VDDQ
OE
CLKT4
CLKC4
CLKT5
CLKC5
ICS97U877
CLK_INT
CLKT6
CLKC6
CLK_INC
10K-100k
CLKT7
CLKC7
GND 10
21
PLL
OS
GND
11
20
CLKT8
CLKC8
FB_INT
FB_INC
CLKT9
CLKC9
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
40-Pin MLF
FB_OUTT
FB_OUTC
0792—07/07/03
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS97U877
Advance Information
Pin Descriptions
Terminal
Name
Electrical
Characteristics
Description
AGND
AVDD
Analog Ground
Analog power
Ground
1.8 V nominal
CLK_INT
CLK_INC
FB_INT
Clock input with a (10K-100K Ohm) pulldown resistor
Complentary clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Differential input
Differential input
Differential input
FB_INC
FB_OUTT
FB_OUTC
OE
Complementary feedback clock input
Feedback clock output
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
Complementary feedback clock output
Output Enable (Asynchronous)
OS
Output Select (tied to GND or VDDQ
Ground
)
GND
VDDQ
Logic and output power
Clock outputs
1.8V nominal
CLKT[0:9]
CLKC[0:9]
NB
Differential outputs
Differential outputs
Complementary clock outputs
No ball
The PLL clock buffer, ICS97U877, is designed for aVDDQ of 1.8V, a AVDD of 1.8V and differential data input and output
levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC).
The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the
LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except FB_OUTT/
FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a
program pin that must be tied to GND orVDDQ.When OS is high, OE will function as described above.When OS is low,
OEhasnoeffectonCLKT7/CLKC7(theyarefreerunninginadditiontoFB_OUTT/FB_OUTC).WhenAVDD isgrounded,
the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit onthedifferentialinputs, independent from theinput buffers, willdetect thelogic lowlevelandperform
alow powerstatewherealloutputs, thefeedbackandthePLLareOFF.Whentheinputstransitionfrombothbeinglogic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
willobtainphaselockbetweenthefeedbackclockpair(FB_INT, FB_INC)andtheinputclockpair(CLK_INT, CLK_INC)
within the specified stabilization time tSTAB
.
The PLL in ICS97U877 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC)toprovidehigh-performance, low-skew, low-jitteroutputdifferentialclocks(CLKT[0:9], CLKC[0:9]).ICS97U877
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97U877 is characterized for operation from 0°C to 70°C.
0792—07/07/03
2
ICS97U877
Advance Information
Function Table
Inputs
OE OS CLK_INT
Outputs
FB_OUTT
PLL
AVDD
GND
GND
GND
CLK_INT
CLKT
L
CLKC
H
FB_OUTC
H
H
L
X
X
H
L
H
L
H
L
L
H
L
Bypassed/Off
Bypassed/Off
Bypassed/Off
H
L
H
L
H
*L(Z)
*L(Z)
H
*L(Z),
CLKT7
active
*L(Z),
CLKC7
active
L
Bypassed/Off
GND
L
L
L
L
H
L
H
L
L
H
L
H
1.8V(nom)
1.8V(nom)
*L(Z)
*L(Z)
L
H
L
On
On
*L(Z),
CLKT7
active
*L(Z),
CLKC7
active
H
H
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
H
H
X
X
X
X
X
X
L
H
L
H
L
L
H
H
L
L
H
H
L
On
On
Off
L
*L(Z)
*L(Z)
*L(Z)
*L(Z)
H
H
Reserved
*L(Z) means the outputs are disabled to a low stated meeting the IODL limit.
0792—07/07/03
3
ICS97U877
Advance Information
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . . -0.5V to 2.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VDDQ + 0.5V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
Input High Current
(CLK_INT, CLK_INC)
Input Low Current (OE,
OS, FB_INT, FB_INC)
Output Disabled Low
Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
±250
UNITS
µA
IIH
VI = VDDQ or GND
IIL
VI = VDDQ or GND
±10
µA
µA
IODL
OE = L, VODL = 100mV
100
Operating Supply
Current
IDD1.8 CL = 0pf @ 270MHz
300
500
-1.2
mA
µA
V
IDDLD
VIK
CL = 0pf
Input Clamp Voltage
VDDQ = 1.7V Iin = -18mA
IOH = -100 µA
High-level output
voltage
VDDQ - 0.2
1.1
V
VOH
VOL
I
OH = -9 mA
1.45
0.25
V
IOL=100 µA
0.10
0.6
3
V
Low-level output voltage
IOL=9 mA
V
Input Capacitance1
Output Capacitance1
CIN
VI = GND or VDDQ
VOUT = GND or VDDQ
2
2
pF
pF
COUT
3
1Guaranteed by design, not 100% tested in production.
0792—07/07/03
4
ICS97U877
Advance Information
Recommended Operating Condition
(see note1)
TA = 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
1.7
TYP
1.8
MAX
1.9
UNITS
V
VDDQ, AVDD
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.35 x VDDQ
0.35 x VDDQ
V
V
V
V
V
Low level input voltage
High level input voltage
VIL
OE, OS
CLK_INT, CLK_INC, FB_INC,
FB_INT
OE, OS
0.65 x VDDQ
0.65 x VDDQ
-0.3
VIH
VIN
DC input signal voltage
(note 2)
VDDQ + 0.3
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.3
0.6
V
DDQ + 0.4
V
V
V
V
Differential input signal
voltage (note 3)
VID
VDDQ + 0.4
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
VOX
VIX
VDDQ/2 - 0.10
VDDQ/2 + 0.10
VDDQ/2 - 0.15 VDD/2 VDDQ2 + 0.15
High level output current
IOH
IOL
-9
9
mA
mA
Low level output current
Operating free-air
temperature
TA
0
70
°C
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDDQ and is the
voltage at which the differential signal must be crossing.
0792—07/07/03
5
ICS97U877
Advance Information
Timing Requirements
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
freqop
MIN
95
MAX UNITS
Max clock frequency
370
MHz
1.8V+0.1V @ 25°C
Application Frequency
Range
freqApp
dtin
1.8V+0.1V @ 25°C
160
40
350
60
MHz
%
Input clock duty cycle
CLK stabilization
TSTAB
15
µs
Switching Characteristics1
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
Output enable time
Output disable time
Period jitter
SYMBOL
ten
CONDITION
OE to any output
OE to any output
MIN
TYP
4.73
5.82
MAX UNITS
8
8
ns
ns
ps
tdis
tjit (per)
tjit(hper)
-30
30
60
4
Half-period jitter
-60
1
0.5
1.5
0
ps
Input Clock
Output Enable (OE), (OS)
2.5
2.5
v/ns
v/ns
v/ns
ps
Input slew rate
SLr1(i)
Output clock slew rate
Cycle-to-cycle period jitter
3
SLr1(o)
tjit(cc+)
40
-40
20
50
40
33
tjit(cc-)
t( )dyn
0
ps
ps
Dynamic Phase Offset
Static Phase Offset
-20
-50
2
0
ps
tSPO
Output to Output Skew
SSC modulation frequency
SSC clock input frequency
deviation
tskew
ps
30.00
0.00
kHz
-0.50
%
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
MHz
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
0792—07/07/03
6
ICS97U877
Advance Information
Parameter Measurement Information
V
DD
V
(CLKC)
V
(CLKC)
ICS97U877
GND
Figure 1. IBIS Model Output Load
VDD/2
C = 10 pF
ICS97U877
- GND
SCOPE
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 2.97"
R = 1MΩ
C = 1 pF
Z = 120Ω
R = 10Ω
V
(TT)
Z = 50Ω
Z = 60Ω
Z = 2.97"
R = 1MΩ
C = 1 pF
V
(TT)
C = 10 pF
Note: VTT = GND
GND
-VDD/2
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
t
t
c(n+1)
c(n)
t
= t
± t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
0792—07/07/03
7
ICS97U877
Advance Information
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
( ) n
( ) n+1
n = N
t
1
( ) n
t
=
( )
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(skew)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
tC(n)
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
fO
t(jit_per) tc(n)
=
-
Figure 6. Period Jitter
0792—07/07/03
8
ICS97U877
Advance Information
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
jit(hper_n+1)
jit(hper_n)
1
f
o
tjit(hper) = tjit(hper_n)
1
2xfO
-
Figure 7. Half-Period Jitter
80%
80%
V , V
ID OD
20%
20%
Clock Inputs
and Outputs
t
t
slf
slr
Figure 8. Input and Output Slew Rates
0792—07/07/03
9
ICS97U877
Advance Information
CK
CK
FBIN
FBIN
t(
t(
)
)
SSC OFF
SSC OFF
SSC ON
SSC ON
t(
t(
t(
t(
)dyn
)dyn
)dyn
)dyn
Figure 9. Dynamic Phase Offset
50% VDDQ
OE
t
Y
en
50% VDDQ
Y
Y/ Y
OE
50% VDDQ
t
dis
Y
Y
50 % VDDQ
Figure 10. Time delay between OE and Clock Output (Y,Y)
0792—07/07/03
10
ICS97U877
Advance Information
Figure 11. AVDD Filtering
- Place the 2200pF capacitor close to the PLL.
- Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one
GND via (farthest from PLL).
- Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
0792—07/07/03
11
ICS97U877
Advance Information
0.40 DIA.
± 0.15
TYP.
SYMBOL
MIN.
0.86
0.15
0.71
4.40
6.90
NOM.
0.93
0.18
0.75
4.50
MAX.
1.00
0.21
0.79
4.60
7.10
A
A1
A2
D
E
I
J
M
aaa
bbb
ccc
b
Seating
Plane
A1
3 2 1
A
B
C
D
E
F
G
H
I
7.00
0.625 REF.
0.575 REF.
6X10
E
0.10
0.10
0.10
0.45
J
TOP VIEW
D
0.35
0.40
0.15 MIN.
1.00 MAX.
e
0.65 TYP.
Ordering Information
ICS97U877yHT
Example:
ICS XXXX y H - T
Designation for tape and reel packaging
Package Type
H = BGA
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0792—07/07/03
12
ICS97U877
Advance Information
Symbol
Common Dimensions
A
A1
A2
A3
D
-
0.00
-
0.85
0.90
0.05
0.80
0.01
0.65
0.20 REF
6.00 BSC
5.75 BSC
6.00 BSC
5.75 BSC
D1
E
40-Pin MLF
E1
Q
12
P
0.24
0.13
0.42
0.17
0.60
0.23
R
Pitch Varation D
e
N
0.50 BSC
40
Nd
Ne
L
10
10
0.30
0.18
0.00
2.75
2.75
0.40
0.23
0.20
2.90
2.90
0.50
0.30
0.45
3.05
3.05
Ordering Information
b
Q
ICS97U877yKT
D2
E2
Example:
ICS XXXX y K - T
Designation for tape and reel packaging
Package Type
K = MLF
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0792—07/07/03
13
相关型号：
ICS97ULP877AKLFT
97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40, ROHS COMPLIANT, PLASTIC, VFQFN, MLF-40
IDT
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