ICSSSTV16857CGLF-T [IDT]

D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 0.240 INCH, TSSOP-48;


型号：	ICSSSTV16857CGLF-T
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 0.240 INCH, TSSOP-48 光电二极管逻辑集成电路触发器电视
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ICSSSTV16857C

Integrated

Circuit

Systems, Inc.

DDR 14-Bit Registered Buffer

Recommended Applications:

Pin Configuration

•

DDR Memory Modules

•

Provides complete DDR DIMM logic solution with

ICS93V857 or ICS95V857

GND

VDDQ

GND

VDDQ

GND

VDD

CLK#

CLK

VDD

GND

VREF

RESET#

•

SSTL_2 compatible data registers

Product Features:

•

Differential clock signal

•

Meets SSTL_2 signal data

Supports SSTL_2 class I & II specifications

Low-voltage operation

- V_DD= 2.3V to 2.7V

48 pin TSSOP package

VDDQ

GND

•

VDDQ

GND

Q10

Q11

Q12

VDDQ

GND

Q13

Q14

D10

D11

D12

VDD

GND

D13

D14

Truth Table¹

Inputs

CLK CLK#

X or X or

Q Outputs

RESET#

X or

Floating Floating Floating

48-Pin TSSOP & TVSOP

↑

↓

6.10 mm. Body, 0.50 mm. pitch = TSSOP

4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)

L or H

Q₀⁽²⁾

Notes:

H = High Signal Level

L = Low Signal Level

↑ = Transition LOW-to-HIGH

↓ = Transition HIGH -to LOW

X = Irrelevant

Block Diagram

Output level before the indicated

steady state input conditions were

established.

CLK

CLK#

RESET#

CLK

VREF

To 13 Other Channels

0002F—10/25/02

ICSSSTV16857C

General Description

The 14-bit ICSSSTV16857C is a universal bus driver designed for 2.3V to 2.7V V_DDoperation and SSTL_2 I/O levels,

except for the LVCMOS RESET# input.

Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#).The positive edge

of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an

LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16857C supports low-power

standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic

“Low”state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off.Please note that RESET# must always

be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up.

To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic

“Low” level during power up.

In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.

Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,

the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable the

differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power

standby state, the register will become active quickly relative to the time to enable the differential input receivers. When

the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until the

input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.

Pin Configuration

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

24, 23, 20, 19, 18,

15, 14, 11, 10, 7,

6, 5, 2, 1

Q (14:1)

OUTPUT

Data output

3, 8, 13, 22,

27, 36, 46

GND

PWR

Ground

4, 9, 12, 16, 21

VDDQ

Output supply voltage

25, 26, 29, 30, 31,

32, 33, 40, 41, 42,

43, 44, 47, 48

D (14:1)

INPUT

Data input

CLK

CLK#

INPUT

PWR

Positive clock input

Negative clock input

Core supply voltage

Reset (active low)

28, 37, 45

VDD

RESET#

VREF

INPUT

Input reference voltage

0002F—10/25/02

ICSSSTV16857C

Absolute Maximum Ratings

Notes:

Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V

Input Voltage¹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to V_DD+0.5

Output Voltage^1,2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to V_DDQ+0.5

Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA

Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50 mA

Continuous Output Current . . . . . . . . . . . . . . . ±50 mA

V_DD, V_DDQor GND Current/Pin . . . . . . . . . . . . ±100 mA

1. The input and output negative voltage

ratings may be excluded if the input

andoutputclampratingsareobserved.

2. This current will flow only when the

output is in the high state level

V₀>V_DDQ

3. The package thermal impedance is

calculated in accordance with

JESD 51.

Package Thermal Impedance³. . . . . . . . . . . . . . . . 55°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings

are stress specifications only and functional operation of the device at these or any other conditions above those listed in

the operational sections of the specifications is not implied.Exposure to absolute maximum rating conditions for extended

periods may affect product reliability.

Recommended Operating Conditions

DESCRIPTION

PARAMETER

MIN

2.3

TYP

2.5

MAX

2.7

UNITS

Supply Voltage

V_DD

I/O Supply Voltage

V_DDQ

V_REF

2.3

2.5

2.7

Reference Voltage

1.15

1.25

V_REF

1.35

Termination Voltage

Input Voltage

V_TT

V_REF- 0.04

V_REF+ 0.04

V_DDQ

V_I

V_{IH (DC)}

V_{IH (AC)}

V_{IL (DC)}

V_IH

DC Input High Voltage

AC Input High Voltage

DC Input Low Voltage

AC Input Low Voltage

Input High Voltage Level

Input Low Voltage Level

Common mode Input Range

Differential Input Voltage

V_REF+ 0.15

V_REF+ 0.31

Data Inputs

V_REF- 0.15

V_REF- 0.31

1.7

RESET#

V_IL

0.7

V_ICR

0.97

0.36

1.53

CLK, CLK#

V_ID

Cross Point Voltage of Differential Clock

Pair

V_IX

(V_DDQ/2) - 0.2

(V_DDQ/2) + 0.2

High-Level Output Current

Low-Level Output Current

Operating Free-Air Temperature

I_OH

I_OL

T_A

-20

°C

¹Guarenteed by design, not 100% tested in production.

0002F—10/25/02

ICSSSTV16857C

Electrical Characteristics - DC

T_A= 0 - 70º C; V_DD= 2.5 +/-0.2V, V_DDQ=2.5 +/-0.2V; (unless otherwise stated)

CONDITIONS

SYMBOL

V_IK

PARAMETERS

V_DDQ

2.3V

MIN

TYP MAX

-1.2

UNITS

I_I= -18mA

V_DDQ

0.2

_OH= -100µA

2.3V-2.7V

V_OH

_OH= -16mA

2.3V

2.3V-2.7V

2.3V

1.95

I_OL= 100µA

0.2

0.35

±5

V_OL

I_I

I_OL= 16mA

All Inputs

V_I= V_DDor GND

RESET# = GND

V_I= V_IH(AC)or V_IL(AC)

RESET# = V_DD

2.7V

µA

Standby (Static)

0.01

I_DD

Operating (Static)

RESET# = V_DD

Dynamic operating

(clock only)

µA/clock

MHz

V_I= V_IH(AC)or V_IL(AC)

CLK and CLK# switching

50% duty cycle.

I_O= 0

2.7V

RESET# = V_DD

I_DDD

V_I= V_IH(AC)or V_{IL (AC)}

CLK and CLK# switching

50% duty cycle. One data

input switching at half

clock frequency, 50%

duty cycle

Dynamic Operating

(per each data input)

µA/ clock

MHz/data

r_OH

r_OL

Output High

Output Low

I_OH= -20mA

2.3V-2.7V

13.5

Ω

I_OL= 20mA

[r_OH- r_OL] each

separate bit

Data Inputs

r_O(D)

_O= 20mA, T_A= 25° C

2.5V

Ω

V_I= V_REF±350mV

V_ICR= 1.25V, V_I(PP)= 360mV

2.5

3.5

C_i

CLK and CLK#

Notes:

1 - Guaranteed by design, not 100% tested in production.

0002F—10/25/02

ICSSSTV16857C

Timing Requirements¹

(over recommended operating free-air temperature range, unless otherwise noted)

V_DDQ= 2.5±0.2V

SYMBOL

PARAMETERS

UNITS

MIN

MAX

200

2.5

3.5

f_clock

t_PD

t_RST

t_SL

Clock frequency

MHz

Clock to output time

Reset to output time

Output slew rate

Setup time, fast slew rate ^{2 & 4}

Setup time, slow slew rate ^{3 & 4}

Hold time, fast slew rate ^{2 & 4}

Hold time, slow slew rate ^{3 & 4}

1.7

V/ns

0.4

0.5

0.4

0.5

t_S

Data before CLK↑ , CLK#↓

Data after CLK↑ , CLK#↓

T_h

Notes:

1 - Guaranteed by design, not 100% tested in production.

2 - For data signal input slew rate ≥ 1V/ns.

3 - For data signal input slew rate ≥ 0.5V/ns and < 1V/ns.

4 - CLK, CLK# signals input slew rates are ≥ 1V/ns.

Switching Characteristics

(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)

From

(Input)

(Output)

V_DD= 2.5V ±0.2V

SYMBOL

UNITS

MIN

200

1.7

TYP

2.1

MAX

f_max

t_PD

t_phl

MHz

CLK, CLK#

RESET#

2.5

3.5

0002F—10/25/02

ICSSSTV16857C

V_TT

R_L50Ω

From Output

Under Test

Test Point

C_L= 30 pF

(see Note 1)

Load Circuit

LVCMOS

RESET#

Input

V_DDQ

0 V

V_DDQ/2

V_I(pp)

Timing

Input

V_ICR

t_inact

t_act

I_DDH

t_PHL

I_DD

90%

(see note 2)

10%

V_OH

V_OL

I_DDL

V_TT

Voltage and Current Waveforms

Inputs Active and Inactive Times

Output

Voltage Waveforms - Propagation Delay Times

t_w

V_IH

V_IL

Input

V_REF

Voltage Waveforms - Pulse Duration

LVCMOS

RESET#

Input

V_IH

V_I(pp)

VDD/2

V_IL

Timing

Input

V_ICR

t_PHL

V_OH

V_OL

Output

t_h

t_S

V_TT

Voltage Waveforms - Propagation Delay Times

V_IH

V_IL

V_REF

Input

V_REF

Voltage Waveforms - Setup and Hold Times

Figure 1 - Parameter Measurement Information (V

= 2.5V ±0.2V)

DDQ

Notes: 1. CL incluces probe and jig capacitance.

2. I_DDtested with clock and data inputs held at V_DDQor GND, and I_O= 0 mA.

3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,

Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).

4. The outputs are measured one at a time with one transition per measurement.

5. V_TT= V_REF= V_DDQ/2

6. V_IH= V_REF+ 310mV (AC voltage levels) for differential inputs. V_IH= V_DDQfor LVCMOS input.

7. V_IL= V_REF- 310mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS input.

8. t_PLHand t_PHLare the same as t_pd

0002F—10/25/02

ICSSSTV16857C

In Millimeters

In Inches

SYMBOL

COMMON DIMENSIONS COMMON DIMENSIONS

MIN

0.05

0.80

0.17

0.09

MAX

1.20

0.15

1.05

0.27

0.20

MIN

.002

.032

.007

.0035

MAX

.047

.006

.041

.011

.008

INDEX

AREA

SEE VARIATIONS

8.10 BASIC

SEE VARIATIONS

0.319 BASIC

6.00

6.20

.236

0.020 BASIC

.244

0.50 BASIC

0.45

0.75

.018

.030

SEE VARIATIONS

0°

8°

0.10

0°

8°

.004

aaa

VARIATIONS

D mm.

D (inch)

- CC --

MIN

12.40

MAX

12.60

MIN

.488

MAX

.496

SEATING

PLANE

Reference Doc.: JEDEC Publication 95, M O-153

aaa

10-0039

6.10 mm. Body, 0.50 mm. pitch TSSOP

(0.020 mil)

(240 mil)

Ordering Information

ICSSSTV16857CG-T

Example:

ICS XXXX y G - PPP - T

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code

patterns)

Package Type

G=TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

0002F—10/25/02

ICSSSTV16857C

In Millimeters

In Inches

SYMBOL

COMMON DIMENSIONS COMMON DIMENSIONS

MIN

0.05

0.80

0.13

0.09

MAX

1.20

0.15

1.05

0.23

0.20

MIN

.002

.032

.005

.0035

MAX

.047

.006

.041

.009

.008

INDEX

AREA

SEE VARIATIONS

6.40 BASIC

SEE VARIATIONS

0.252 BASIC

4.30

4.50

.169

0.016 BASIC

.177

0.40 BASIC

0.45

0.75

.018

.030

SEE VARIATIONS

0°

8°

0.08

0°

8°

.003

aaa

VARIATIONS

D mm.

D (inch)

- CC --

MIN

9.60

MAX

9.80

MIN

.378

MAX

.386

SEATING

PLANE

Reference Doc.: JEDEC P ublicatio n 95, M O-153

aaa

10-0037

4.40 mm. Body, 0.40 mm. pitch TSSOP

(16 mil)

(173 mil)

Ordering Information

ICSSSTV16857CL-T

Example:

ICS XXXX y L - PPP - T

Designation for tape and reel packaging

Pattern Number (2 or 3 digit number for parts with ROM code

patterns)

Package Type

L = TSSOP (TVSOP)

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

0002F—10/25/02

ICSSSTV16857CGLF-T [IDT]

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