IDT71128S20YG8 [IDT]
Standard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, GREEN, PLASTIC, SOJ-32;
| 型号： | IDT71128S20YG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 256KX4, 20ns, CMOS, PDSO32, 0.400 INCH, GREEN, PLASTIC, SOJ-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Static RAM
1 Meg (256K x 4-Bit)
Revolutionary Pinout
IDT71128
Description
Features
◆
The IDT71128 is a 1,048,576-bit high-speed static RAM
organized as 256K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability CMOS technology. This state-of-the-art
technology, combined with innovative circuit design techniques,
provides a cost-effective solution for high-speed memory needs.
The JEDEC centerpower/GND pinout reduces noise generation
and improves system performance.
256K x 4 advanced high-speed CMOS static RAM
◆
JEDEC revolutionary pinout (center power/GND) for
reduced noise.
Equal access and cycle times
◆
— Commercial and Industrial: 12/15/20ns
One Chip Select plus one Output Enable pin
Bidirectional inputs and outputs directly
◆
◆
The IDT71128 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71128 are TTL-compat-
ible and operation is from a single 5V supply. Fully static asyn-
chronous circuitry is used; no clocks or refreshes are required for
operation.
TTL-compatible
Low power consumption via chip deselect
Available in a 32-pin 400 mil Plastic SOJ.
◆
◆
The IDT71128 is packaged in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A0
1,048,576-BIT
MEMORY
ARRAY
ADDRESS
DECODER
.
A17
4
4
I/O0 - I/O3
I/O CONTROL
CS
WE
OE
CONTROL
LOGIC
3483 drw 01
FEBRUARY 2001
DSC-3483/09
1
©2000IntegratedDeviceTechnology,Inc.
IDT71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Pin Configuration
Absolute Maximum Ratings(1)
Symbol
Rating
Value
Unit
A
A
17
16
NC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(2)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +7.0(2)
V
A
A
A
A
CS
0
1
2
2
3
4
5
A15
A
A
14
13
TA
Operating Temperature
0 to +70
oC
oC
3
Temperature
Under Bias
-55 to +125
TBIAS
OE
I/O
GND
6
SO32-3
3
I/O0
7
VCC
Storage
-55 to +125
oC
TSTG
8
Temperature
VCC
GND
9
I/O1
I/O
A
2
10
11
12
13
14
15
16
P
T
Power Dissipation
DC Output Current
1.25
50
W
WE
12
IOUT
mA
A4
A11
A10
A9
A
5
6
3483 tbl 02
NOTES:
A
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation
ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational
sections of this specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability.
A7
A8
NC
NC
3483 drw 02
2. VTERM mustnotexceedVcc+0.5V.
SOJ
Top View
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Truth Table(1,2)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
I/O
Function
CS
OE
WE
CIN
V
8
8
pF
L
L
H
DATAOUT Read Data
DATAIN Write Data
High-Z Output Disabled
CI/O
V
pF
L
X
H
X
L
3483 tbl 03
NOTE:
L
H
1. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.
H
X
High-Z Deselected - Standby (ISB
)
(3)
HC
X
X
High-Z Deselected - Standby (ISB1)
V
Recommended Operating
3483 tbl 01
NOTES:
Temperature and Supply Voltage
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VCC -0.2V.
3. Other inputs ≥VHC or ≤VLC.
Grade
Temperature
0°C to +70°C
–40°C to +85°C
GND
VCC
Commercial
Industrial
0V
5.0V ± 10%
0V
5.0V ± 10%
3483 tbl 04
Recommended DC Operating
Conditions
Symbol
Parameter
Supply Voltage
GND Ground
Min.
4.5
Typ.
Max.
5.5
0
Unit
V
VCC
5.0
0
0
V
____
V
IH
Input High Voltage
Input Low Voltage
2.2
V
CC +0.5
V
VIL
-0.5(1)
0.8
V
____
3483 tbl 05
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
6.42
2
IDT 71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
Unit
µA
µA
V
Symbol
Parameter
Test Conditions
CC = Max., VIN = GND to VCC
CC = Max., CS = VIH, VOUT = GND to VCC
OL = 8mA, VCC = Min.
OH = -4mA, VCC = Min.
Min.
Max.
___
|ILI|
Input Leakage Current
V
5
5
___
___
|ILO
|
Output Leakage Current
Output Low Voltage
Output High Voltage
V
VOL
I
0.4
___
VOH
I
2.4
V
3483 tbl 06
DC Electrical Characteristics(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71128S12
71128S15
Com'l.
71128S20
Symbol
Parameter
Dynamic Operating Current
Com'l.
Ind.
Ind.
Com'l.
Ind.
Unit
155
155
150
150
145
145
mA
ICC
(2)
CS < VIL, Outputs Open, VCC = Max., f = fMAX
Standby Power Supply Current (TTL Level)
40
10
40
10
40
40
10
40
10
40
10
mA
mA
I
SB
(2)
CS > VIH, Outputs Open, VCC = Max., f = fMAX
Full Standby Power Supply Current (CMOS Level)
10
ISB1
CS > VHC, Outputs Open, VCC = Max., f = 0(2)
VIN < VLC or VIN > VHC
3483 tbl 07
NOTES:
1. Allvaluesaremaximumguaranteedvalues.
2. fMAX=1/tRC (alladdress inputs are cyclingatfMAX); f=0means noaddress inputlines are changing.
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
3ns
1.5V
1.5V
See Figure 1 and 2
3483 tbl 08
AC Test Loads
5V
5V
480Ω
480Ω
255Ω
OUT
DATA
OUT
DATA
5pF*
255Ω
30pF
3483 drw 04
3483 drw 03
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
6.42
3
IDT71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges)
71128S12
71128S15
71128S20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACS
Read Cycle Time
12
15
20
ns
ns
ns
ns
____
____
____
t
Address Access Time
12
15
20
____
____
____
t
Chip Select Access Time
Chip Select to Output in Low-Z
12
15
20
____
____
____
(1)
3
3
3
tCLZ
(1)
Chip Deselect to Output in High-Z
Output Enable to Output Valid
0
6
0
7
0
8
ns
ns
ns
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
6
7
8
____
____
____
(1)
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
0
0
4
0
0
4
0
0
4
tOLZ
(1)
OHZ
5
5
7
t
____
____
____
tOH
____
____
____
(1)
PU
0
0
0
t
____
____
____
(1)
PD
12
15
20
t
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
AS
WP
WR
DW
DH
Write Cycle Time
12
10
10
0
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End of Write
Chip Select to End of Write
Address Set-up Time
Write Pulse Width
t
t
t
10
0
12
0
15
0
t
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
t
7
8
9
t
0
0
0
____
____
____
(1)
OW
Output active from End-of-Write
3
3
4
t
(1)
WHZ
Write Enable to Output in High-Z
0
5
0
5
0
8
ns
t
3483 tbl 09
NOTE:
1. This parameterguaranteedwiththeACload(Figure2)bydevicecharacterization,butis notproductiontested.
6.42
4
IDT 71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
OE
tAA
tOE
(5)
tOLZ
CS
(3)
tACS
(5)
(5)
t
OHZ
t
CLZ
(5)
CHZ
t
HIGH IMPEDANCE
DATAOUT
DATAOUT VALID
t
PD
t
PU
I
I
CC
SB
V
CC SUPPLY
CURRENT
3483 drw 05
Timing Waveform of Read Cycle No. 2(1, 2, 4)
t
RC
ADDRESS
tAA
t
OH
tOH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
3483 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Deviceiscontinuouslyselected, CSisLOW.
3. AddressmustbevalidpriortoorcoincidentwiththelaterofCStransitionLOW;otherwisetAA isthelimitingparameter.
4. OEisLOW.
5. Transitionismeasured±200mVfromsteadystate.
6.42
5
IDT71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1, 2, 4)
tWC
ADDRESS
tAW
CS
(2)
tWR
tAS
tWP
WE
(5)
(5)
tCHZ
(5)
tWHZ
tOW
HIGH IMPEDANCE
(3)
(3)
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
3483 drw 07
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)
tWC
ADDRESS
CS
tAW
tWR
tCW
tAS
WE
tDW
tDH
DATAIN
DATAIN VALID
3483 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OEis continuouslyHIGH. DuringaWEcontrolledwritecyclewithOELOW,tWP mustbegreaterthanorequaltotWHZ+tDW toallowtheI/Odriverstoturnoffanddatatobeplaced
onthe bus forthe requiredtDW. IfOEis HIGHduringa WEcontrolledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. IftheCSLOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahighimpedancestate. CSmustbeactiveduringthetCW writeperiod.
5. Transitionismeasured±200mVfromsteadystate.
6.42
6
IDT 71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Ordering Information
IDT
71128
S
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Y
400-mil SOJ (SO32-3)
12
15
20
Speed in nanoseconds
3483 drw 09
6.42
7
IDT71128 CMOS Static RAM
1 Meg (256K x 4-bit) Revolutionary Pinout
Commercial and Industrial Temperature Ranges
Datasheet Document History
8/5/99
Updated to new format
Removed military entries from DC table
Pg. 3
Pg. 4
Pg. 6
Pg. 8
Removed Note 1, renumbered notes and footnotes
Removed Note 1, renumbered notes and footnotes
Added Datasheet Document History
8/13/99
9/30/99
2/18/00
3/14/00
8/09/00
02/01/01
Pg. 1, 3, 4, 7
Pg. 3
Pg. 3
Added12ns,15ns,and20nsindustrialtemperaturespeedgradeofferings
ReviseISB forIndustrialTemperatureofferingstomeetcommericalspecifications
RevisedISB toaccomidatespeedfunctionality
Notrecommendedfornewdesigns
Removed"Notrecommendedfornewdesigns"
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www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
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