IDT71V2577S85PF8 [IDT]

Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100;
IDT71V2577S85PF8
型号: IDT71V2577S85PF8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

时钟 静态存储器 内存集成电路
文件: 总23页 (文件大小:518K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
128K x 36, 256K x 18  
IDT71V2577  
IDT71V2579  
3.3V Synchronous SRAMs  
2.5V I/O, Flow-Through Outputs  
Burst Counter, Single Cycle Deselect  
Description  
Features  
The IDT71V2577/79 are high-speed SRAMs organized as  
128Kx36/256Kx18.TheIDT71V2577/79SRAMs containwrite,data,  
address andcontrolregisters.Therearenoregisters inthedataoutput  
path (flow-through architecture). Internal logic allows the SRAM to  
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil  
128K x 36, 256K x 18 memory configurations  
Supports fast access times:  
Commercial:  
– 7.5ns up to 117MHz clock frequency  
CommercialandIndustrial:  
– 8.0ns up to 100MHz clock frequency  
– 8.5ns up to 87MHz clock frequency  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O  
theendofthewritecycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V2577/79canprovidefourcyclesofdata  
fora single address presentedtothe SRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe  
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof  
the same cycle. If burst mode operation is selected (ADV=LOW), the  
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe  
next three rising clock edges. The order of these three addresses are  
definedbytheinternalburstcounterandtheLBOinputpin.  
Packaged in a JEDEC Standard 100-pin plastic thin quad  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball  
grid array (fBGA)  
The IDT71V2577/79 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
0
17  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Chip Enable  
CE  
0
1
CS , CS  
Chip Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
GW  
BWE  
(1)  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV  
ADSC  
ADSP  
LBO  
Clock  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
N/A  
Synchronous  
Synchronous  
Synchronous  
DC  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
ZZ  
Asynchronous  
Synchronous  
N/A  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Data Input / Output  
DD DDQ  
V , V  
Core Power, I/O Power  
Ground  
Supply  
Supply  
SS  
V
N/A  
4877 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V2579.  
OCTOBER 2000  
1
©2000ntegratedDeviceTechnology,Inc.  
DSC-4877/06  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
PinDefinition(1)  
Symbol  
Pin Function  
I/O  
Active  
Description  
0
17  
A -A  
Address Inputs  
I
N/A  
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising  
edge of CLK and ADSC Low or ADSP Low and CE Low.  
Address Status  
(Cache Controller)  
I
I
I
LOW  
LOW  
LOW  
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is  
ADSC  
ADSP  
ADV  
used to load the address registers with new addresses.  
Address Status  
(Processor)  
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to  
load the address registers with new addresses. ADSP is gated by CE.  
Burst Address  
Advance  
Synchronous Address Advance. ADV is an active LOW input that is used to advance the  
internal burst counter, controlling burst access after the initial address is loaded. When the  
input is HIGH the burst counter is not incremented; that is, there is no address advance.  
1
4
Byte Write Enable  
I
LOW  
Synchronous byte write enable gates the byte write inputs BW -BW . If BWE is LOW at the  
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is  
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.  
BWE  
1
0-7  
P1  
2
8-15  
P2  
Individual Byte  
Write Enables  
I
I
I
LOW  
LOW  
N/A  
Synchronous byte write enables. BW controls I/O , I/O , BW controls I/O , I/O , etc.  
1
4
BW -BW  
Any active byte write causes all outputs to be disabled.  
0
1
Chip Enable  
Synchronous chip enable. CE is used with CS and CS to enable the IDT71V2577/79. CE  
CE  
also gates ADSP.  
CLK  
Clock  
This is the clock input. All timing references for the device are made with respect to this  
input.  
0
0
1
CS  
Chip Select 0  
Chip Select 1  
I
I
I
HIGH Synchronous active HIGH chip select. CS is used with CE and CS to enable the chip.  
1
0
LOW  
LOW  
Synchronous active LOW chip select. CS is used with CE and CS to enable the chip.  
1
CS  
Global Write  
Enable  
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on  
the rising edge of CLK. GW supersedes individual byte write enables.  
GW  
0
31  
I/O -I/O  
Data Input/Output  
I/O  
I
N/A  
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the  
rising edge of CLK. The data output path is flow-through (no output register).  
P1  
P4  
I/O -I/O  
Linear Burst Order  
LOW  
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst  
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a  
static input and must not change state while the device is operating.  
LBO  
Output Enable  
I
LOW  
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the  
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance  
state.  
OE  
DD  
V
Power Supply  
Power Supply  
Ground  
N/A  
N/A  
N/A  
N/A  
1
N/A  
N/A  
3.3V core power supply.  
DDQ  
V
2.5V I/O Supply.  
SS  
V
N/A  
Ground.  
NC  
ZZ  
No Connect  
Sleep Mode  
N/A  
NC pins are not electrically connected to the device.  
HIGH  
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the  
IDT71V2577/79 to its lowest power consumption level. Data retention is guaranteed in  
Sleep Mode.  
4877 tbl 02  
NOTE:  
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.  
6.42  
2
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
FunctionalBlockDiagram  
LBO  
ADV  
CEN  
INTERNAL  
ADDRESS  
128K x 36/  
256K x 18-  
BIT  
MEMORY  
ARRAY  
CLK  
2
Burst  
Logic  
17/18  
Binary  
Counter  
ADSC  
A0*  
A1*  
Q0  
Q1  
CLR  
ADSP  
2
CLK EN  
A0,A1  
A2 - A17  
ADDRESS  
REGISTER  
A0 - A16/17  
GW  
36/18  
36/18  
17/18  
BWE  
Byte 1  
Write Register  
Byte 1  
Write Driver  
BW1  
BW2  
9
9
Byte 2  
Write Register  
Byte 2  
Write Driver  
Byte 3  
Write Register  
Byte 3  
Write Driver  
3
BW  
9
9
Byte 4  
Write Register  
Byte 4  
Write Driver  
BW4  
CE  
Q
D
CS0  
CS1  
Enable  
DATA INPUT  
REGISTER  
Register  
CLK EN  
ZZ  
Powerdown  
OE  
OUTPUT  
BUFFER  
OE  
,
36/18  
I/O0 - I/O31  
I/OP1 - I/OP4  
4877 drw 01  
6.42  
3
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
AbsoluteMaximumRatings(1)  
RecommendedOperating  
TemperatureandSupplyVoltage  
Commerical &  
Industrial Values  
Symbol  
Rating  
Unit  
Temperature(1)  
0°C to +70°C  
-40°C to +85°C  
V
V
SS  
DD  
DDQ  
V
Grade  
(2)  
TERM  
V
Terminal Voltage with  
Respect to GND  
-0.5 to +4.6  
V
Commercial  
Industrial  
0V  
0V  
3.3V±5%  
3.3V±5%  
2.5V±5%  
2.5V±5%  
(3,6)  
(4,6)  
(5,6)  
TERM  
DD  
V
Terminal Voltage with  
Respect to GND  
-0.5 to V  
V
V
4877 tbl 04  
NOTES:  
1. TA is the instant on” case temperature.  
TERM  
V
DD  
Terminal Voltage with  
Respect to GND  
-0.5 to V +0.5  
TERM  
V
DDQ  
Terminal Voltage with  
Respect to GND  
-0.5 to V +0.5  
V
RecommendedDCOperating  
Conditions  
Commercial  
Operating Temperature  
-0 to +70  
-40 to +85  
-55 to +125  
-55 to +125  
oC  
oC  
oC  
oC  
W
Symbol  
VDD  
VDDQ  
VSS  
Parameter  
Core Supply Voltage  
I/O Supply Voltage  
Supply Voltage  
Min.  
3.135  
2.375  
0
Typ.  
Max.  
Unit  
V
(7)  
A
T
3.3  
3.465  
2.625  
0
Industrial  
Operating Temperature  
2.5  
V
BIAS  
T
Temperature  
Under Bias  
0
V
____  
VIH  
Input High Voltage - Inputs  
Input High Voltage - I/O  
Input Low Voltage  
1.7  
VDD + 0.3  
V
STG  
T
Storage  
(1)  
____  
____  
VIH  
1.7  
VDDQ + 0.3  
V
Temperature  
(2)  
VIL  
-0.3  
0.7  
V
T
P
Power Dissipation  
DC Output Current  
2.0  
50  
4877 tbl 05  
NOTES:  
OUT  
I
mA  
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.  
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.  
4877 tbl 03  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated  
in the operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect reliability.  
2. VDD terminals only.  
3. VDDQ terminals only.  
4. Input terminals only.  
5. I/O terminals only.  
6. This is a steady-state DC parameter that applies after the power supplies have  
ramped up. Power supply sequencing is not necessary; however, the voltage  
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.  
7. TA is the instant on” case temperature.  
100PinTQFPCapacitance  
(TA = +25°C, f = 1.0MHz)  
119BGACapacitance  
(TA = +25°C, f = 1.0MHz)  
Symbol  
Parameter(1)  
Input Capacitance  
I/O Capacitance  
Conditions  
VIN = 3dV  
VOUT = 3dV  
Max. Unit  
Symbol  
Parameter(1)  
Input Capacitance  
I/O Capacitance  
Conditions  
VIN = 3dV  
VOUT = 3dV  
Max. Unit  
CIN  
7
7
pF  
CIN  
5
7
pF  
CI/O  
pF  
CI/O  
pF  
4877 tbl 07a  
4877 tbl 07  
165fBGACapacitance  
(TA = +25°C, f = 1.0MHz)  
Symbol  
Parameter(1)  
Input Capacitance  
I/O Capacitance  
Conditions  
VIN = 3dV  
VOUT = 3dV  
Max. Unit  
CIN  
TBD  
TBD  
pF  
CI/O  
pF  
4877 tbl 07b  
NOTE:  
1. This parameter is guaranteed by device characterization, but not production tested.  
6.42  
4
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Pin Configuration – 128K x 36  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
1
80  
79  
78  
77  
I/OP2  
I/O15  
I/O14  
VDDQ  
VSS  
I/O13  
I/O12  
I/O11  
I/O10  
VSS  
VDDQ  
I/O9  
I/O8  
VSS  
NC  
I/OP3  
2
I/O16  
I/O17  
VDDQ  
VSS  
I/O18  
I/O19  
I/O20  
I/O21  
VSS  
3
4
5
76  
75  
74  
73  
6
7
8
9
72  
71  
70  
69  
68  
67  
66  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VDDQ  
I/O22  
I/O23  
(1)  
VSS  
VDD  
NC  
VSS  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
VDD  
ZZ(3)  
I/O7  
I/O6  
VDDQ  
VSS  
I/O24  
I/O25  
VDDQ  
VSS  
I/O26  
I/O27  
I/O28  
I/O29  
VSS  
VDDQ  
I/O30  
I/O31  
I/OP4  
I/O5  
I/O4  
I/O3  
I/O2  
VSS  
VDDQ  
I/O1  
I/O0  
I/OP1  
,
31  
33 34 35 36  
38 39 40 41 42 43 44 45 46 47 48 49 50  
37  
32  
4877 drw 02a  
100TQFP  
Top View  
NOTES:  
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.  
2. Pins 38 and 39 can be either NC or connected to VSS.  
3. Pin 64 can be left unconnected and the device will always remain in active mode.  
6.42  
5
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Pin Configuration – 256K x 18  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
1
80  
79  
A10  
NC  
NC  
NC  
NC  
NC  
VDDQ  
VSS  
NC  
NC  
I/O8  
I/O9  
VSS  
2
3
78  
77  
4
VDDQ  
VSS  
NC  
I/OP1  
I/O7  
I/O6  
VSS  
VDDQ  
I/O5  
I/O4  
VSS  
NC  
VDD  
ZZ(3)  
I/O3  
I/O2  
VDDQ  
VSS  
5
76  
75  
74  
73  
6
7
8
9
72  
71  
70  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VDDQ  
69  
68  
67  
66  
I/O10  
I/O11  
(1)  
VSS  
VDD  
NC  
VSS  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
I/O12  
I/O13  
VDDQ  
VSS  
I/O14  
I/O15  
I/OP2  
NC  
VSS  
VDDQ  
NC  
NC  
I/O1  
I/O0  
NC  
NC  
VSS  
VDDQ  
NC  
NC  
NC  
,
52  
51  
NC  
31  
33 34 35 36  
38 39 40 41 42 43 44 45 46 47 48 49 50  
37  
32  
4877 drw 02b  
100TQFP  
Top View  
NOTES:  
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.  
2. Pins 38 and 39 can be either NC or connected to VSS.  
3. Pin 64 can be left unconnected and the device will always remain in active mode.  
6.42  
6
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Pin Configuration – 128K x 36, 119 BGA  
1
2
3
4
5
6
7
DDQ  
6
4
8
16  
DDQ  
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
ADSP  
ADSC  
3
2
9
1
CS  
NC  
NC  
CS  
NC  
NC  
0
7
A
DD  
V
12  
15  
A
A
16  
I/O  
P3  
I/O  
SS  
SS  
SS  
SS  
SS  
SS  
P2  
I/O  
15  
I/O  
V
V
V
NC  
CE  
V
V
V
17  
I/O  
18  
I/O  
13  
I/O  
14  
I/O  
DDQ  
20  
19  
I/O  
12  
I/O  
DDQ  
V
V
OE  
21  
I/O  
3
2
BW  
11  
I/O  
10  
I/O  
I/O  
G
H
J
BW  
ADV  
GW  
22  
I/O  
23  
I/O  
SS  
SS  
9
I/O  
8
I/O  
V
V
DDQ  
V
DD  
DD  
V
DD  
DDQ  
7
V
NC  
NC  
V
V
24  
I/O  
26  
I/O  
SS  
V
SS  
V
6
I/O  
CLK  
I/O  
K
L
(2)  
25  
I/O  
27  
I/O  
4
1
BW  
4
I/O  
5
I/O  
NC  
BW  
DDQ  
28  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
3
DDQ  
1
V
I/O  
V
V
V
V
V
V
V
I/O  
V
M
N
P
R
T
BWE  
29  
I/O  
30  
I/O  
1
A
2
I/O  
I/O  
31  
P4  
I/O  
0
A
0
I/O  
P1  
I/O  
NC  
NC  
I/O  
NC  
5
DD  
11  
13  
A
A
V
LBO  
(3)  
10  
A
14  
A
,
NC  
DNU  
A
NC  
ZZ  
(4)  
(4)  
(4)  
(2,4)  
(4)  
DDQ  
V
DNU  
DDQ  
V
DNU  
DNU  
DNU  
U
4877 drw 02c  
Top View  
Pin Configuration – 256K x 18, 119 BGA  
1
2
3
4
5
6
7
DDQ  
6
4
8
16  
A
DDQ  
V
A
B
C
D
E
F
V
A
A
A
A
A
A
ADSP  
ADSC  
3
2
9
1
CS  
NC  
NC  
CS  
NC  
NC  
NC  
0
7
DD  
V
13  
17  
A
A
A
8
I/O  
SS  
SS  
SS  
2
SS  
SS  
SS  
SS  
SS  
7
NC  
V
V
V
NC  
CE  
V
V
V
V
V
I/O  
NC  
9
6
I/O  
NC  
I/O  
NC  
DDQ  
V
5
DDQ  
V
I/O  
NC  
OE  
10  
I/O  
4
G
H
J
NC  
I/O  
NC  
BW  
ADV  
GW  
11  
I/O  
SS  
3
I/O  
NC  
V
DDQ  
V
DD  
12  
DD  
V
DD  
DDQ  
V
V
NC  
NC  
V
SS  
V
SS  
V
2
K
L
NC  
I/O  
NC  
CLK  
NC  
I/O  
NC  
(2)  
SS  
V
13  
I/O  
1
BW  
1
I/O  
NC  
DDQ  
15  
14  
SS  
SS  
SS  
SS  
SS  
SS  
DDQ  
V
V
I/O  
NC  
V
V
V
V
V
NC  
M
N
P
R
T
BWE  
1
A
0
I/O  
I/O  
NC  
P2  
I/O  
0
A
P1  
I/O  
NC  
V
NC  
5
DD  
V
SS  
14  
12  
11  
NC  
NC  
DDQ  
A
V
A
NC  
LBO  
(3)  
10  
15  
A
ZZ  
A
NC  
A
A
(4)  
(4)  
(2,4)  
(4)  
(4)  
,
DDQ  
V
V
DNU  
DNU  
DNU  
DNU  
DNU  
U
4877 drw 02d  
NOTES:  
Top View  
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.  
2. L4 and U4 can be either NC or connected to VSS.  
3. T7 can be left unconnected and the device will always remain in active mode.  
4. DNU = Do not use U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TDI, TDO, TMS, TCK and TRST on future revisions. Within the current  
version these pins are not connected.  
6.42  
7
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Pin Configuration – 128K x 36, 165 fBGA  
1
2
3
4
5
6
7
8
9
10  
A8  
11  
(4)  
A
B
C
D
E
F
NC  
A7  
NC  
CE1  
BW3  
BW4  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
A2  
BW2  
BW1  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
CS1  
CLK  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
BWE  
GW  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
ADSC  
OE  
ADV  
(4)  
NC  
A6  
CS0  
A9  
NC  
ADSP  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
I/OP3  
I/O17  
I/O19  
I/O21  
I/O23  
VSS(1)  
I/O25  
I/O27  
I/O29  
I/O31  
I/OP4  
NC  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
A10  
NC  
I/OP2  
I/O14  
I/O12  
I/O10  
I/O8  
I/O16  
I/O18  
I/O20  
I/O22  
I/O15  
I/O13  
I/O11  
I/O9  
NC  
G
H
J
(2)  
(3)  
NC  
ZZ  
I/O24  
I/O26  
I/O28  
I/O30  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
A5  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
A13  
I/O7  
I/O5  
I/O3  
I/O1  
NC  
I/O6  
I/O4  
I/O2  
I/O0  
I/OP1  
K
L
M
N
P
(5)  
(4)  
(2)  
DNU  
NC  
NC  
(4)  
(5)  
(5)  
(4)  
NC  
DNU  
A1  
A0  
DNU  
A14  
A15  
NC  
(4)  
(5)  
(5)  
R
NC  
A4  
A3  
DNU  
DNU  
A11  
A12  
A16  
LBO  
4877 tbl 17  
Pin Configuration – 256K x 18, 165 fBGA  
1
2
3
4
5
6
7
8
9
10  
A8  
11  
(4)  
A
B
C
D
E
F
NC  
NC  
NC  
NC  
NC  
NC  
NC  
A7  
NC  
A10  
CE  
BW2  
NC  
CS1  
CLK  
VSS  
VSS  
VSS  
VSS  
VSS  
BWE  
GW  
VSS  
VSS  
VSS  
VSS  
VSS  
ADSC  
OE  
ADV  
(4)  
A6  
CS0  
A9  
NC  
BW1  
VSS  
VSS  
VSS  
VSS  
VSS  
ADSP  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
VSS  
VDD  
VDD  
VDD  
VDD  
VSS  
VDD  
VDD  
VDD  
VDD  
NC  
NC  
NC  
NC  
NC  
NC  
I/O3  
I/OP1  
I/O7  
I/O6  
I/O5  
I/O4  
I/O8  
I/O9  
I/O10  
I/O11  
G
H
J
(1)  
(2)  
(3)  
V
NC  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
ZZ  
SS  
I/O12  
NC  
NC  
NC  
NC  
NC  
VDDQ  
VDD  
VSS  
VSS  
VSS  
VDD  
VDDQ  
NC  
NC  
NC  
NC  
NC  
K
L
M
N
P
I/O  
13  
V
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
I/O  
2
DDQ  
DDQ  
I/O14  
I/O15  
I/OP2  
NC  
VDDQ  
VDDQ  
VDDQ  
A5  
VDD  
VDD  
VSS  
A2  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VSS  
A11  
VDDQ  
VDDQ  
VDDQ  
A14  
I/O1  
I/O0  
NC  
(5)  
(4)  
(2)  
DNU  
NC  
NC  
(4)  
(5)  
(5)  
(4)  
NC  
DNU  
A1  
DNU  
A15  
NC  
(4)  
(5)  
(5)  
R
NC  
A
4
A
3
DNU  
A
0
DNU  
A
12  
A
13  
A
16  
A
17  
LBO  
4877 tbl 17a  
NOTES:  
1. H1 does not have to be directly VSS as long as input voltage is < VIL.  
2. H2 and N7 can be either NC or connected to VSS.  
3. H11 can be left unconnected and the device will always remain in active mode.  
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.  
5. DNU = Do not use; Pins P5, P7, R5, R7 and N5 are reserved for respective JTAG pins: TDI, TDO, TMS, TCK and TRST on future revisions. Within the  
current version these pins are not connected.  
6.42  
8
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)  
Symbol  
Parameter  
Test Conditions  
Min.  
Max.  
Unit  
___  
|ILI|  
Input Leakage Current  
VDD = Max., VIN = 0V to VDD  
5
µA  
(1)  
___  
___  
___  
ZZ and LBO Input Leakage Current  
Output Leakage Current  
Output Low Voltage  
LI  
DD  
IN  
DD  
|I |  
V
= Max., V = 0V to V  
30  
5
µA  
µA  
V
|ILO|  
VOUT = 0V to VDDQ, Device Deselected  
IOL = +6mA, VDD = Min.  
VOL  
0.4  
___  
OH  
V
OH  
I
DD  
Output High Voltage  
= -6mA, V = Min.  
2.0  
V
4877 tbl 08  
NOTE:  
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range(1)  
7.5ns  
8ns  
8.5ns  
Com'l  
Symbol  
Parameter  
Test Conditions  
Com'l Only Com'l  
Ind  
Ind  
Unit  
Operating Power Supply Current  
Device Selected, Outputs Open, VDD = Max.,  
VDDQ = Max., VIN > VIH or < VIL, f = fMAX  
255  
30  
200  
30  
210  
180  
190  
mA  
IDD  
(2)  
ISB1  
CMOS Standby Power Supply  
Current  
Device Deselected, Outputs Open, VDD = Max.,  
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)  
35  
95  
35  
30  
35  
90  
35  
mA  
mA  
SB2  
I
DD  
Clock Running Power Supply  
Current  
Device Deselected, Outputs Open, V = Max.,  
90  
85  
80  
(2,3)  
VDDQ = Max., VIN > VHD or < VLD, f = fMAX  
IZZ  
Full Sleep Mode Supply Current  
ZZ > VHD, VDD = Max.  
30  
30  
30  
mA  
4877 tbl 09  
NOTES:  
1. All values are maximum guaranteed values.  
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.  
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.  
AC Test Conditions  
AC Test Load  
V
DDQ/2  
(VDDQ = 2.5V)  
50  
Input Pulse Levels  
0 to 2.5V  
2ns  
I/O  
0  
Z = 50  
Input Rise/Fall Times  
,
Input Timing Reference Levels  
Output Timing Reference Levels  
AC Test Load  
(VDDQ/2)  
(VDDQ/2)  
See Figure 1  
4877d03  
Figure 1. AC Test Load  
6
5
4
4877 tbl 10  
3
tCD  
(Typical, ns)  
2
1
,
20 30 50  
80 100  
Capacitance (pF)  
200  
4877d05  
Figure 2. Lumped Capacitive Load, Typical Derating  
6.42  
9
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
SynchronousTruthTable(1,3)  
CE  
CS  
1
ADSP ADSC ADV  
GW  
BWE BW  
x
OE(2)  
Operation  
Address  
CS  
0
CLK  
I/O  
Used  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Deselected Cycle, Power Down  
Read Cycle, Begin Burst  
None  
None  
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
HI-Z  
HI-Z  
HI-Z  
HI-Z  
HI-Z  
None  
L
L
None  
L
X
L
X
X
L
None  
L
L
External  
External  
External  
External  
External  
External  
External  
Next  
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
D
OUT  
Read Cycle, Begin Burst  
L
L
L
H
L
HI-Z  
Read Cycle, Begin Burst  
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
D
OUT  
Read Cycle, Begin Burst  
L
L
L
L
D
OUT  
Read Cycle, Begin Burst  
L
L
L
L
H
X
X
L
HI-Z  
Write Cycle, Begin Burst  
L
L
L
L
D
IN  
IN  
OUT  
HI-Z  
Write Cycle, Begin Burst  
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
Next  
L
H
L
Next  
L
D
OUT  
Next  
L
H
L
HI-Z  
Next  
L
D
OUT  
Next  
L
H
L
HI-Z  
Next  
L
D
OUT  
Next  
L
H
X
X
X
X
L
HI-Z  
Next  
L
D
IN  
IN  
IN  
IN  
OUT  
HI-Z  
Next  
L
X
L
X
L
D
Next  
L
H
L
D
Next  
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
H
L
D
OUT  
H
L
HI-Z  
D
OUT  
H
L
HI-Z  
D
OUT  
H
X
X
X
X
HI-Z  
D
IN  
IN  
IN  
IN  
4877 tbl 11  
X
L
X
L
D
H
L
D
X
X
D
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. OE is an asynchronous input.  
3. ZZ = low for this table.  
6.42  
10  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Synchronous Write Function Truth Table(1, 2)  
GW  
H
H
L
BWE  
H
L
BW1  
BW2  
X
BW3  
X
BW4  
X
Operation  
Read  
X
Read  
H
H
H
H
Write all Bytes  
Write all Bytes  
Write Byte 1(3)  
Write Byte 2(3)  
Write Byte 3(3)  
Write Byte 4(3)  
X
L
X
X
X
X
H
H
H
H
H
L
L
L
L
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
4877 tbl 12  
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. BW3 and BW4 are not applicable for the IDT71V2579.  
3. Multiple bytes may be selected during the same cycle.  
AsynchronousTruthTable(1)  
Operation(2)  
OE  
ZZ  
I/O Status  
Power  
Read  
L
H
X
X
X
L
L
L
L
H
Data Out  
High-Z  
Active  
Active  
Read  
Write  
High-Z – Data In  
High-Z  
Active  
Deselected  
Sleep Mode  
Standby  
Sleep  
High-Z  
4877 tbl 13  
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.  
InterleavedBurstSequenceTable(LBO=VDD)  
Sequence 1  
Sequence 2  
Sequence 3  
Sequence 4  
A1  
A0  
0
A1  
A0  
1
A1  
1
A0  
0
A1  
A0  
1
First Address  
0
0
1
1
0
0
1
1
1
1
0
0
Second Address  
Third Address  
1
0
1
1
0
0
1
0
0
1
Fourth Address(1)  
1
0
0
1
0
4877 tbl 14  
NOTE:  
1. Upon completion of the Burst sequence the counter wraps around to its initial state.  
LinearBurstSequenceTable(LBO=VSS)  
Sequence 1  
Sequence 2  
Sequence 3  
Sequence 4  
A1  
0
A0  
0
A1  
0
A0  
1
A1  
1
A0  
0
A1  
1
A0  
1
First Address  
Second Address  
Third Address  
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)  
1
1
0
0
0
1
1
0
4877 tbl 15  
NOTE:  
1. Upon completion of the Burst sequence the counter wraps around to its initial state.  
6.42  
11  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
AC Electrical Characteristics  
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)  
7.5ns(5)  
8ns  
8.5ns  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max. Unit  
Clock Parameter  
____  
____  
____  
____  
____  
____  
tCYC  
Clock Cycle Time  
8.5  
3
10  
4
11.5  
4.5  
ns  
ns  
ns  
(1)  
CH  
Clock High Pulse Width  
Clock Low Pulse Width  
t
____  
____  
____  
(1)  
3
4
4.5  
tCL  
Output Parameters  
____  
____  
____  
CD  
t
Clock High to Valid Data  
7.5  
8
8.5  
ns  
ns  
ns  
____  
____  
____  
tCDC  
Clock High to Data Change  
Clock High to Output Active  
Clock High to Data High-Z  
Output Enable Access Time  
Output Enable Low to Output Active  
2
0
2
0
2
0
____  
____  
____  
(2)  
tCLZ  
(2)  
2
3.5  
2
3.5  
2
3.5  
ns  
ns  
ns  
ns  
tCHZ  
____  
____  
____  
tOE  
3.5  
3.5  
3.5  
____  
____  
____  
(2)  
0
0
0
tOLZ  
____  
____  
____  
(2)  
OHZ  
Output Enable High to Output High-Z  
3.5  
3.5  
3.5  
t
Set Up Times  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
tSA  
Address Setup Time  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
2
2
2
2
2
2
2
2
2
2
2
2
ns  
ns  
ns  
ns  
ns  
ns  
SS  
t
Address Status Setup Time  
Data In Setup Time  
SD  
t
SW  
t
Write Setup Time  
tSAV  
tSC  
Address Advance Setup Time  
Chip Enable/Select Setup Time  
Hold Times  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
tHA  
tHS  
Address Hold Time  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
Address Status Hold Time  
Data In Hold Time  
tHD  
tHW  
tHAV  
tHC  
Write Hold Time  
Address Advance Hold Time  
Chip Enable/Select Hold Time  
Sleep Mode and Configuration Parameters  
____  
____  
____  
____  
____  
____  
____  
____  
____  
tZZPW  
tZZR(3)  
tCFG (4)  
ZZ Pulse Width  
100  
100  
34  
100  
100  
40  
100  
100  
50  
ns  
ns  
ZZ Recovery Time  
Configuration Set-up Time  
ns  
4877 tbl 16  
NOTES:  
1. Measured as HIGH above VIH and LOW below VIL.  
2. Transition is measured ±200mV from steady-state.  
3. Device must be deselected when powered-up from sleep mode.  
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.  
5. Commercial temperature range only.  
6.42  
12  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Flow-Through Read Cycle(1,2)  
,
6.42  
13  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Combined Flow-Through Read and Write Cycles(1,2,3)  
,
6.42  
14  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Write Cycle No. 1 - GW Controlled(1,2,3)  
,
6.42  
15  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Write Cycle No. 2 - Byte Controlled(1,2,3)  
,
6.42  
16  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)  
,
6.42  
17  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Non-Burst Read Cycle Timing Waveform  
CLK  
ADSP  
ADSC  
Av  
Aw  
Ax  
Ay  
Az  
ADDRESS  
GW, BWE, BWx  
CE, CS1  
CS0  
OE  
(Av)  
(Aw)  
(Ax)  
(Ay)  
DATAOUT  
,
4877 drw 10  
NOTES:  
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.  
2. (Ax) represents the data for address Ax, etc.  
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.  
Non-Burst Write Cycle Timing Waveform  
CLK  
ADSP  
ADSC  
Av  
Aw  
Ax  
Ay  
Az  
ADDRESS  
GW  
CE, CS1  
CS0  
(Av)  
(Aw)  
(Ax)  
(Ay)  
(Az)  
DATAIN  
,
4877 drw 11  
NOTES:  
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.  
2. (Ax) represents the data for address Ax, etc.  
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.  
4. For write cycles, ADSP and ADSC have different limitations.  
6.42  
18  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
100-Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline  
6.42  
19  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
119 Ball Grid Array (BGA) Package Diagram Outline  
6.42  
20  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline  
6.42  
21  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
OrderingInformation  
IDT XXX  
S
XX  
X
X
Device  
Type  
Power  
Speed  
Package  
Process/  
Temperature  
Range  
Blank  
I
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)  
PF  
BG  
BQ  
100-pin Plastic Thin Quad Flatpack (TQFP)  
119 Ball Grid Array (BGA)  
165 Fine Pitch Ball Grid Array (fBGA)  
75*  
80  
85  
Access Time in Tenths of Nanoseconds  
,
128K x 36 Flow-Through Burst Synchronous SRAM with 2.5V I/O  
256K x 18 Flow-Through Burst Synchronous SRAM with 2.5V I/O  
71V2577  
71V2579  
*Commercial temperature range only.  
4877 drw 12  
6.42  
22  
IDT71V2577, IDT71V2579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
2.5V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Datasheet Document History  
7/23/99  
9/17/99  
Updatedtonewformat  
RevisedI/Opindescription  
Revisedblockdiagramforflow-throughfunctionality  
Revised ISB1 and IZZ for speeds 7.5 to 8.5ns  
Added119-leadBGApackagediagram  
Pg. 2  
Pg. 3  
Pg. 8  
Pg. 18  
Pg. 20  
AddedDatasheetDocumentHistory  
12/31/99 Pg. 1, 4, 8, 11, 19  
04/04/00 Pg. 18  
Pg. 4  
AddedIndustrialTemperaturerangeofferings  
Add100pinTQFPPackageDiagramOutline  
AddcapacitancetableforBGApackage;AddIndustrialtemperaturetotable;insertnoteto  
AbsoluteMaxRatingtableandRecommendedOperatingTemperaturetables.  
Addnewpackage offering, 13x15mm165fBGA  
Correct119BGAPackageDiagramOutline  
06/01/00  
Pg. 20  
07/15/00 Pg. 7  
Pg. 8  
AddnotereferencetoBG119pinout  
AddDNUreference note toBQ165pinout  
Pg. 20  
10/25/00  
Pg. 8  
UpdateBG119PackageDiagramOutlineDimensions  
RemovePreliminarystatus  
Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST  
CORPORATE HEADQUARTERS  
2975StenderWay  
Santa Clara, CA 95054  
for SALES:  
for Tech Support:  
sramhelp@idt.com  
800-544-7726, x4033  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
www.idt.com  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
6.42  
23  

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