IDT72T51243L5BBI [IDT]
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits; 2.5V多队列流量控制器件（ 32队列） 36位宽配置1,179,648位和2,359,296位
| 型号： | IDT72T51243L5BBI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 文件： | 总55页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
IDT72T51233
IDT72T51243
IDT72T51253
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION
589,824 bits, 1,179,648 bits and 2,359,296 bits
•
•
•
•
Individual, Active queue flags (OV, FF, PAE, PAF)
4 bit parallel flag status on both read and write ports
Provides continuous PAE and PAF status of up to 4 Queues
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
- x18in to x18out
- x9in to x18out
FEATURES:
•
Choose from among the following memory density options:
IDT72T51233
IDT72T51243
IDT72T51253
Total Available Memory = 589,824 bits
Total Available Memory = 1,179,648 bits
Total Available Memory = 2,359,296 bits
•
•
•
Configurable from 1 to 4 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
Independent Read and Write access per queue
User programmable via serial port
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
Default multi-queue device configurations
-IDT72T51233: 8,192 x 18 x 4Q
- x18in to x9out
- x9in to x9out
•
•
•
•
•
•
•
•
FWFT mode of operation on read port
Partial Reset, clears data in single Queue
Expansion of up to 8 multi-queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
-IDT72T51243: 16,384 x 18 x 4Q
-IDT72T51253: 32,768 x 18 x 4Q
•
•
•
•
•
•
•
•
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
FUNCTIONALBLOCKDIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
RADEN
ESTR
WADEN
FSTR
RDADD
5
WRADD
WEN
Q0
REN
5
RCLK
EREN
WCLK
ERCLK
OE
Q
out
x9, x18
D
in
x9, x18
DATA IN
DATA OUT
OV
FF
Q3
PAF
PAFn
PAE
PAEn
4
4
6115 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc
NOVEMBER 2003
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6115/2
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Iftheuserdoesnotwishtoprogramthemulti-queuedevice,adefaultoptionis
availablethatconfiguresthedeviceinapredeterminedmanner.
BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster
Reset latches in all configuration setup pins and must be performed before
programmingofthedevicecantakeplace.APartialResetwillresetthereadand
writepointersofanindividualqueue,providedthatthequeueisselectedonboth
thewriteportandreadportatthetimeofpartialreset.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided.Theseareoutputs fromthereadportofthequeuethatarerequired
forhighspeeddatacommunication,toprovidetightersynchronizationbetween
thedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedby
theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith
respecttoERENandERCLK,thisisveryusefulwhendataisbeingreadathigh
speed.
Themulti-queueflow-controldevicehasthecapabilityofoperatingitsIOin
either2.5VLVTTL,1.5VHSTLor1.8VeHSTLmode.ThetypeofIOisselected
viatheIOSELinput.Thecoresupplyvoltage(VCC)tothemulti-queueisalways
2.5V,howevertheoutputlevelscanbesetindependentlyviaaseparatesupply,
VDDQ.
ThedevicesalsoprovideadditionalpowersavingsviaaPowerDownInput.
This input disables the write port data inputs when no write operations are
required.
DESCRIPTION
The IDT72T51233/72T51243/72T51253 multi-queue flow-control de-
vicesaresinglechipwithinwhichanywherebetween1and4discreteFIFO
queuescanbesetup.Allqueueswithinthedevicehaveacommondatainput
bus,(writeport)andacommondataoutputbus,(readport).Datawritteninto
the write portis directedtoa respective queue via aninternalde-multiplex
operation,addressedbytheuser.Datareadfromthereadportisaccessed
froma respective queue via aninternalmultiplexoperation,addressedby
the user. Data writes and reads can be performed at high speeds up to
200MHz,withaccesstimesof3.6ns.Datawriteandreadoperationsaretotally
independent of each other, a queue maybe selected on the write port and
adifferentqueueonthereadportorbothportsmayselectthesamequeue
simultaneously.
The device provides FullflagandOutputValidflagstatus forthe queue
selectedforwriteandreadoperations respectively.AlsoaProgrammable
AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.
Two 4 bit programmable flag busses are available, providing status of all
queues,includingqueuesnotselectedforwriteorreadoperations,theseflag
busses provide an individual flag per queue.
BusMatchingisavailableonthisdevice,eitherportcanbe9bitsor18bits
wide.WhenBusMatchingisusedthedeviceensuresthelogicaltransferof
datathroughputinaLittleEndianmanner.
Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable
toprogramthetotalnumberofqueuesbetween1and4,theindividualqueue
depthsbeingindependentofeachother.Theprogrammableflagpositionsare
alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.
AJTAGtestportisprovided,herethemulti-queueflow-controldevicehasa
fullyfunctionalBoundaryScanfeature,compliantwithIEEE1149.1Standard
TestAccessPortandBoundaryScanArchitecture.
SeeFigure1,Multi-QueueFlow-ControlDeviceBlockDiagramforanoutline
ofthefunctionalblockswithinthedevice.
2
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D
in
x9, x18
D
- D
17
0
WCLK
WEN
INPUT
DEMUX
TMS
5
WRADD
WADEN
Write Control
Logic
TDI
JTAG
Logic
TDO
TCK
TRST
Write Pointers
PAF
General Flag
Monitor
FSTR
PAFn
4
FSYNC
Upto 4
FIFO
Queues
FXO
FXI
OV
Active Q
Flags
PAE
0.5 Mbit
1.1 Mbit
2.3 Mbit
Dual Port
Memory
Active Q
Flags
FF
PAF
PAE
General Flag
Monitor
4
SI
SO
SCLK
PAEn
ESTR
ESYNC
Serial
Multi-Queue
Programming
SENI
EXI
SENO
EXO
Read Pointers
FM
IW
5
Reset
Logic
RDADD
RADEN
NULL-Q
Read Control
Logic
OW
MAST
REN
RCLK
ID0
ID1
ID2
DF
Device ID
3 Bit
OUTPUT
MUX
PAE/ PAF
Offset
DFM
OUTPUT
REGISTER
EREN
PRS
MRS
ERCLK
6115 drw02
IOSEL
Vref
IO Level Control
&
Power Down
OE
Q
- Q
17
0
PD
Q
x9, x18
out
Figure 1. Multi-Queue Flow-Control Device Block Diagram
3
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATION
A1 BALL PAD CORNER
A
D14
D15
D17
D13
D16
GND
D12
D11
GND
D10
D9
Q9
Q8
Q7
Q15
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
FM
D7
D6
D5
D4
D3
D2
D1
D0
TCK
TMS
TDO
TDI
ID2
ID1
ID0
Q3
Q2
Q1
Q6
Q5
Q4
Q12
Q11
Q14
Q13
B
C
D
E
F
D8
TRST
IOSEL
Q0
Q10
Q16
DNC
Q17
DNC
DNC
VDDQ
VCC
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDQ
VDDQ
VCC
VCC
VDDQ
VDDQ
VCC
V
CC
GND
GND
GND
GND
GND
VCC
GND
GND
GND
GND
GND
GND
VCC
VDDQ
VDDQ
GND
GND
VDDQ
VCC
VDDQ
VCC
GND
VCC
VDDQ
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
DNC
DNC
DNC
DNC
DNC
MAST
G
H
J
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
PD
GND
NULL-Q
GND
GND
GND
VCC
DNC
GND
GND
GND
GND
GND
VCC
GND
GND
VCC
VCC
K
L
VREF
VCC
VCC
VCC
VCC
GND
ADVANCE
SI
VDDQ
GND
GND
GND
GND
VCC
DFM
DF
SO
VCC
GND
VDDQ
IW
OW
GND
GND
M
N
P
R
T
SENO
SENI
OE
VDDQ
VDDQ
VCC
VCC
GND
VCC
VCC
VDDQ
VDDQ
RDADD0 RDADD1
VDDQ
WRADD1 WRADD0 SCLK
GND
GND
GND
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VCC
VDDQ
V
DDQ
GND
GND
GND
WADEN
FF
OV
RDADD2 RDADD3 RDADD4
PAF3
DNC
DNC
PAE
DNC
DNC
PAE3
INFORMATION
WRADD3 WRADD2 FSYNC
DNC
DNC
WCLK
7
DNC
DNC
ESTR ESYNC
FSTR
PAF
EREN
REN
PAE2
PAE1
RADEN
PAF2
ERCLK
DNC
EXO
EXI
FXI
FXO
WEN
PRS
MRS
RCLK
PAE0
WRADD4
PAF0
PAF1
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
6115 drw03
NOTE:
1. DNC - Do Not Connect.
PBGA (BB256-1, order code: BB)
TOP VIEW
4
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
provides a user programmable almost full flag for all 4 queues and when a
respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
for that queue. Conversely, the read port has an output valid flag, providing
statusofthedatabeingreadfromthequeueselectedonthereadport.Aswell
astheoutputvalidflagthedeviceprovidesadedicatedalmostemptyflag.This
almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.
Thedeviceprovidesauserprogrammablealmostemptyflagforall4queues
andwhenarespectivequeueisselectedonthereadport,thealmostemptyflag
providesstatusforthatqueue.
DETAILEDDESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
singledataoutputportwithupto4FIFOqueuesinparallelbufferingbetween
thetwoports.Theusercansetupbetween1and4Queueswithinthedevice.
Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing
theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths,
independentofoneanother.
MEMORYORGANIZATION/ALLOCATION
PROGRAMMABLE FLAG BUSSES
Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing
512x18or1,024x9bits.Whentheuserisconfiguringthenumberofqueues
andindividualqueue sizes the usermustallocate the memorytorespective
queues,inunitsofblocks,thatis,asinglequeuecanbemadeupfrom0tom
blocks,wheremisthetotalnumberofblocksavailablewithinadevice.Alsothe
totalsize of anygiven queue mustbe in increments of 512 x 18or1,024 x 9.
Forthe IDT72T51233, IDT72T51243andIDT72T51253the TotalAvailable
Memoryis64,128and256blocksrespectively(ablockbeing512x18or1,024
x9).Ifanyportisconfiguredforx18buswidth,ablocksizeis512x18.Ifboth
thewriteandreadportsareconfiguredforx9buswidth,ablocksizeis1,024
x9.Queuescanbebuiltfromtheseblockstomakeanysizequeuedesiredand
any number of queues desired.
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost
fullflagstatusbusisprovided,thisbusis4bitswide.Also,analmostemptyflag
statusbusisprovided,againthisbusis4bitswide.Thepurposeoftheseflag
bussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels
withinqueuesthatmaynotbeselectedonthewriteorreadport.Asmentioned,
thedeviceprovidesalmostfullandalmostemptyregisters(programmableby
the user) for each of the 4 queues in the device.
The4bitPAEnand4bitPAFnbussesprovideadiscretestatusoftheAlmost
EmptyandAlmostFullconditionsofall4queue's.Ifthedeviceisprogrammed
for less than 4 queue's, then there will be a corresponding number of active
outputs onthePAEnandPAFnbusses.
Theflagbussescanprovideacontinuousstatusofallqueues.Ifdevicesare
connectedinexpansionmodetheindividualflagbussescanbeleftinadiscrete
form,providingconstantstatusofallqueues,orthebussesofindividualdevices
canbe connectedtogethertoproduce a single bus of4bits. The device can
then operate in a "Polled" or "Direct" mode.
Whenoperatinginpolledmodetheflagbusprovidesstatusofeachdevice
sequentially,thatis,oneachrisingedgeofaclocktheflagbusisupdatedtoshow
thestatusofeachdeviceinorder.Therisingedgeofthewriteclockwillupdate
theAlmostFullbusandarisingedgeonthereadclockwillupdatetheAlmost
Emptybus.
Whenoperatingindirectmodethedevicedrivingtheflagbusisselectedby
theuser.Theuseraddresses thedevicethatwilltakecontrolofarespective
flagbus, these PAFnand PAEnflagbusses operatingindependentlyofone
another.AddressingoftheAlmostFullflagbus is doneviathewriteportand
addressingoftheAlmostEmptyflagbus is doneviathereadport.
BUS WIDTHS
Theinputportiscommontoallqueueswithinthedevice,asistheoutputport.
ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport
andoutputportcanbeeitherx9orx18bitswide,thereadandwriteportwidths
beingsetindependentlyofoneanother.Becausetheportsarecommontoall
queuesthewidthofthequeuesisnotindividuallyset,sothattheinputwidthof
all queues are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete
queueviathewritequeueselectaddressinputs.Conversely,databeingread
fromthedevicereadportisreadfromaqueueselectedviathereadqueueselect
addressinputs.Datacanbesimultaneouslywrittenintoandreadfromthesame
queueordifferentqueues.Onceaqueueisselectedfordatawritesorreads,
the writing and reading operation is performed in the same manner as
conventionalIDTsynchronous FIFO,utilizingclocks andenables,thereis a
singleclockandenableperport.Whenaspecificqueueisaddressedonthe
writeport,dataplacedonthedatainputsiswrittentothatqueuesequentially
basedontherisingedgeofawriteclockprovidedsetupandholdtimesaremet.
Conversely,dataisreadontotheoutputportafteranaccesstimefromarising
edge on a read clock.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.
Whenaqueueis selectedontheoutputport,thenextwordinthatqueuewill
automaticallyfallthroughtotheoutputregister.Allsubsequentwordsfromthat
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the
lastwordfromtheprevious queuewillremainontheoutputregister.
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice
EXPANSION
Expansionofmulti-queuedevicesisalsopossible,upto8devicescanbe
connectedinaparallelfashionprovidingthepossibilityofbothdepthexpansion
or queue expansion. Depth Expansion means expanding the depths of
individual queues. Queue expansion means increasing the total number of
queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore
memoryblocks withinamulti-queuedevicecanbeallocatedtoincreasethe
depth of a queue. For example, depth expansion of 8 devices provides the
possibilityof8queuesof32Kx18deepwithintheIDT72T51233,64Kx18deep
withintheIDT72T51243and128Kx18deepwithintheIDT72T51253,each
queuebeingsetupwithinasingledeviceutilizingallmemoryblocksavailable
toproduceasinglequeue. This is thedeepestqueuethatcansetupwithina
device.
For queue expansion of the 4 queue device, a maximum number of 32 (8
x 4) queues may be setup, each queue being 4K x18 or 2K x 9 deep, if less
queuesaresetup,thenmorememoryblockswillbeavailabletoincreasequeue
depthsifdesired.Whenconnectingmulti-queuedevicesinexpansionmodeall
respectiveinputpins(data&control)andoutputpins(data& flags),shouldbe
“connected”togetherbetweenindividualdevices.
5
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS
Symbol &
Pin No.
Name
I/OTYPE
Description
D[17:0]
DataInputBus HSTL-LVTTL These are the 18data inputpins. Data is writtenintothe device via these inputpins onthe risingedge
Din (See Pin
tablefordetails)
INPUT
ofWCLKprovidedthatWENisLOW.Duetobusmatchingnotallinputsmaybeused,anyunusedinputs
shouldbetiedLOW.
DF(1)
(L3)
DefaultFlag
DefaultMode
LVTTL
INPUT
Iftheuserrequiresdefaultprogrammingofthemulti-queuedevice,thispinmustbesetupbeforeMaster
Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
(1)
DFM
(L2)
LVTTL
INPUT
The multi-queue device requires programmingaftermasterreset. The usercandothis seriallyvia the
serialport,ortheusercanusethedefaultmethod.IfDFMisLOWatmasterresetthenserialmodewillbe
selected,ifHIGHthendefaultmodeisselected.
ERCLK
(R10)
RCLK Echo
HSTL-LVTTL ReadClockEchooutput,thisoutputgeneratesaclockbasedonthereadclockinput,thisisusedforSource
OUTPUT SynchronousclockingwherethereceivingdevicesutilizestheERCLKtoclockdataoutputfromthequeue.
HSTL-LVTTL ReadEnableEchooutput,canbeusedinconjunctionwiththeERCLKoutputtoloaddataoutputfromthe
EREN
(R11)
REN Echo
OUTPUT
queue intothe receivingdevice.
ESTR
(R15)
PAEn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK
andtheRDADDbustoselectadeviceforitsqueuestobeplacedontothePAEnbusoutputs.Adevice
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.Note,thataPAEnflagbus
selectioncannotbemade,(ESTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
ESYNC
(R16)
PAEn Bus Sync HSTL-LVTTL ESYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAEnbus
OUTPUT
duringPolledoperationofthePAEnbus.DuringPolledoperationeachdevice'squeuestatusflagsare
loadedontothe PAEnbus outputs sequentiallybasedonRCLK. The firstRCLKrisingedge loads
device 1 onto PAEn, the second RCLK rising edge loads device 2 and so on. During the RCLK cycle
thata selecteddevice is placedontothePAEnbus, the ESYNCoutputwillbe HIGH.
EXI
(T16)
PAEnBus
ExpansionIn
LVTTL
INPUT
The EXIinputis usedwhenmulti-queue devices are connectedinexpansionmode andPolledPAEn
bus operationhas beenselected. EXIofdevice ‘N’connects directlytoEXOofdevice ‘N-1’. The EXI
receives a tokenfromthe previous device ina chain. Insingle device mode the EXIinputmustbe tied
LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheEXIinput
mustbeconnectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
EXO
(T15)
PAEnBus
ExpansionOut
LVTTL
OUTPUT
EXOis anoutputthatis usedwhenmulti-queuedevices areconnectedinexpansionmodeandPolled
PAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.This
pinpulses whendevice Nplaces its PAE status ontothe PAEnbus withrespecttoRCLK. This pulse
(token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising edge the
firstquadrantofdevice N+1willbe loadedontothe PAEnbus. This continues throughthe chainand
EXOofthelastdeviceis thenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeachdevice
inthechainprovides synchronizationtotheuserofthis loopingevent.
FF
(P8)
Full Flag
HSTL-LVTTL This pinprovides the fullflagoutputforthe active queue, thatis, the queue selectedonthe input
OUTPUT portforwrite operations,(selectedvia WCLK,WRADDbus andWADEN).Onthe WCLKcycle after
aqueueselection,this flagwillshowthestatus ofthenewlyselectedqueue.Datacanbewrittento
this queue on the next cycle providedFF is HIGH. This flaghas High-Impedance capability, this is
importantduringexpansionofdevices, whentheFF flagoutputofupto8devices maybe connected
togetherona commonline. The device witha queue selectedtakes controlofthe FF bus, allother
devices place theirFFoutputintoHigh-Impedance.Whena queue selectionis made onthe write
portthisoutputwillswitchfromHigh-ImpedancecontrolonthenextWCLKcycle.Thisflagissynchronized
toWCLK.
(1)
FM
Flag Mode
HSTL-LVTTL Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe
(K16)
INPUT
FMpinduringMasterResetwilldetermine whetherthe PAFnandPAEnflagbusses operate ineither
PolledorDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.
6
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
FSTR
(R4)
PAFn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK
andtheWRADDbustoselectadeviceforitsqueuestobeplacedontothePAFnbusoutputs.Adevice
addressedviatheWRADDbus is selectedontherisingedgeofWCLKprovidedthatFSTRis HIGH.If
Polledoperations has beenselected,FSTRshouldbetiedinactive,LOW.Note,thataPAFnflagbus
selectioncannotbemade,(FSTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
FSYNC
(R3)
PAFn Bus Sync
LVTTL
OUTPUT
FSYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAFnbus
duringPolledoperationofthePAFnbus.DuringPolledoperationeachdevice's queuestatus flags
areloadedontothePAFnbusoutputssequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads
device 1 onto PAFn, the second WCLK rising edge loads device 2 and so on. During the WCLK cycle
thata selecteddevice is placedontothe PAFnbus, the FSYNCoutputwillbe HIGH.
FXI
(T2)
PAFnBus
ExpansionIn
LVTTL
INPUT
The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn
bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives a tokenfromthe previous device ina chain. Insingle device mode the FXIinputmustbe tied
LOWifthePAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXIinput
mustbeconnectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
FXO
(T3)
PAFnBus
ExpansionOut
LVTTL
OUTPUT
FXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolled
PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This
pinpulses whendevice Nplaces its PAE status ontothe PAFnbus withrespecttoWCLK. This pulse
(token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising edgethe
firstquadrantofdeviceN+1willbeloadedontothePAFnbus.ThiscontinuesthroughthechainandFXO
ofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdeviceinthe
chainprovidessynchronizationtotheuserofthisloopingevent.
(1)
ID[2:0]
Device ID Pins HSTL-LVTTL Forthe4Qmulti-queuedevicetheWRADDandRDADDaddressbussesare5bitswide.Whenaqueue
ID2-C9
ID1-A10
ID0-B10
INPUT
selectiontakes placethe3MSb’s ofthis 5bitaddress bus areusedtoaddress thespecificdevice(the
2 LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s
oftheaddressarecomparedtothedeviceIDpins.Thefirstdeviceinachainofmulti-queue’s(connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould
besetupas‘000’andthe3MSb’softheWRADDandRDADDaddressbussesshouldbetiedLOW.The
ID[2:0]inputssetuparespectivedevicesIDduringmasterreset.TheseIDpinsmustnottoggleduring
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
IOSEL
(C8)
IOSelect
LVTTL
INPUT
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
required then IOSEL should be tied HIGH. If LVTTL I/O are required then it should be tied LOW.
(1)
IW
InputWidth
LVTTL
INPUT
IWselectsthebuswidthforthedatainputbus.IfIWisLOWduringaMasterResetthenthebuswidth
is x18, if HIGH then it is x9.
(L15)
(1)
MAST
MasterDevice HSTL-LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe
(K15)
INPUT
Masterdevice ora Slave. Ifthis pinis HIGH, the device is the masterifitis LOWthenitis a Slave. The
masterdeviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-
Impedance,preventingbuscontention.Ifamulti-queuedeviceisbeingusedinsingledevicemode,this
pinmustbesetHIGH.
MRS
MasterReset
HSTL-LVTTL AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
INPUT aftermasterreset.
HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD
INPUT and RADEN address bus to address the Null-Q.
(T9)
NULL-Q
(J2)
NullQueue
Select
OE
(M14)
OutputEnable HSTL-LVTTL TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue
INPUT
dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswill
beinaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbe
7
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
OE
(Continued)
(M14)
OutputEnable HSTL-LVTTL inHighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbe
INPUT
inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-
stateofthatrespectivedevice.
OV
(P9)
OutputValid
Flag
HSTL-LVTTL Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-controldevice
OUTPUT
dataoutputport,Qout.Thisflagistherefore,2-stagedelayedtomatchthedataoutputpathdelay.That
is,thereisa2RCLKcycledelayfromthetimeagivenqueueisselectedforreads,tothetimetheOVflag
representsthedatainthatrespectivequeue.Whenaselectedqueueonthereadportisreadtoempty,
theOV flagwillgoHIGH, indicatingthatdata onthe outputbus is notvalid. TheOVflagalsohas High-
Impedancecapability,requiredwhenmultipledevicesareusedandtheOVflagsaretiedtogether.
(1)
OW
OutputWidth
LVTTL
INPUT
OWselectsthebuswidthforthedataoutputbus.IfOWisLOWduringaMasterResetthenthebuswidth
is x18, if HIGH then it is x9.
(L16)
PAE
(P10)
Programmable HSTL-LVTTL ThispinprovidestheAlmost-Emptyflagstatusforthequeuethathasbeenselectedontheoutputport
Almost-Empty
Flag
OUTPUT
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queueisalmost-empty.ThisflagoutputmaybeduplicatedononeofthePAEnbuslines.Thisflagis
synchronizedtoRCLK.
PAEn
Programmable HSTL-LVTTL Onthe4QdevicethePAEnbusis8bitswide.DuringaMasterResetthisbusissetupforAlmostEmpty
(PAE3-P13
PAE2-R13
PAE1-T13
PAE0-T14)
Almost-Empty
FlagBus
OUTPUT
mode.ThisoutputbusprovidesPAEstatusof4queueswithinaselecteddevice.Duringqueueread/write
operationstheseoutputsprovideprogrammableemptyflagstatus,ineitherdirectorpolledmode.The
modeofflagoperationisdeterminedduringmasterresetviathestateoftheFMinput.Thisflagbusiscapable
ofHigh-Impedancestate,thisisimportantduringexpansionofmulti-queuedevices.Duringdirect
operationthePAEnbusisupdatedtoshowthePAEstatusofqueueswithinaselecteddevice.Selection
ismadeusingRCLK,ESTRandRDADD.DuringPolledoperationthePAEnbusisloadedwiththePAE
statusofmulti-queueflow-controldevicessequentiallybasedontherisingedgeofRCLK.
PAF
(R8)
Programmable HSTL-LVTTL ThispinprovidestheAlmost-Fullflagstatusforthequeuethathasbeenselectedontheinputportforwrite
Almost-FullFlag OUTPUT
operations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselectedqueueisalmost-
full.ThisflagoutputmaybeduplicatedononeofthePAFnbuslines.ThisflagissynchronizedtoWCLK.
PAFn
Programmable HSTL-LVTTL Onthe 4Qdevice the PAFnbus is 8bits wide. This outputbus provides PAF status of4queues within
(PAF3-P5
PAF2-R5
PAF1-T5
PAF0-T4)
Almost-FullFlag OUTPUT
Bus
aselecteddevice.Duringqueueread/writeoperationstheseoutputsprovideprogrammablefullflag
status,ineitherdirectorpolledmode.Themodeofflagoperationisdeterminedduringmasterresetvia
thestateoftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansion
ofmulti-queuedevices.DuringdirectoperationthePAFnbusisupdatedtoshowthePAFstatusofqueues
withinaselecteddevice.SelectionismadeusingWCLK,FSTR,WRADDandWADEN.DuringPolled
operationthePAFnbusisloadedwiththePAFstatusofmulti-queueflow-controldevicessequentially
basedonthe risingedge ofWCLK.
PD
(K1)
Power Down
PartialReset
HSTL
INPUT
This inputis usedtoprovide additionalpowersavings. Whenthe device I/Ois setupforHSTL/eHSTL
modeaHIGHonthePDinputdisablesthedatainputsonthewriteportonly,providingsignificantpower
savings. In LVTTL mode this pin has no operation
PRS
(T8)
HSTL-LVTTL APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial
INPUT
Resetcanbe performedona queue, thatqueue mustbe selectedonboththe write portandreadport
2clockcycles beforetheresetis performed.APartialResetis thenperformedbytakingPRSLOWfor
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
thefirstmemorylocation,noneofthedevicesconfigurationwillbechanged.
Q[17:0]
DataOutputBus HSTL-LVTTL Thesearethe18dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge
Qout(SeePin
tablefordetails)
OUTPUT
ofRCLKprovidedthatREN is LOW, OE is LOWandthe queue is selected. Due tobus matchingnot
alloutputs maybeused,anyunusedoutputs shouldnotbeconnected.
RADEN
(R14)
ReadAddress HSTL-LVTTL The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to
Enable
INPUT
bereadfrom.AqueueaddressedviatheRDADDbusisselectedontherisingedgeofRCLKprovided
thatRADENisHIGH.RADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).RADEN
shouldnotbepermanentlytiedHIGH.RADENcannotbeHIGHforthesameRCLKcycleasESTR.Note,
thatareadqueueselectioncannotbemade,(RADENmustNOTgoactive)untilprogrammingofthepart
has beencompletedandSENO has goneLOW.
8
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
RCLK
Name
I/OTYPE
Description
ReadClock
HSTL-LVTTL When enabledbyREN, the risingedge ofRCLKreads data fromthe selectedqueue via the output
(T10)
INPUT
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe
devicetobeplacedonthePAEnbusduringdirectflagoperation.DuringpolledflagoperationthePAEn
bus is cycledwithrespecttoRCLKandtheESYNCsignalis synchronizedtoRCLK.ThePAEandOV
outputsareallsynchronizedtoRCLK.DuringdeviceexpansiontheEXOandEXIsignalsarebasedon
RCLK.RCLKmustbecontinuous andfree-running.
RDADD
ReadAddress HSTL-LVTTL For the 4Q device the RDADD bus is 5 bits. The RDADD bus is a dual purpose address bus. The first
[4:0]
Bus
INPUT
functionofRDADDistoselectaqueuetobereadfrom.Theleastsignificant2bitsofthebus,RDADD[1:0]
areusedtoaddress1of4possiblequeueswithinamulti-queuedevice.Themostsignificant 3bits,
RDADD[4:2]areusedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
RDADDbus willbe selectedona risingedge ofRCLKprovidedthatRADENis HIGH, (note, thatdata
canbeplacedontotheQoutbus,readfromthepreviouslyselectedqueueonthisRCLKedge).Onthe
next rising RCLK edge after a read queue select, a data word from the previous queue will be placed
ontotheoutputs,Qout,regardlessoftheRENinput.TwoRCLKrisingedgesafterreadqueueselect,data
willbeplacedontotheQoutoutputsfromthenewlyselectedqueue,regardlessofRENdue tothefirst
wordfallthrougheffect.
(RDADD4-P16
RDADD3-P15
RDADD2-P14
RDADD1-M16
RDADD0-M15)
ThesecondfunctionoftheRDADDbusistoselectthedeviceofqueuestobeloadedontothePAEnbus
duringstrobedflagmode.Themostsignificant3bits,RDADD[4:2]areagainusedtoselect1of8
possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsRDADD[1:0]
aredon’tcareduringdeviceselection.ThedeviceaddresspresentontheRDADDbuswillbeselected
onthe risingedge ofRCLKprovidedthatESTRis HIGH, (note, thatdata canbe placedontothe Qout
bus, read from the previously selected queue on this RCLK edge). Please refer toTable 2 for details
on RDADD bus.
REN
ReadEnable
SerialClock
HSTL-LVTTL The REN input enables read operations from a selected queue based on a rising edge of RCLK. A
(T11)
INPUT
queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
ofthestateofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond
RCLKcycle afterqueue selectionregardless ofRENdue tothe FWFToperation. Areadenable is not
required to cycle the PAEn bus (in polled mode) or to select the device, (in direct mode).
SCLK
(N3)
HSTL-LVTTL Ifserialprogrammingofthemulti-queuedevicehasbeenselectedduringmasterreset,theSCLKinput
INPUT
clockstheserialdatathroughthemulti-queuedevice.DatasetupontheSIinputisloadedintothedevice
ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed
theSCLKofalldevices shouldbeconnectedtothesamesource.
SENI
(M2)
SerialInput
Enable
HSTL-LVTTL Duringserialprogrammingofamulti-queuedevice,dataloadedontotheSIinputwillbeclockedintothe
INPUT
part(via a risingedge ofSCLK), providedtheSENI inputofthatdevice is LOW. Ifmultiple devices are
cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loadingofagivendeviceiscomplete,itsSENOoutputgoesLOW,allowingthenextdeviceinthechain
tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.
SENO
(M1)
SerialOutput
Enable
HSTL-LVTTL Thisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingofthemulti-queuedevice
OUTPUT
hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso
goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENOoutput
shouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthe
firstdeviceiscomplete,SENO willgoLOW,therebytakingtheSENIinputofthenextdeviceLOWand
soonthroughoutthe chain. Whena givendevice inthe chainis fullyprogrammedtheSENO output
essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.
WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.
SI
SerialIn
HSTL-LVTTL Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.
(L1)
INPUT
Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
9
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
SI
(Continued)
(L1)
Name
SerialIn
I/OTYPE
Description
HSTL-LVTTL modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO
INPUT
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connectstotheSIpinofthesecondandsoon.Themulti-queuedevicesetupregistersareshiftregisters.
SO
SerialOut
HSTL-LVTTL Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain
(M3)
OUTPUT
tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe
chain. The SOofthe finaldevice ina chainshouldnotbe connected.
(2)
TCK
(A8)
JTAGClock
LVTTL
INPUT
ClockinputforJTAGfunction.Oneoffourterminals requiredbyIEEEStandard1149.1-1990.Test
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising
edgeofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignal
needs tobe tiedtoGND.
(2)
TDI
JTAGTestData
Input
LVTTL
INPUT
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation,testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,
IDRegisterandBypass Register.Aninternalpull-upresistorforces TDIHIGHifleftunconnected.
(B9)
(2)
TDO
(A9)
JTAGTestData
Output
LVTTL
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
OUTPUT operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstruction
Register,IDRegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,while
in SHIFT-DR and SHIFT-IR controller states.
TMS(2)
(B8)
JTAGMode
Select
LVTTL
INPUT
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthe
devicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
(C7)
JTAGReset
LVTTL
INPUT
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
resetuponpower-up, thus itmustbe resetbyeitherthis signalorbysettingTMS=HIGHforfive TCK
cycles.IftheTAPcontrollerisnotproperlyresetthentheoutputswillalwaysbeinhigh-impedance.Ifthe
JTAGfunctionisusedbuttheuserdoesnotwanttouseTRST,thenTRSTcanbetiedwithMRStoensure
properqueue operation. Ifthe JTAGfunctionis notusedthenthis signalneeds tobe tiedtoGND. An
internalpull-upresistorforcesTRSTHIGHifleftunconnected.
WADEN
(P4)
WriteAddress
Enable
LVTTL
INPUT
TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto
bewritteninto.AqueueaddressedviatheWRADDbusisselectedontherisingedgeofWCLKprovided
thatWADENisHIGH.WADENshouldbeasserted(HIGH)onlyduringaqueuecycle(s).WADENshould
notbepermanentlytiedHIGH.WADENcannotbeHIGHforthesameWCLKcycleasFSTR.Note,that
awritequeueselectioncannotbemade,(WADENmustNOTgoactive)untilprogrammingoftheparthas
beencompletedandSENO hasgoneLOW.
WCLK
(T7)
WriteClock
HSTL-LVTTL WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheselectedqueueviatheinputbus,
INPUT
Din.ThequeuetobewrittentoisselectedviatheWRADDaddressbusandarisingedgeofWCLKwhile
WADENisHIGH.ArisingedgeofWCLKinconjunctionwithFSTRandWRADDwillalsoselecttheflag
quadranttobeplacedonthePAFnbusduringdirectflagoperation.DuringpolledflagoperationthePAFn
busiscycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.ThePAFn,PAFand
FFoutputsareallsynchronizedtoWCLK.DuringdeviceexpansiontheFXOandFXIsignalsarebased
onWCLK.TheWCLKmustbecontinuous andfree-running.
WEN
(T6)
WriteEnable
HSTL-LVTTL TheWENinputenableswriteoperationstoaselectedqueuebasedonarisingedgeofWCLK.Aqueue
INPUT
tobewrittentocanbeselectedviaWCLK,WADENandtheWRADDaddressbusregardlessofthestate
ofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLKcycleafter
queueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFnbus(inpolled
mode)ortoselectthePAFnquadrant, (indirectmode).
WRADD
WriteAddress HSTL-LVTTL Forthe 4Qdevice the WRADDbus is 5bits. The WRADDbus is a dualpurpose address bus. The first
[4:0]
Bus
INPUT
functionofWRADDistoselectaqueuetobewrittento.Theleastsignificant2bitsofthebus,WRADD[1:0]
areusedtoaddress1of4possiblequeueswithinamulti-queuedevice.Themostsignificant 3bits,
WRADD[4:2]areusedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
WRADDbuswillbeselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,thatdata
presentontheDinbuscanbewrittenintothepreviouslyselectedqueueonthisWCLKedgeandonthe
(WRADD4-T1
WRADD3-R1
WRADD2-R2
WRADD1-N1
WRADD0-N2)
10
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
WRADD
[4:0]
WriteAddress HSTL-LVTTL nextrisingWCLKalso,providingthatWENis LOW).TwoWCLKrisingedges afterwritequeueselect,
Bus
INPUT
datacanbewrittenintothenewlyselectedqueue.
(Continued)
ThesecondfunctionoftheWRADDbusistoselectthedeviceofqueuestobeloadedontothePAFnbus
duringstrobedflagmode.Themostsignificant3bits,WRADD[4:2]areagainusedtoselect1of8possible
multi-queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsWRADD[1:0]aredon’tcare
duringdevice selection. The device address presentonthe WRADDbus willbe selectedonthe rising
edgeofWCLKprovidedthatFSTRisHIGH,(note,thatdatacanbewrittenintothepreviouslyselected
queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus.
VCC
(See below)
+2.5VSupply
Power
Power
These are VCC power supply pins and must all be connected to a +2.5V supply rail.
VDDQ
(See Pin No.
tablebelow)
O/PRailVoltage
Thesepinsmustbetiedtothedesiredoutputrailvoltage.ForLVTTLI/Othesepinsmustbeconnected
to+2.5V,forHSTLthesepinsmustbeconnectedto+1.5VandforeHSTLthesepinsmustbeconnected
to+1.8V.
GND
GroundPin
Ground
These are Ground pins and must all be connected to the GND supply rail.
(See below)
Vref
(K3)
Reference
Voltage
HSTL
INPUT
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable
"RecommendedDCOperatingConditions". The inputprovides the reference levelforHSTL/eHSTL
inputs. ForLVTTLI/Omode this inputshouldbe tiedtoGND.
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 50-54 and Figures 30-32.
PIN NUMBER TABLE
Symbol
Name
I/OTYPE
HSTL-LVTTL D17-C1, D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5, D5-C5,
INPUT D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
Pin Number
D[17:0]
Din
DataInputBus
Q[17:0]
Qout
DataOutputBus HSTL-LVTTL Q17-C15, Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14, Q11-B14, Q10-C14, Q9-A13, Q8-B13,
OUTPUT Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11, Q(1,0)-C(11,10)
VCC
+2.5VSupply
O/PRailVoltage
GroundPin
Power
Power
Ground
D(7-10),E(6,7,10,11),F(5,12),G(4,5,12,13),H(4,13),J(4,13),K(4,5,12,13),L(5,12),M(6,7,10,11),N(7-10)
D(4-6,11-13), E(4,5,12,13), F(4,13), L(4,13), M(4,5,12,13), N(4-6,11-13)
VDDQ
GND
C(2,3), D(1-3), E(1-3,8-9), F(1-3,6-11), G(1-3,6-11), H(1-3,5-12), J(1,3,5-12), K(2,6-11,14), L(6-11,14),
M(8-9), N(14-16), P(1-3)
DNC
DoNotConnect
None
B16, C16, D(15,16), E(14-16), F(14-16), G(14-16), H(14-16), J(15,16), P(6,7,11,12), R(6,7,9,12), T12
11
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
–0.5to+3.6(2)
Unit
Symbol
Parameter(1)
Conditions
Max.
Unit
VTERM
TerminalVoltage
with respect to GND
V
(2,3)
CIN
Input
Capacitance
VIN = 0V
10(3)
pF
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
(1,2)
COUT
Output
Capacitance
VOUT = 0V
15
pF
NOTES:
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
RECOMMENDEDDCOPERATINGCONDITIONS
Symbol
VCC
Parameter
Min.
2.375
0
Typ.
2.5
0
Max.
2.625
0
Unit
V
SupplyVoltage
SupplyVoltage
GND
V
VIH
InputHighVoltage
LVTTL
eHSTL
HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
—
—
V
V
V
VIL
InputLowVoltage
LVTTL
eHSTL
HSTL
-0.3
—
—
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
VREF
(HSTL only)
VoltageReferenceInput eHSTL
HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
TA
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
0
—
—
70
85
°C
°C
TA
-40
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
12
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
ILI
Parameter
Min.
–10
–10
Max.
10
Unit
µA
µA
V
V
V
InputLeakageCurrent
OutputLeakageCurrent
ILO
10
(3)
VOH
OutputLogic“1”Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
VDDQ-0.4
VDDQ-0.4
VDDQ-0.4
—
—
—
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
VOL
OutputLogic“0”Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
—
—
—
0.4V
0.4V
0.4V
V
V
V
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
ICC1(1,2)
ICC2(1)
ICC3(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
80
150
150
mA
mA
mA
Standby VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
25
100
100
mA
mA
mA
Standby VCC Current in Power Down mode(VCC = 2.5V) I/O = LVTTL
—
—
—
—
50
50
mA
mA
mA
I/O = HSTL
I/O = eHSTL
(1,2)
IDDQ
ActiveVDDQ Current (VDDQ =2.5VLVTTL)
(VDDQ = 1.5V HSTL)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
10
10
10
mA
mA
mA
(VDDQ = 1.8V eHSTL)
NOTES:
1. Both WCLK and RCLK toggling at 20MHz.
2. Data inputs toggling at 10MHz.
3. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].
4. Outputs are not 3.3V tolerant.
5. The following inputs should be pulled to GND: WRADD, RDADD, WADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.
The following inputs should be pulled to VCC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST.
All other inputs are don't care and should be at a known state.
13
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
HSTL
AC TEST LOADS
1.5V AC TEST CONDITIONS
VDDQ/2
InputPulseLevels
0.25to1.25V
0.4ns
InputRise/FallTimes
50Ω
InputTimingReferenceLevels
OutputReferenceLevels
0.75
Z0 = 50Ω
I/O
VDDQ/2
6115 drw04
NOTE:
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDEDHSTL
1.8V AC TEST CONDITIONS
6
5
4
3
2
1
InputPulseLevels
0.4 to 1.4V
0.4ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.9
VDDQ/2
NOTE:
1. VDDQ = 1.8V±.
20 30 50 80 100
Capacitance (pF)
200
6115 drw04a
2.5VLVTTL
2.5V AC TEST CONDITIONS
Figure 2b. Lumped Capacitive Load, Typical Derating
InputPulseLevels
GND to 2.5V
1ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
VCC/2
VDDQ/2
NOTE:
1. For LVTTL VCC = VDDQ.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
Output
Normally
LOW
V
CC/2
OL
V
CC/2
100mV
100mV
100mV
V
V
OH
Output
Normally
HIGH
100mV
VCC/2
VCC/2
6115 drw04b
NOTE:
1. REN is HIGH.
14
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72T51233L5
IDT72T51243L5
IDT72T51253L5
IDT72T51233L6
IDT72T51243L6
IDT72T51253L6
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency (WCLK & RCLK)
DataAccessTime
—
0.6
5
200
3.6
—
—
—
—
—
—
—
—
—
—
—
—
3.6
3.6
3.6
10
—
0.6
6
166
3.7
—
—
—
—
—
—
—
—
—
—
—
—
3.7
3.7
3.7
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock High Time
2.3
2.3
1.5
0.5
1.5
0.5
30
2.7
2.7
2.0
0.5
2.0
0.5
30
Clock Low Time
DataSetupTime
tDH
DataHoldTime
tENS
tENH
tRS
EnableSetupTime
EnableHoldTime
ResetPulseWidth
tRSS
tRSR
tPRSS
tPRSH
ResetSetupTime
15
15
ResetRecoveryTime
10
10
PartialResetSetup
1.5
0.5
0.6
0.6
0.6
—
100
45
2.0
0.5
0.6
0.6
0.6
—
100
45
PartialResetHold
(2)
tOLZ(OE-Qn)
OutputEnabletoOutputinLow-Impedance
OutputEnabletoOutputinHigh-Impedance
OutputEnabletoDataOutputValid
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
(2)
tOHZ
tOE
fC
tSCLK
tSCKH
tSCKL
tSDS
—
—
—
—
—
—
—
20
—
—
—
—
—
—
—
20
Serial Clock High
Serial Clock Low
45
45
SerialDataInSetup
20
20
tSDH
tSENS
tSENH
tSDO
tSENO
tSDOP
tSENOP
tPCWQ
tPCRQ
tAS
Serial Data In Hold
1.2
20
1.2
20
SerialEnableSetup
SerialEnableHold
1.2
—
—
1.5
1.5
20
1.2
—
—
1.5
1.5
20
SCLK to Serial Data Out
SCLK to Serial Enable Out
SerialDataOutPropagationDelay
SerialEnablePropagationDelay
ProgrammingCompletetoWriteQueueSelection
ProgrammingCompletetoReadQueueSelection
AddressSetup
20
20
3.7
3.7
—
—
—
—
3.6
3.6
—
—
—
—
3.6
3.6
3.6
3.6
3.7
3.7
—
—
—
3.7
3.7
—
—
—
—
3.7
3.7
3.7
3.7
20
20
1.5
1.0
—
—
1.5
0.5
1.5
1.0
0.6
0.6
0.6
0.6
2.5
1.5
—
—
2.0
0.5
2.0
0.5
0.6
0.6
0.6
0.6
tAH
Address Hold
tWFF
tROV
tSTS
Write Clock to Full Flag
ReadClocktoOutputValid
PAE/PAF Strobe Setup
PAE/PAF Strobe Hold
QueueSetup
tSTH
tQS
tQH
QueueHold
tWAF
tRAE
WCLK to PAF flag
RCLK to PAE flag
Write ClocktoSynchronous Almost-FullFlagBus
Read Clock to Synchronous Almost-Empty Flag Bus
tPAF
tPAE
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
15
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(CONTINUED)
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72T51233L5
IDT72T51243L5
IDT72T51253L5
IDT72T51233L6
IDT72T51243L6
IDT72T51253L6
Symbol
tERCLK
Parameter
RCLK to Echo RCLK Output
Min.
—
—
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4
Max.
Min.
—
—
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4.5
6
Max.
4.2
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.0
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
—
—
—
—
—
tCLKEN
RCLK to Echo REN Output
(2)
tPAELZ
RCLK to PAE Flag Bus to Low-Impedance
RCLK to PAE Flag Bus to High-Impedance
WCLK to PAF Flag Bus to Low-Impedance
WCLK to PAF Flag Bus to High-Impedance
WCLKtoFullFlagtoHigh-Impedance
WCLKtoFullFlagtoLow-Impedance
(2)
tPAEHZ
(2)
tPAFLZ
(2)
tPAFHZ
(2)
tFFHZ
(2)
tFFLZ
(2)
tOVLZ
RCLKtoOutputValidFlagtoLow-Impedance
RCLKtoOutputValidFlagtoHigh-Impedance
WCLK to PAF Bus Sync to Output
WCLK to PAF Bus Expansion to Output
RCLK to PAE Bus Sync to Output
RCLK to PAE Bus Expansion to Output
SKEW time between RCLK and WCLK for FF and OV
SKEW time between RCLK and WCLK for PAF and PAE
SKEW time between RCLK and WCLK for PAF[0:3] and PAE[0:3]
SKEW time between RCLK and WCLK for OV
ExpansionInputSetup
(2)
tOVHZ
tFSYNC
tFXO
tESYNC
tEXO
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tXIS
5
—
5
6
—
5
6
—
1.0
0.5
1.0
0.5
—
tXIH
ExpansionInputHold
—
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
16
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
active,LOW.Upondetectionofcompletionofprogramming,theusershould
ceaseallprogrammingandtakeSENIinactive,HIGH.Note,SENOfollowsSENI
onceprogrammingofadeviceiscomplete.Therefore,SENOwillgoLOWafter
programmingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENO
willalsogoHIGH.TheoperationoftheSOoutputissimilar,whenprogramming
ofagivendeviceiscomplete,theSOoutputwillfollowtheSIinput.
FUNCTIONALDESCRIPTION
MASTERRESET
AMasterResetisperformedbytogglingtheMRSinputfromHIGHtoLOW
toHIGH.Duringamasterresetallinternalmulti-queuedevicesetupandcontrol
registersareinitializedandrequireprogrammingeitherseriallybytheuservia
theserialport,orusingthedefaultsettings.Duringamasterresetthestateof
thefollowinginputsdeterminethefunctionalityofthepart,thesepinsshouldbe
held HIGH or LOW.
FM – Flag bus Mode
IW,OW–BusMatchingoptions
MAST – Master Device
ID0, 1, 2 – Device ID
DFM–Programmingmode,serialordefault
DF – Offset value for PAE and PAF
Onceamasterresethastakenplace,thedevicemustbeprogrammedeither
seriallyorviathedefaultmethodbeforeanyread/writeoperationscanbegin.
See Figure 5, Master Reset for relevant timing.
Ifdevicesarebeingusedinexpansionmodetheserialportsofdevicesshould
becascaded.Theusercanloadalldevicesviatheserialinputportcontrolpins,
SI & SENI, of the first device in the chain. Again, the user may utilize the ‘C’
programtogeneratetheserialbitstream,theprogrampromptingtheuserfor
the numberofdevices tobe programmed. The SENO andSO(serialout)of
thefirstdeviceshouldbeconnectedtotheSENI andSIinputs ofthesecond
devicerespectivelyandsoon,withtheSENO&SOoutputsconnectingtothe
SENI&SIinputsofalldevicesthroughthechain.Alldevicesinthechainshould
beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould
be monitored by the user. When SENO of the final device goes LOW, this
indicates thatserialprogrammingofalldevices has beensuccessfullycom-
pleted.Upondetectionofcompletionofprogramming,theusershouldceaseall
programmingandtakeSENIofthefirstdeviceinthechaininactive,HIGH.
Asmentioned,thefirstdeviceinthechainhasitsserialinputportcontrolled
bytheuser,thisisthefirstdevicetohaveitsinternalregistersseriallyloaded
bytheserialbitstream.Whenprogrammingofthisdeviceiscompleteitwilltake
its SENOoutputLOWandbypasstheserialdataloadedontheSIinputtoits
SOoutput.Theserialinputoftheseconddeviceinthechainisnowloadedwith
thedatafromtheSOofthefirstdevice,whiletheseconddevicehasitsSENI
input LOW. This process continues through the chain until all devices are
programmedandtheSENO ofthefinaldevicegoesLOW.
PARTIALRESET
APartialResetisameansbywhichtheusercanresetboththereadandwrite
pointers of a single queue that has been setup within a multi-queue device.
Beforeapartialresetcantakeplaceonaqueue,therespectivequeuemustbe
selectedonboththereadportandwriteportaminimumof2RCLKand2WCLK
cyclesbeforethePRSgoesLOW.Thepartialresetisthenperformedbytoggling
thePRSinputfromHIGHtoLOWtoHIGH,maintainingtheLOWstateforatleast
oneWCLKandoneRCLKcycle.Onceapartialresethastakenplaceaminimum
of3WCLKand3RCLKcyclesmustoccurbeforeenabledwritesorreadscan
occur.
Once all serial programming has been successfully completed, normal
operations,(queueselectionsonthereadandwriteports)maybegin.When
connectedinexpansionmode,theIDT72T51233/72T51243/72T51253de-
vicesrequireatotalnumberofseriallyloadedbitsperdevicetocompleteserial
programming,(SCLKcycleswithSENIenabled),calculatedby:n[19+(Qx72)]
whereQis thenumberofqueues theuserwishes tosetupwithinthedevice,
where n is the number of devices in the chain.
APartialResetonlyresets thereadandwritepointers ofagivenqueue,a
partialresetwillnoteffecttheoverallconfigurationandsetupofthemulti-queue
deviceandits queues.
See Figure 6, PartialReset for relevant timing.
SERIAL PROGRAMMING
SeeFigure7,SerialPortConnectionandFigure8,SerialProgrammingfor
connectionandtiminginformation.
The multi-queue flow-control devices is a fully programmable device,
providingtheuserwithflexibilityinhowqueuesareconfiguredintermsofthe
numberofqueues,depthofeachqueueandpositionofthePAF/PAEflagswithin
respectivequeues.Alluserprogrammingisdoneviatheserialportafteramaster
resethas takenplace. Internallythe multi-queue device has setupregisters
whichmustbeseriallyloaded,theseregisterscontainvaluesforeveryqueue
within the device, such as the depth and PAE/PAF offset values. The
IDT72T51233/72T51243/72T51253 devices are capable of up to 4 queues
andthereforecontain4setsofregistersforthesetupofeachqueue.
DuringaMasterResetiftheDFM(DefaultMode)inputisLOW,thenthedevice
willrequire serialprogrammingbythe user. Itis recommendedthatthe user
utilizea‘C’programprovidedbyIDT,thisprogramwillprompttheuserforall
informationregardingthemulti-queuesetup.Theprogramwillthengenerate
aserialbitstreamwhichshouldbeseriallyloadedintothedeviceviatheserial
port.FortheIDT72T51233/72T51243/72T51253devicestheserialprogram-
mingrequiresatotalnumberofseriallyloadedbitsperdevice,(SCLKcycleswith
SENIenabled),calculatedby:19+(Qx72)whereQisthenumberofqueuesthe
userwishestosetupwithinthedevice.
DEFAULTPROGRAMMING
Duringa MasterResetifthe DFM(DefaultMode)inputis HIGHthe multi-
queuedevicewillbeconfiguredfordefaultprogramming,(serialprogramming
is not permitted). Default programming provides the user with a simpler,
howeverlimitedmeansbywhichtosetupthemulti-queueflow-controldevices,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possiblearesetup,withallofthepartsavailablememoryblocksbeingallocated
equallybetweenthequeues.ThevaluesofthePAE/PAFoffsetsisdetermined
bythe state ofthe DF(default)pinduringa masterreset.
FortheIDT72T51233/72T51243/72T51253devicesthedefaultmodewill
setup4queues,eachqueueconfiguredasfollows:FortheIDT72T51233with
x9 input and x9 output ports, 16,384 x 9. If one or both ports is x18, 8,192 x
18. FortheIDT72T51243withx9inputandx9outputports,32,768x9.Ifone
or both ports is x18, 16,384 x 18. For the IDT72T51253 with x9 input and x9
outputports,65,536x9.Ifoneorbothportsisx18,32,768x18.Forbothdevices
thevalueofthePAE/PAFoffsetsisdeterminedatmasterresetbythestateof
theDFinput.IfDFisLOWthenboththePAE&PAFoffsetwillbe8,ifHIGHthen
the value is 128.
Once the master reset is complete and MRS is HIGH, the device can be
seriallyloaded.DatapresentontheSI(serialin),inputisloadedintotheserial
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
enable),isLOW.Onceserialprogrammingofthedevicehasbeensuccessfully
completedthedevicewillindicatethisviatheSENO(serialoutputenable)going
WhenconfiguringtheIDT72T51233/72T51243/72T51253devicesinde-
faultmodetheusersimplyhastoapplyWCLKcyclesafteramasterreset,until
17
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SENOgoesLOW,thissignalsthatdefaultprogrammingiscomplete.Theseclock AqueuetobewrittentoneedonlybeselectedonasinglerisingedgeofWCLK.
cyclesarerequiredforthedevicetoloaditsinternalsetupregisters.Whena Allsubsequentwriteswillbewrittentothatqueueuntilanewqueueisselected.
singlemulti-queuedeviceis used,thecompletionofdeviceprogrammingis Aminimumof3WCLKcyclesmustoccurbetweenqueueselectionsonthewrite
signaledbytheSENOoutputofadevicegoingfromHIGHtoLOW.Note,that port.OnthenextWCLKrisingedgethewriteportdiscretefullflagwillupdate
SENImustbeheldLOWwhenadeviceissetupfordefaultprogrammingmode. toshowthefullstatusofthenewlyselectedqueue.Onthesecondrisingedge
Whenmulti-queuedevicesareconnectedinexpansionmode,theSENIof ofWCLK,datapresentonthedatainputbus,Dincanbewrittenintothenewly
the first device in a chain can be held LOW. The SENO of a device should selectedqueueprovidedthatWENisLOWandthenewqueueisnotfull.The
connecttotheSENIofthenextdeviceinthechain.TheSENOofthefinaldevice cycleofthequeueselectionandthenextcyclewillcontinuetowritedatapresent
isusedtoindicatethatdefaultprogrammingofalldevicesiscomplete.Whenthe onthedatainputbus,DinintothepreviousqueueprovidedthatWENisactive
finalSENOgoesLOWnormaloperationsmaybegin.Again,alldeviceswillbe LOW.
programmedwiththeirmaximumnumberofqueuesandthememorydivided
equally between them. Please refer to Figure 9, DefaultProgramming.
IfWENisHIGH,inactiveforthese3clockcycles,thendatawillnotbewritten
in to the previous queue.
Ifthenewlyselectedqueueisfullatthepointofitsselection,thenwritestothat
queue willbe prevented, a fullqueue cannotbe writteninto.
Inthe4queuemulti-queuedevicetheWRADDaddressbusis5bitswide.
WRITE QUEUE SELECTION & WRITE OPERATION
TheIDT72T51233/72T51243/72T51253multi-queueflow-controldevices
haveupto4queuesthatdatacanbewrittenintoviaacommonwriteportusing Theleastsignificant2bitsareusedtoaddressoneofthe4availablequeues
the data inputs, Din, write clock, WCLK and write enable, WEN. The queue withinasinglemulti-queuedevice.Themostsignificant3bitsareusedwhen
address present on the write address bus, WRADD during a rising edge on adeviceis connectedinexpansionmode,upto8devices canbeconnected
WCLKwhilewriteaddressenable,WADENisHIGH,isthequeueselectedfor inexpansion,eachdevicehavingits own3bitaddress.Theselecteddevice
writeoperations.ThestateofWENisdon’tcareduringthewritequeueselection istheoneforwhichtheaddressmatchesa3bitIDcode,whichisstaticallysetup
cycle.ThequeueselectiononlyhastobemadeonasingleWCLKcycle,this on the ID pins, ID0, ID1, and ID2 of each individual device.
willremainthe selectedqueue untilanotherqueue is selected, the selected
queueisalwaysthelastqueueselected.
Note,theWRADDbusisalsousedinconjunctionwithFSTR(almostfullflag
busstrobe),toaddressthealmostfullflagbusquadrantduringdirectmodeof
Thewriteportisdesignedsuchthat100%busutilizationcanbeobtained. operation.
ThismeansthatdatacanbewrittenintothedeviceoneveryWCLKrisingedge
RefertoTable1,forWriteAddressbusarrangement.Also,refertoFigure
includingthecyclethatanewqueueisbeingaddressed.Whenanewqueue 10, Write Queue Select, Write Operation and Full flag Operation in Single
isselectedforwriteoperationstheaddressforthatqueuemustbepresenton Device Mode and Figure 12, Full Flag Timing Expansion Mode for timing
theWRADDbusduringarisingedgeofWCLKprovidedthatWADENisHIGH. diagrams.
TABLE 1 — WRITE ADDRESS BUS, WRADD[4:0]
Operation WCLK WADEN FSTR
WRADD[4:0]
4 3 2
Device Select
(Compared to
ID0,1,2)
1 0
Write Queue Address
(2 bits = 4 Queues)
Write Queue
1
0
Select
4 3 2
1
0
PAFn Flag
Bus Device
Select
0
1
Device Select
(Compared to
ID0,1,2)
X
X
6115 drw05
18
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
READ QUEUE SELECTION & READ OPERATION
registerafter3RCLKcycles.Asmentioned,intheprevious3RCLKcyclesto
Themulti-queueflow-controldevices has upto4queues thatdatais read thenewdatabeingavailable,datacanstillbereadfromthepreviousqueue,
fromviaacommonreadportusingthedataoutputs,Qout,readclock,RCLK providedthatthequeueisnotempty.Atthepointofqueueselection,the internal
andreadenable,REN.Anoutputenable,OEcontrolpinisalsoprovidedtoallow datapipelineisloadedwiththelastwordfromthepreviousqueueandthenext
High-ImpedanceselectionoftheQoutdataoutputs.Themulti-queuedevice wordfromthenewqueue,boththesewordswillfallthroughtotheoutputregister
readportoperatesinamodesimilarto“FirstWordFallThrough”onatraditional consecutivelyuponselectionofthenewqueue.Thispipeliningeffectprovides
IDT FIFO, but with the added feature of data output pipelining. This data theuserwith100%busutilization,andbringsaboutthepossibilitythata“NULL”
pipeliningontheoutputportallows theusertoachieve100%bus utilization, queue maybe requiredwithina multi-queue device. Nullqueue operationis
which is the ability to read out a data word on every rising edge of RCLK discussedinthenextsectionon.
regardless of whether a new queue is being selected for read operations.
IfanemptyqueueisselectedforreadoperationsontherisingedgeofRCLK,
Thequeueaddresspresentonthereadaddressbus,RDADDduringarising onthesameRCLKedgeandthefollowingRCLKedge,2finalreadswillbemade
edge on RCLK while read address enable, RADEN is HIGH, is the queue fromthepreviousqueue,providedthatRENisactive,LOW.OnthenextRCLK
selectedforreadoperations.Aqueuetobereadfromneedonlybeselected rising edge a read from the new queue will not occur, because the queue is
on a single rising edge of RCLK. All subsequent reads will be read from that empty.Thelastwordinthedataoutputregister(fromthepreviousqueue),will
queueuntilanewqueueisselected.Aminimumof3RCLKcyclesmustoccur remainthere,buttheoutputvalidflag,OVwillgoHIGH,toindicatethatthedata
betweenqueueselectionsonthereadport.Datafromthenewlyselectedqueue present is no longer valid.
willbepresentontheQoutoutputsafter3RCLKcyclesplusanaccesstime,
TheRDADDbusisalsousedinconjunctionwithESTR(almostemptyflag
providedthatOEisactive,LOW.OnthesameRCLKrisingedgethatthenew busstrobe),toaddressthealmostemptyflagbusquadrantduringdirectmode
queueis selected,datacanstillbereadfromthepreviouslyselectedqueue, ofoperation.Inthe4queuemulti-queuedevicetheRDADDaddressbusis5
providedthatRENisLOW,activeandthepreviousqueueisnotemptyonthe bitswide.Theleastsignificant2bitsareusedtoaddressoneofthe4available
followingrisingedgeofRCLKawordwillbereadfromthepreviouslyselected queueswithinasinglemulti-queuedevice.Themostsignificant3bitsareused
queueregardlessofRENduetothefallthroughoperation,(providedthequeue when a device is connected in expansion mode, up to 8 devices can be
isnotempty). RememberthatOEallowstheusertoplacetheQout,dataoutput connectedinexpansion,eachdevicehavingitsown3bitaddress.Theselected
bus into High-Impedance and the data can be read onto the output register deviceistheoneforwhichtheaddressmatchesa3bitIDcode,whichisstatically
regardlessofOE.
setup on the ID pins, ID0, ID1, and ID2 of each individual device.
RefertoTable2,forReadAddressbusarrangement.Also,refertoFigures
Whenaqueueis selectedonthereadport, thenextwordavailableinthat
queue (provided that the queue is not empty), will fall through to the output 13,15&16forreadqueueselectionandreadportoperationtimingdiagrams.
TABLE 2 — READ ADDRESS BUS, RDADD[4:0]
Operation
RCLK RADEN ESTR
Null-Q
0
RDADD[4:0]
4 3 2
1 0
Read Queue
Select
1
0
1
0
1
0
Device Select
(Compared to
ID0,1,2)
Read Queue Address
(2 bits = 4 Queues)
4 3 2
Device Select
(Compared to
ID0,1,2)
1
X
0
PAEn Flag
Bus Device
Select
0
1
X
4 3 2
1
X
0
Null Queue
Select
X
X
X
X
6115 drw06
19
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NULL QUEUE OPERATION (OF THE READ PORT)
FULL FLAG OPERATION
Pipeliningofdatatotheoutputportenablesthedevicetoprovide100%bus
Themulti-queueflow-controldevicesprovidesasingleFullFlagoutput,FF.
utilizationinstandardmode.Datacanbereadoutofthemulti-queueflow-control TheFFflagoutputprovidesafullstatusofthequeuecurrentlyselectedonthe
deviceoneveryRCLKcycleregardlessofqueueswitchesorotheroperations. writeportforwriteoperations.Internallythemulti-queueflow-controldevice
Thedevicearchitectureissuchthatthepipelineisconstantlyfilledwiththenext monitorsandmaintainsastatusofthefullconditionofallqueueswithinit,however
wordsinaselectedqueuetobereadout,againproviding100%busutilization. onlythequeuethatisselectedforwriteoperationshasitsfullstatusoutputtothe
This type of architecture does assume that the user is constantly switching FF flag.This dedicatedflagis oftenreferredtoas the“activequeuefullflag”.
queuessuchthatduringaqueueswitch,thelastdatawordrequiredfromthe
previousqueuewillfallthroughthepipelinetotheoutput.
Whenqueueswitchesarebeingmadeonthewriteport,theFFflagoutput
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
Note,thatifreadsceaseattheemptyboundaryofaqueue,thenthelastword onthecycleafteranewqueueselectionismade.Theuserthenhasafullstatus
willautomaticallyflowthroughthepipelinetotheoutput. forthenewqueueonecycleaheadoftheWCLKrisingedgethatdatacanbe
The NullQoperationis achievedbysettingthe NullQsignalHIGHduring writtenintothenewqueue.Thatis,anewqueuecanbeselectedonthewrite
aqueueselect.NotethatthereadaddressbusRDADD[4:0]isadon'tcare.The portviatheWRADDbus,WADENenableandarisingedgeofWCLK.Onthe
NullQueueisaseparatequeuewithinthedeviceandthusthemaximumnumber secondrisingedgeofWCLK,theFFflagoutputwillshowthefullstatusofthe
ofqueuesandmemoryisalwaysavailableregardlessofwhetherornottheNull newlyselectedqueue.OnthethirdrisingedgeofWCLKfollowingthequeue
queue is used. Also note that in expansion mode a user may want to use a selection,datacanbewrittenintothenewlyselectedqueueprovidedthatdata
dedicatednullqueueforeachdevice.Anullqueuecanbeselectedwhenno andenablesetup&holdtimesaremet.
furtherreadsarerequiredfromapreviouslyselectedqueue.Changingtoanull
Note,theFFflagwillprovidestatusofanewlyselectedqueuetwoWCLKcycle
queuewillcontinuetopropagatedatainthepipelinetothepreviousqueue's afterqueueselection,whichisonecyclebeforedatacanbewrittentothatqueue.
output.TheNullQcanremainselecteduntiladatabecomesavailableinanother Thispreventstheuserfromwritingdatatoaqueuethatisfull,(assumingthat
queueforreading.TheNull-Qcanbeutilizedineitherstandardorpacketmode. a queue switchhas beenmade toa queue thatis actuallyfull).
Note:Iftheuserswitchesthereadporttothenullqueue,thisqueueisseen
TheFFflagissynchronoustotheWCLKandalltransitionsoftheFFflagoccur
asandtreatedasanemptyqueue,thereforeafterswitchingtothenullqueue basedonarisingedgeofWCLK.Internallythemulti-queuedevicemonitorsand
thelastwordfromthepreviousqueuewillremainintheoutputregisterandthe keepsarecordofthefullstatusforallqueues.Itispossiblethatthestatusofa
OVflagwillgoHIGH,indicatingdatais notvalid.
FFflagmaybechanginginternallyeventhoughthatflagisnottheactivequeue
TheNullqueueoperationonlyhassignificancetothereadportofthemulti- flag (selected on the write port). A queue selected on the read port may
queue, it is a means to force data through the pipeline to the output. Null Q experienceachangeofitsinternalfullflagstatusbasedonreadoperations.
selectionandoperationhasnomeaningonthewriteportofthedevice.Also,
refer to Figure 17, Read Operation and Null Queue Select for diagram.
See Figure 10, Write Queue Select, Write Operation and Full Flag
OperationinSingleDeviceModeandFigure12,FullFlagTiminginExpansion
Modefortiminginformation.
BUS MATCHING OPERATION
BusMatchingoperationbetweentheinputportandoutputportisavailable. EXPANSION MODE - FULL FLAG OPERATION
Duringamasterresetofthemulti-queuethestateofthetwosetuppins,IW(Input
Whenmulti-queuedevicesareconnectedinExpansionmodetheFFflags
Width)andOW(OutputWidth)determinetheinputandoutputportbuswidths of all devices should be connected together, such that a system controller
as pertheselections showninTable3,“Bus MatchingSet-up”.9bitbytes or monitoring and managing the multi-queue devices write port only looks at a
18bitwordscanbewrittenintoandreadformthequeues.Whenwritingtoor singleFFflag(asopposedtoadiscreteFFflagforeachdevice).ThisFFflag
readingfromthemulti-queueinabusmatchingmode,thedeviceordersdatain isonlypertinenttothequeuebeingselectedforwriteoperationsatthattime.
a“LittleEndian”format.SeeFigure3,BusMatchingByteArrangementfordetails. Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe
TheFullflagandAlmostFullflagoperationis always basedonwrites and writtentoatanymomentintime,thustheFFflagprovidesstatusoftheactive
readsofdatawidthsdeterminedbythewriteportwidth.Forexample,iftheinput queue on the write port.
portisx18andtheoutputportisx9,thentwodatareadsfromafullqueuewill
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheFFflag
berequiredtocausethefullflagtogoHIGH(queuenotfull).Conversely,the outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis
OutputValidflagandAlmostEmptyflagoperationsarealwaysbasedonwrites madeonlyasingledevicedrivestheFFflagbusandallotherFF flagoutputs
andreadsofdatawidthsdeterminedbythereadport.Forexample,iftheinputport connectedtotheFFflagbusareplacedintoHigh-Impedance.Theuserdoes
isx9andtheoutputportisx18,twowriteoperationswillberequiredtocausethe nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control
outputvalidflagofanemptyqueuetogoLOW,outputvalid(queueisnotempty). deviceswillautomaticallyplaceitsFFflagoutputintoHigh-Impedancewhen
Note,thattheinputportservesallqueueswithinadevice,asdoestheoutput noneofitsqueuesareselectedforwriteoperations.
port,thereforetheinputbuswidthtoallqueuesisequal(determinedbytheinput
portsize)andtheoutputbuswidthfromallqueuesisequal(determinedbythe flagoutputofthatdevicewillmaintaincontroloftheFFflagbus.ItsFFflagwill
outputportsize).
Whenqueueswithinasingledeviceareselectedforwriteoperations,theFF
simplyupdatebetweenqueueswitchestoshowtherespectivequeuefullstatus.
Themulti-queuedeviceplacesitsFFflagoutputintoHigh-Impedancebased
onthe3bitIDcodefoundinthe3mostsignificantbitsofthewritequeueaddress
bus,WRADD.Ifthe3mostsignificantbitsofWRADDmatchthe3bitIDcodesetup
onthestaticinputs,ID0,ID1andID2thentheFFflagoutputoftherespective
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheFFflag
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure
12,FullFlagTiminginExpansionModefordetailsofflagoperation,including
when more than one device is connected in expansion.
TABLE 3 — BUS-MATCHING SET-UP
IW
OW
Write Port
Read Port
0
0
1
1
0
1
0
1
x18
x18
x9
x18
x9
x18
x9
x9
20
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OUTPUTVALIDFLAGOPERATION
14,OutputValidFlagTimingfordetailsofflagoperation,includingwhenmore
The multi-queue flow-control devices provides a single Output Valid flag thanone device is connectedinexpansion.
output,OV.TheOVprovidesanemptystatusordataoutputvalidstatusforthe
datawordcurrentlyavailableontheoutputregisterofthereadport.Therising ALMOST FULL FLAG
edgeofanRCLKcyclethatplacesnewdataontotheoutputregisteroftheread
As previouslymentionedthemulti-queueflow-controldevices provides a
port, also updates the OV flag to show whether or not that new data word is singleProgrammableAlmostFullflagoutput,PAF.ThePAFflagoutputprovides
actually valid. Internally the multi-queue flow-control device monitors and astatusofthealmostfullconditionfortheactivequeuecurrentlyselectedonthe
maintainsastatusoftheemptyconditionofallqueueswithinit,howeveronly writeportforwriteoperations.Internallythemulti-queueflow-controldevice
thequeuethatisselectedforreadoperationshasitsoutputvalid(empty)status monitorsandmaintainsastatusofthealmostfullconditionofallqueueswithin
outputtotheOVflag,givingavalidstatusforthewordbeingreadatthattime. it,howeveronlythequeuethatisselectedforwriteoperationshasitsfullstatus
Thenatureofthefirstwordfallthroughoperationmeansthatwhenthelast outputtothePAFflag.Thisdedicatedflagisoftenreferredtoasthe“activequeue
datawordisreadfromaselectedqueue,theOVflagwillgoHIGHonthenext almostfullflag”.ThepositionofthePAFflagboundarywithinaqueuecanbe
enabled read, that is, on the next rising edge of RCLK while REN is LOW.
atanypointwithinthatqueuesdepth.Thislocationcanbeuserprogrammed
Whenqueueswitchesarebeingmadeonthereadport,theOVflagwillswitch viatheserialportoroneofthedefaultvalues(8or128)canbeselectedifthe
toshowstatusofthenewqueueinlinewiththedataoutputfromthenewqueue. userhasperformeddefaultprogramming.
Whenaqueueselectionismadethefirstdatafromthatqueuewillappearon
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost
theQoutdataoutputs3RCLKcycleslater,theOVwillchangestatetoindicate fullstatus,whenaqueueisselectedonthewriteport,thisstatusisoutputviathe
validityofthedatafromthenewlyselectedqueueonthis3rd RCLKcyclealso. PAFflag.ThePAFflagvalueforeachqueueisprogrammedduringmulti-queue
Thepreviouscycleswillcontinuetooutputdatafromthepreviousqueueand device programming (along with the number of queues, queue depths and
theOVflagwillindicatethestatusofthoseoutputs.Again,theOVflagalways almostemptyvalues).ThePAFoffsetvalue,m,forarespectivequeuecanbe
indicatesstatusforthedatacurrentlypresentontheoutputregister.
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory
TheOVflagissynchronoustotheRCLKandalltransitionsoftheOVflagoccur depthforthatqueue.ThePAFvalueofdifferentqueueswithinthesamedevice
basedonarisingedgeofRCLK.Internallythemulti-queuedevicemonitorsand canbedifferentvalues.
keepsarecordoftheoutputvalid(empty)statusforallqueues.Itispossiblethat
Whenqueueswitchesarebeingmadeonthewriteport,thePAFflagoutput
thestatusofanOVflagmaybechanginginternallyeventhoughthatrespective willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
flagisnottheactivequeueflag(selectedonthereadport).Aqueueselected onthethirdcycleafteranewqueueselectionismade,onthesameWCLKcycle
onthewriteportmayexperienceachangeofitsinternalOVflagstatusbased thatdata canactuallybe writtentothe newqueue. Thatis, a newqueue can
on write operations, that is, data may be written into that queue causing it to beselectedonthewriteportviatheWRADDbus,WADENenableandarising
become“notempty”.
edgeofWCLK.OnthethirdrisingedgeofWCLKfollowingaqueueselection,
SeeFigure13,ReadQueueSelect,ReadOperationinSingleDeviceMode thePAFflagoutputwillshowthefullstatusofthenewlyselectedqueue.ThePAF
andFigure 14, OutputValidFlagTimingfordetails ofthe timing.
isflagoutputistripleregisterbuffered,sowhenawriteoperationoccursatthe
almostfullboundarycausingtheselectedqueuestatustogoalmostfullthePAF
willgoLOW3WCLKcyclesafterthewrite.Thesameistruewhenareadoccurs,
EXPANSION MODE – OUTPUT VALID FLAG OPERATION
Whenmulti-queuedevicesareconnectedinExpansionmode,theOVflags there will be a 3 WCLK cycle delay after the read operation.
of all devices should be connected together, such that a system controller
monitoring and managing the multi-queue devices read port only looks at a
singleOVflag(asopposedtoadiscreteOVflagforeachdevice).ThisOVflag
is onlypertinenttothequeuebeingselectedforreadoperations atthattime.
Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe
So the PAF flag delays are:
froma write operationtoPAF flagLOWis 2WCLK+tWAF
ThedelayfromareadoperationtoPAFflagHIGHistSKEW2+WCLK+tWAF
Note, if tSKEW is violated there will be one added WCLK cycle delay.
ThePAFflagissynchronoustotheWCLKandalltransitionsofthePAFflag
readfromatanymomentintime,thustheOVflagprovidesstatusoftheactive occur based on a rising edge of WCLK. Internally the multi-queue device
queue on the read port. monitorsandkeepsarecordofthealmostfullstatusforallqueues.Itispossible
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheOVflag thatthestatusofaPAFflagmaybechanginginternallyeventhoughthatflagis
outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis nottheactivequeueflag(selectedonthewriteport).Aqueueselectedonthe
madeonlyasingledevicedrivestheOVflagbusandallotherOVflagoutputs readportmayexperienceachangeofitsinternalalmostfullflagstatusbased
connectedtotheOVflagbusareplacedintoHigh-Impedance.Theuserdoes on read operations. The multi-queue flow-control devices also provides a
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control duplicateofthePAFflagonthePAF[3:0]flagbus,thiswillbediscussedindetail
deviceswillautomaticallyplaceitsOVflagoutputintoHigh-Impedancewhen inalatersectionofthedatasheet.
noneofits queues areselectedforreadoperations.
SeeFigures 19and20forAlmostFullflagtimingandqueueswitching.
Whenqueueswithinasingledeviceareselectedforreadoperations,theOV
flagoutputofthatdevicewillmaintaincontroloftheOVflagbus.ItsOVflagwill ALMOSTEMPTYFLAG
simplyupdatebetweenqueueswitchestoshowtherespectivequeueoutput
validstatus.
As previouslymentionedthemulti-queueflow-controldevices provides a
single Programmable Almost Empty flag output, PAE. The PAE flag output
Themulti-queuedeviceplacesitsOVflagoutputintoHigh-Impedancebased providesastatusofthealmostemptyconditionfortheactivequeuecurrently
onthe3bitIDcodefoundinthe3mostsignificantbitsofthereadqueueaddress selectedonthereadportforreadoperations.Internallythemulti-queueflow-
bus,RDADD.Ifthe3mostsignificantbitsofRDADDmatchthe3bitIDcodesetup controldevicemonitorsandmaintainsastatusofthealmostemptyconditionof
onthestaticinputs,ID0,ID1andID2thentheOVflagoutputoftherespective allqueueswithinit,howeveronlythequeuethatisselectedforreadoperations
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheOVflag hasitsemptystatusoutputtothePAEflag.Thisdedicatedflagisoftenreferred
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure toasthe“activequeuealmostemptyflag”.ThepositionofthePAEflagboundary
21
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
withinaqueuecanbeatanypointwithinthatqueuesdepth.Thislocationcan POWER DOWN (PD)
beuserprogrammedviatheserialportoroneofthedefaultvalues(8or128)
canbeselectediftheuserhasperformeddefaultprogramming.
This device has a power down feature intended for reducing power
consumptionforHSTL/eHSTLconfiguredinputswhenthedeviceisidlefora
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost long period of time. By entering the power down state certain inputs can be
emptystatus,whenaqueueisselectedonthereadport,thisstatusisoutputvia disabled,therebysignificantlyreducingthepowerconsumptionofthepart.All
thePAEflag.ThePAEflagvalueforeachqueueisprogrammedduringmulti- WENandRENsignalsmustbedisabledforaminimumoffourWCLKandRCLK
queuedeviceprogramming(alongwiththenumberofqueues,queuedepths cycles before activating the power down signal. The power down signal is
andalmostfullvalues).ThePAEoffsetvalue,n,forarespectivequeuecanbe asynchronousandneedstobeheldLOWthroughoutthedesiredpowerdowntime.
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory Duringpowerdown,thefollowingconditionsfortheinputs/outputssignalsare:
depthforthatqueue.ThePAEvalueofdifferentqueueswithinthesamedevice
canbedifferentvalues.
• Alldata inQueue(s)memoryare retained.
• Alldatainputsbecomeinactive.
Whenqueueswitchesarebeingmadeonthereadport,thePAEflagoutput
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
onthethirdcycleafteranewqueueselectionismade,onthesameRCLKcycle
thatdataactuallyfallsthroughtotheoutputregisterfromthenewqueue.That
is,anewqueuecanbeselectedonthereadportviatheRDADDbus,RADEN
enableandarisingedgeofRCLK.OnthethirdrisingedgeofRCLKfollowing
a queue selection, the data wordfromthe newqueue willbe available atthe
outputregisterandthePAEflagoutputwillshowtheemptystatusofthenewly
selectedqueue.ThePAEisflagoutputistripleregisterbuffered,sowhenaread
operationoccurs atthealmostemptyboundarycausingtheselectedqueue
statustogoalmostemptythePAEwillgoLOW3RCLKcyclesaftertheread.
Thesameistruewhenawriteoccurs,therewillbea3RCLKcycledelayafter
thewriteoperation.
• Allwrite andreadpointers maintaintheirlastvalue before powerdown.
• Allenables,chipselects,andclockinputpinsbecomeinactive.
• Alldataoutputsbecomeinactiveandenterhigh-impedancestate.
• Allflagoutputswillmaintaintheircurrentstatesbeforepowerdown.
• Allprogrammableflagoffsetsmaintaintheirvalues.
• Allechoclocks andenables willbecomeinactiveandenterhigh-
impedancestate.
• TheserialprogrammingandJTAGportwillbecomeinactiveandenter
high-impedancestate.
• AllsetupandconfigurationCMOSstaticinputsarenotaffected,asthese
pins are tied to a known value and do not toggle during operation.
Allinternalcounters,registers,andflagswillremainunchangedandmaintain
theircurrentstatepriortopowerdown.Clockinputscanbecontinuousandfree-
runningduringpowerdown,butwillhavenoaffectonthepart.However,itis
recommendedthattheclockinputsbelowwhenthepowerdownisactive.To
So the PAE flag delays are:
from a read operation toPAE flag LOW is 2 RCLK + tRAE
ThedelayfromawriteoperationtoPAEflagHIGHistSKEW2+RCLK+tRAE exitpowerdownstateandresumenormaloperations,disablethepowerdown
Note, if tSKEW is violated there will be one added RCLK cycle delay.
signalbybringingitHIGH.Theremustbeaminimumof1µswaitingperiodbefore
ThePAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag readandwriteoperationscanresume.Thedevicewillcontinuefromwhereit
occur based on a rising edge of RCLK. Internally the multi-queue device hadstoppedandnoformofresetisrequiredafterexitingpowerdownstate.The
monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible powerdownfeaturedoesnotprovideanypowersavingswhentheinputsare
thatthestatusofaPAEflagmaybechanginginternallyeventhoughthatflagis configuredforLVTTLoperation.However,itwillreducethecurrentforI/Osthat
nottheactivequeueflag(selectedonthereadport).Aqueueselectedonthe are not tied directly to VCC or GND. See Figure 28, Power Down Operation,
writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased fortheassociatedtimingdiagram.
on write operations. The multi-queue flow-control devices also provides a
duplicateofthePAEflagonthePAE[3:0]flagbus,thiswillbediscussedindetail
inalatersectionofthedatasheet.
SeeFigures21and22forAlmostEmptyflagtimingandqueueswitching.
22
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
Output Valid, OV Flag Boundary
Full Flag, FF Boundary
I/O Set-Up
OV Boundary Condition
I/O Set-Up
FF Boundary Condition
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenotebelowfortiming)
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after D+1 Writes
(seenotebelowfortiming)
In18 to out9)
OV Goes LOW after 1st Write
(seenotebelowfortiming)
In18 to out18 or In9 to out9
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
In9 to out18
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 2nd Write
(seenotebelowfortiming)
In18 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
In18 to out9
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after D Writes
NOTE:
1. OV Timing
Assertion:
(seenotebelowfortiming)
Write to OV LOW: tSKEW1 + RCLK + tROV
If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV
De-assertion:
In9 to out18
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 2) Writes
(seenotebelowfortiming)
Read Operation to OV HIGH: tROV
In9 to out18
FF Goes LOW after (D x 2) Writes
(seenotebelowfortiming)
(Writeportonlyselectedforqueue
when the 1st Word is written in)
NOTE:
D = Queue Depth
FF Timing
Assertion:
Write Operation to FF LOW: tWFF
De-assertion:
Read to FF HIGH: tSKEW1 + tWFF
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
I/O Set-Up
PAF & PAFn Boundary
In18 to out18 or In9 to out9
PAF/PAFn Goes LOW after
(Bothportsselectedforsamequeuewhenthe1st D+1-mWrites
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)
In18 to out18 or In9 to out9
PAF/PAFn Goes LOW after
(Writeportonlyselectedforsamequeuewhenthe D-mWrites
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
In18 to out9
In9 to out18
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(seenotebelowfortiming)
NOTE:
D = Queue Depth
m = Almost Full Offset value.
Default values: if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
Assertion:
Write Operation to PAF LOW: 2 WCLK + tWAF
De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
Assertion:
Write Operation to PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
23
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag Bus, PAEn Boundary
Programmable Almost Empty Flag, PAE Boundary
I/O Set-Up
PAEn Boundary Condition
PAEn Goes HIGH after
I/O Set-Up
PAE Assertion
PAE Goes HIGH after n+2
In18 to out18 or In9 to out9
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeuewhenthe1st Writes
Wordiswritteninuntiltheboundaryisreached)
(Bothportsselectedforsamequeuewhenthe1st n+2Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
(seenotebelowfortiming)
In18 to out18 or In9 to out9
PAEn Goes HIGH after
In18 to out9
PAE Goes HIGH after n+1
(Writeportonlyselectedforsamequeuewhenthe n+1Writes
(Bothportsselectedforsamequeuewhenthe1st Writes
Wordiswritteninuntiltheboundaryisreached)
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
(seenotebelowfortiming)
In18 to out9
In9 to out18
PAEn Goes HIGH after n+1
Writes (seebelowfortiming)
In9 to out18
PAE Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
Wordiswritteninuntiltheboundaryisreached)
PAEn Goes HIGH after
(seenotebelowfortiming)
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
In9 to out18
PAEn Goes HIGH after
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 2) Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
PAE Timing
Assertion:
Read Operation to PAE LOW: 2 RCLK + tRAE
NOTE:
De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion:
Read Operation to PAEn LOW: 2 RCLK* + tPAE
De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
24
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PAFn FLAG BUS OPERATION
passing is done via the FXO outputs and FXI inputs of the devices (“PAFn
TheIDT72T51233/72T51243/72T51253multi-queueflow-controldevices ExpansionOut”and“PAFnExpansionIn”).TheFXOoutputofthefirstdevice
can be configured for up to 4 queues, each queue having its own almost full connectingtothe FXIinputofthe seconddevice inthe chain, the FXOofthe
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,FFandPAF, seconddeviceconnects totheFXIofthethirddeviceandsoon.TheFXOof
onthewriteport.Queuesthatarenotselectedforawriteoperationcanhave thefinaldeviceinachainconnectstotheFXIofthefirstdevice,sothatoncethe
theirPAFstatusmonitoredviathePAFnbus.ThePAFnflagbusis4bitswide, PAFn bus has cycled through all devices control is again passed to the first
sothatall4queuescanhavetheirstatusoutputtothebus.Whenasinglemulti- device.TheFXOoutputofadevicewillbeHIGHfortheWCLKcycleithascontrol
queuedeviceis usedanywherefrom1to4queues maybeset-upwithinthe ofthebus.
part,eachqueuehavingitsowndedicatedPAFflagoutputonthePAFnbus.
Queues 1 through 4 have their PAF status to PAF[0] through PAF[3]
PleaserefertoFigure26,PAFnBus–PolledModefortiminginformation.
respectively. If less than 4 queues are used then only the associated PAFn PAEn FLAG BUS OPERATION
outputswillberequired,unusedPAFnoutputswillbedon’tcareoutputs.When
The IDT72T51233/72T51243/72T51253 multi-queue flow-control de-
devicesareconnectedinexpansionmodethePAFnflagbuscanalsobeexpanded vicescanbeconfiguredforupto4queues,eachqueuehavingitsownalmost
beyond 4 bits toproduce a widerPAFnbus thatencompassesallqueues.
emptystatus.Anactivequeuehasitsflagstatusoutputtothediscreteflags,OV
Alternatively,the4bitPAFnflagbusofeachdevicecanbeconnectedtogether andPAE,onthereadport.Queuesthatarenotselectedforareadoperation
toformasingle4bitbus,i.e.PAF[0]ofdevice1willconnecttoPAF[0]ofdevice canhavetheirPAEstatusmonitoredviathePAEnbus.ThePAEnflagbusis
2etc. Whenconnectingdevices inthis mannerthe PAFncanonlybe driven 4bits wide, sothatall4queues canhave theirstatus outputtothe bus. The
byasingledeviceatanytime,(thePAFnoutputsofallotherdevicesmustbe multi-queue device can provide “Almost Empty” status via the PAEnbus
inhighimpedancestate).Therearetwomethodsbywhichtheusercanselect ofits queues. Ifitis LOWthenthe PAEnbus willprovide “AlmostEmpty”
whichdevicehas controlofthebus,theseare“Direct”(Addressed)modeor status.
“Polled”(Looped)mode,determinedbythestateoftheFM(flagMode)input
duringaMasterReset.
Whenasinglemulti-queuedeviceisusedanywherefrom1to4queuesmay
beset-upwithinthepart,eachqueuehavingitsowndedicatedPAEnflagoutput
onthePAEnbus.Queues1through4havetheirPAEstatustoPAE[0]through
PAE[3]respectively.Iflessthan4queuesareusedthenonlytheassociated
PAFn BUS EXPANSION - DIRECT MODE
If FM is LOW at Master Reset then the PAFn bus operates in Direct PAEnoutputswillberequired,unusedPAEn outputswillbedon’tcareoutputs.
(addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire WhendevicesareconnectedinexpansionmodethePAEn flagbuscanalso
tocontrolthePAFnbus.Theaddresspresentonthe3mostsignificantbitsof beexpandedbeyond4bits toproduceawiderPAEnbus thatencompasses
the WRADD[4:0] address bus with FSTR (PAF flag strobe), HIGH will be allqueues.
selectedasthedeviceonarisingedgeofWCLK.Sotoaddressthefirstdevice
Alternatively, the 4 bit PAEn flag bus of each device can be connected
inabankofdevicestheWRADD[4:0]addressshouldbe“000xx”thesecond togethertoformasingle4bitbus,i.e.PAE[0]ofdevice1willconnecttoPAE[0]
device“001xx”andsoon.The3mostsignificantbitsoftheWRADD[4:0]address ofdevice2etc.WhenconnectingdevicesinthismannerthePAEnbuscanonly
buscorrespondtothedeviceIDinputsID[2:0].ThePAFnbuswillchangestatus bedrivenbyasingledeviceatanytime,(thePAEn outputsofallotherdevices
toshowthenewdeviceselected1WCLKcycleafterdeviceselection.Note,that mustbeinhighimpedancestate).Therearetwomethods bywhichtheuser
if a read or write operation is occurring to a specific queue, say queue ‘x’ on canselectwhichdevicehascontrolofthebus,theseare“Direct”(Addressed)
thesamecycleasaPAFnbusswitchtothedevicecontainingqueue‘x’,then modeor“Polled”(Looped)mode,determinedbythestateoftheFM(flagMode)
theremaybeanextraWCLKcycledelaybeforethatqueuesstatusiscorrectly inputduringaMasterReset.
shownontherespectiveoutputofthe PAFnbus.However,the“active”PAF
flagwillshowcorrectstatusatalltimes.
PAEn - DIRECT BUS
Devices can be selected on consecutive WCLK cycles, that is the device
If FM is LOW at Master Reset then the PAEn bus operates in Direct
controllingthePAFnbuscanchangeeveryWCLKcycle.Also,datapresenton (addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire
theinputbus,Din,canbewrittenintoaqueueonthesameWLCKrisingedge tocontrolthePAEnbus.Theaddresspresentonthe3mostsignificantbitsof
thatadeviceisbeingselectedonthePAFnbus,theonlyrestrictionbeingthat the RDADD[4:0] address bus with ESTR (PAE flag strobe), HIGH will be
awritequeueselectionandPAFnbusselectioncannotbemadeonthesame selectedasthedeviceonarisingedgeofRCLK.Sotoaddressthefirstdevice
cycle.
inabankofdevices theRDADD[4:0]address shouldbe“000xx”thesecond
device“001xx”andsoon.The3mostsignificantbitsoftheRDADD[5:0]address
buscorrespondtothedeviceIDinputsID[2:0].ThePAEnbuswillchangestatus
PAFn – POLLED BUS
IfFMisHIGHatMasterResetthenthePAFnbusoperatesinPolled(Looped) toshowthenewdeviceselected1RCLKcycleafterdeviceselection.Note,that
mode.InpolledmodethePAFnbusautomaticallycyclesthroughthedevices if a read or write operation is occurring to a specific queue, say queue ‘x’ on
connected in expansion. In expansion mode one device will be set as the thesamecycleasaPAEnbusswitchtothedevicecontainingqueue‘x’,then
Master,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtiedLOW.The theremaybeanextraRCLKcycledelaybeforethatqueuesstatusiscorrectly
masterdeviceisthefirstdevicetotakecontrolofthePAFnbusandplacethe shownontherespectiveoutputofthePAEnbus.However,the“active”PAE
PAFstatusofitsqueuesontothebusonthefirstrisingedgeofWCLKafterthe flagwillshowcorrectstatusatalltimes.
MRSinputgoesHIGHonceaMasterResetiscomplete.TheFSYNC(PAFsync
pulse)outputofthefirstdevice(masterdevice),willbeHIGHforonecycleof controllingthePAEnbuscanchangeeveryRCLKcycle.Also,datacanberead
WCLKindicatingthatitishascontrolofthePAFnbusforthatcycle. outofaqueueonthesameRCLKrisingedgethatadeviceis beingselected
Devices can be selected on consecutive RCLK cycles, that is the device
Thedevicealsopassesa“token”ontothenextdeviceinthechain,thenext onthePAEnbus,theonlyrestrictionbeingthatareadqueueselectionandPAEn
deviceassumingcontrolofthePAFnbusonthenextWCLKcycle.Thistoken busselectioncannotbemadeonthesamecycle.
25
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PAEn- POLLED BUS
Thedevicealsopassesa“token”ontothenextdeviceinthechain,thenext
If FM is HIGH at Master Reset then the PAEn bus operates in Polled deviceassumingcontrolofthePAEnbusonthenextRCLKcycle.Thistoken
(Looped)mode.InpolledmodethePAEnbusautomaticallycyclesthroughthe passing is done via the EXO outputs and EXI inputs of the devices (“PAEn
devices connectedinexpansion. Inexpansionmode one device willbe set ExpansionOut”and“PAEnExpansionIn”).TheEXOoutputofthefirstdevice
as theMaster,MASTinputtiedHIGH,allotherdevices willhaveMASTtied connectingtotheEXIinputoftheseconddeviceinthechain,theEXOofthe
LOW.ThemasterdeviceisthefirstdevicetotakecontrolofthePAEnbusand seconddeviceconnects totheEXIofthethirddeviceandsoon.TheEXOof
placethePAEstatusofitsqueuesontothebusonthefirstrisingedgeofRCLK thefinaldeviceinachainconnectstotheEXIofthefirstdevice,sothatoncethe
aftertheMRSinputgoesHIGHonceaMasterResetiscomplete.TheESYNC PAEn bus has cycled through all devices control is again passed to the first
(PAE syncpulse) output of the first device (master device), will be HIGH device.TheEXOoutputofadevicewillbeHIGHfortheRCLKcycleithascontrol
forone cycle ofRCLKindicatingthatitis has controlofthe PAEnbus for ofthebus.
thatcycle.
PleaserefertoFigure27,PAEnBus–PolledModefortiminginformation.
26
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ECHO READ CLOCK (ERCLK)
the slowest Qn, data output. Refer to Figure 3, Echo Read Clock and Data
TheEchoReadClockoutputisprovidedinbothHSTLandLVTTLmode, Output Relationship and Figure 23, Echo RCLK & Echo REN Operation for
selectableviaIOSEL.TheERCLKisafree-runningclockoutput,itwillalways timinginformation.
follow the RCLK input regardless of REN and RADEN.
TheERCLKoutputfollowstheRCLKinputwithanassociateddelay. This ECHO READ ENABLE (EREN)
delayprovidestheuserwithamoreeffectivereadclocksourcewhenreading
TheEchoReadEnableoutputisprovidedinbothHSTLandLVTTLmode,
datafromtheQnoutputs.Thisisespeciallyhelpfulathighspeedswhenvariables selectableviaIOSEL.
withinthedevicemaycausechangesinthedataaccesstimes. Thesevariations
The EREN output is provided to be used in conjunction with the ERCLK
inaccesstimemaybecausedbyambienttemperature,supplyvoltage,device outputandprovidesthereadingdevicewithamoreeffectiveschemeforreading
characteristics. The ERCLK output also compensates for any trace length datafromtheQnoutputportathighspeeds.TheERENoutputiscontrolledby
delaysbetweentheQndataoutputsandreceivingdevicesinputs.
internallogicthatbehavesasfollows:TheERENoutputisactiveLOWforthe
Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding RCLKcyclethatanewwordisreadoutofthequeue.Thatis,arisingedgeof
effectontheERCLKoutputproducedbythequeuedevice,thereforetheERCLK RCLKwillcause EREN togoactive (LOW)ifREN is active andthe queue is
outputleveltransitionsshouldalwaysbeatthesamepositionintimerelativeto NOTempty.
thedataoutputs.Note,thatERCLKisguaranteedbydesigntobeslowerthan
RCLK
tERCLK
tERCLK
ERCLK
tD
tA
Q
SLOWEST(3)
6115 drw08
NOTES:
1. REN is LOW. OE is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
Figure 3. Echo Read Clock and Data Output Relationship
27
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
B
Write to Queue
A
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE
IW
L
OW
L
A
B
Read from Queue
L
(a) x18 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
L
B
A
Read from Queue
H
(b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN
Q8-Q0
Q17-Q9
Q17-Q9
BE
IW
L
OW
H
A
1st: Read from Queue
2nd: Read from Queue
L
Q8-Q0
B
(c) x18 INPUT to x9 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
H
B
1st: Read from Queue
H
Q17-Q9
Q8-Q0
A
2nd: Read from Queue
(d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
A
1st: Write to Queue
2nd: Write to Queue
D17-Q9
D8-Q0
B
BYTE ORDER ON OUTPUT PORT:
Q17-Q9
Q8-Q0
BE
IW OW
A
B
Read from Queue
L
H
L
(a) x9 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
H
OW
L
A
B
Read from Queue
H
(a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN
6115 drw08
Figure 4. Bus-Matching Byte Arrangement
28
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
MRS
t
RSS
RSS
WEN
REN
t
tRSR
SENI
tRSS
FSTR,
ESTR
tRSS
WADEN,
RADEN
t
RSS
RSS
RSS
ID0, ID1,
ID2
t
OW, IW
FM
t
HIGH = Looped
LOW = Strobed (Direct)
tRSS
HIGH = Master Device
LOW = Slave Device
MAST
DFM
t
RSS
RSS
HIGH = Default Programming
LOW = Serial Programming
t
HIGH = Offset Value is 128
LOW = Offset value is 8
DF
t
t
t
t
RSF
HIGH-Z if Slave Device
FF
LOGIC “0" if Master Device
RSF
RSF
RSF
LOGIC "1" if Master Device
OV
PAF
PAE
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
HIGH-Z if Slave Device
LOGIC "0" if Master Device
t
RSF
RSF
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PAFn
PAEn
t
HIGH-Z if Slave Device
LOGIC "0" if Master Device
tRSF
LOGIC "1" if OE is LOW and device is Master
Qn
HIGH-Z if OE is HIGH or Device is Slave
6115 drw09
NOTES:
1. OE can toggle during this period.
2. PRS should be HIGH during a MRS.
Figure 5. Master Reset
29
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
w-3
w-2
w-1
w
w+1
w+2
w+3
WCLK
tQH
tQS
WADEN
WEN
tENS
tENS
tAS
tAH
WRADD
Qx
tWFF
FF
tWAF
PAF
tPAF
Active Bus
PAF-Qx(5)
tPRSS
tPRSH
PRS
tPRSH
tPRSS
RCLK
tENS
tENS
REN
tQS
tQH
RADEN
tAS
tAH
RDADD
Qx
tROV
OV
tRAE
PAE
tPAE
Active Bus
PAE-Qx(6)
r-2
r-1
r
r+1
r+2
r+3
r+4
6115 drw10
NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 3 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
Figure 6. Partial Reset
Master Reset
Default Mode
DFM = 0
MRS
MRS
MRS
DFM
DFM
DFM
MQ2
MQn
MQ1
Serial Loading
Complete
SENI
SENO
SO
SENI
SENI
SENO
SO
SENO
SO
Serial Enable
Serial Input
SI
SI
SI
SCLK
SCLK
SCLK
6115 drw11
Serial Clock
Figure 7. Serial Port Connection for Serial Programming
30
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
31
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
32
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
33
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tENH
tENS
WEN
tDS
tDH
tDS
tDH
tDS
tDH
W3
W1
W2
Dn
tSKEW1
1
2
RCLK
REN
Qout
tENS
tA
tA
tA
Last Word Read Out of Queue
W1 Q3
FWFT
W2 Q3
FWFT
W3 Q3
tROV
tROV
OV
6115 drw15
NOTES:
1. Q3 has previously been selected on both the write and read ports.
2. OE is LOW.
3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
Figure 11. Write Operations & First Word Fall Through
34
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
35
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
36
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
*J*
RCLK
REN
tENS
tAS
tAH
tAS
tAH
RDADD
RADEN
D1
Q3
D1 Q2
Addr=00111
QH
Addr=00110
QH
tQS
t
t
tQS
t
A
tA
tA
tA
tOLZ
Qout
D
1
Q
3
WD
Last Word
D1 Q2
PFT We-1
D1
Q
2 We Last Word
W
0
D
Q
2
(Device 1)
1
t
ROV
tROV
tROV
tROV
tOVLZ
HIGH-Z
OV
(Device 1)
tOVHZ
OV
(Device 2)
tSKEW1
WCLK
WEN
tENH
tENS
tAS
tAH
WRADD
D1 Q2
Addr=00110
tQH
tQS
WADEN
Din
tDS
tDH
D
1
W
Q
2
0
6115 drw18
Cycle:
*A* Queue 3 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control
of Qout bus, its Qout outputs are in Low-Impedance. This diagram only shows the Qout outputs of device 1. (Reads are disabled).
*B* Reads are now enabled. A word from the previously selected queue of Device 2 will be read out.
*C* After a queue switch, there is a 3 RCLK latency for output data.
*D* The Qout of Device 1 goes to Low-Impedance and word Wd is read from Q3 of D1. This happens to be the last word of Q3. Device 2 places its Qout outputs into
High-Impedance, device 1 has control of the Qout bus. The OV flag of Device 2 goes to High-Impedance and Device 1 takes control of OV. The OV flag of Device 1 goes LOW
to show that Wd of Q3 is valid.
*E* Queue 2 of device 1 is selected for read operations. The last word of Q3 was read on the previous cycle, therefore OV goes HIGH to indicate that the data on the Qout is
not valid (Q3 was read to empty). Word, Wd remains on the output bus.
*F* The last word of Q3 remains on the Qout bus, OV is HIGH, indicating that this word has been previously read.
*G* The next word (We-1), available from the newly selected queue, Q2 of device 1 is now read out. This will occur regardless of REN, 2 RCLK cycles after queue selection
due to the FWFT operation. The OV flag updates 3 RCLK cycles after a queue selection.
*H* The last word, We is read from Q2, this queue is now empty.
*I* The OV flag goes HIGH to indicate that Q2 was read to empty on the previous cycle.
*J* Due to a write operation the OV flag goes LOW and data word W0 is read from Q2. The latency is: tSKEW1 + 1*RCLK + tROV.
Figure 14. Output Valid Flag Timing (In Expansion Mode)
37
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
38
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
EO
39
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SELECT
NEW QUEUE
*D*
NULL QUEUE
SELECT
*A*
*B*
*C*
*E*
*F*
*G*
RCLK
tAS
tAH
tAS
tAH
Don’t care
00100
RDADD
RADEN
tQS
tQH
tQS
tQH
tAS
tAH
Null-Q
tENS
tENH
REN
tA
tA
t
A
tA
tA
Q3 W0
FWFT
Qout
OV
Q1 Wn-4
Q1 Wn-3
Q1 Wn-2
Q1 Wn-1
Q1 Wn
tROV
tROV
6115 drw21
NOTES:
1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words
from that queue.
2. Please see Figure 18, Null Queue Flow Diagram.
Cycle:
*A* Null Q of device 0 is selected, when word Wn-1 from previously selected Q1 is read.
*C* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.
Note: *B* and *C* are a minimum 3 RCLK cycles between queue selects.
*D* The Null Q is seen as an empty queue on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH. A new queue, Q3 is selected.
*G* 1st word, W0 of Q3 falls through present on the O/P register after 3 RCLK cycles after the queue select.
Figure 17. Read Operation and Null Queue Select
*A*
*B*
*C*
*D*
*E*
*F*
*G*
Null
Queue
Null
Queue
Queue 3
Memory
Queue 3
Memory
Queue 1
Memory
Queue 1
Memory
Null
Queue
Q1
Q1
Q1
Q1
Q1
Q4
Q4
Wn
Wn
Wn
Wn
Wn
W0
W1
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
Qn
Q1
Q1
Q1
Q1
Q1
Q3
Wn-2
Wn-1
Wn
Wn
Wn
Wn
W0
6115 drw22
Figure 18. Null Queue Flow Diagram
40
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
WCLK
WEN
2
1
tENH
tENS
tAS
tAH
tAS
tAH
WRADD
D1
Q2
D1 Q0
Addr=00110
QH
Addr=00100
QH
tQS
t
t
tQS
WADEN
Din
tDS
tDH
WD-m
D1 Q2
tWAF
tWAF
tAFLZ
HIGH-Z
PAF
(Device 1)
tFFHZ
PAF
(Device 2)
6115 drw23
Cycle:
*A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* No write occurs.
*D* Word, Wd-m is written into Q2 causing the PAF flag to go from LOW to HIGH. The flag latency is 3 WCLK cycles + tWAF.
*E* Queue 0 in device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 3 WCLK + tWAF latency.
*F* The PAF flag goes LOW based on the write 2 cycles earlier.
*G* No write occurs.
*H* The PAF flag goes HIGH due to the queue switch to Q0.
Figure 19. Almost Full Flag Timing and Queue Switch
tCLKL
tCLKL
WCLK
WEN
PAF
1
2
1
tENS
tENH
tWAF
tWAF
D-(m+1) words
in Queue
D - (m+1) words in Queue
D - m words in Queue
tSKEW2
RCLK
tENS
tENH
6115 drw24
REN
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
Figure 20. Almost Full Flag Timing
41
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
RCLK
REN
HIGH
AS
t
tAH
tAS
tAH
RDADD
D1
Q3
D1
Q1
Addr=00101
QH
Addr=00111
QH
tQS
t
t
tQS
RADEN
Qout
t
A
tA
t
A
tA
tOLZ
HIGH-Z
HIGH-Z
D1
Q3
Wn
D
1
Q3
Wn+1
D1
Q1
W0
D1 Q1 W1
tRAE
t
RAE
tAELZ
PAE
(Device 1)
tAEHZ
PAE
(Device 2)
HIGH-Z
6115 drw25
Cycle:
*A* Queue 3 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* No read occurs.
*D* The PAE flag output now switches to device 1. Word, Wn is read from Q3 due to the FWFT operation. This read operation from Q3 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*E* Q1 of device 1 is selected.
*F* The PAE flag goes LOW due to the read from Q3 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*G* Word, W0 is read from Q1 due to the FWFT operation.
*H* The PAE flag goes HIGH to show that Q1 is not almost empty.
Figure 21. Almost Empty Flag Timing and Queue Switch
tCLKL
tCLKH
WCLK
tENH
tENS
WEN
PAE
n+1 words in Queue
SKEW2
n+2 words in Queue
n+1 words in Queue
tRAE
t
tRAE
RCLK
1
2
tENS
tENH
6115 drw26
REN
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + tRAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.
Figure 22. Almost Empty Flag Timing
42
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ERN
43
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
1
*C*
2
*D*
3
*E*
*F*
*G*
*H*
WCLK
WADEN
FSTR
tQS
tQH
tQS
tQH
t
QS
tQH
t
STS
tSTH
tENS
tENS
tENH
tENH
WEN
tAS
tAH
tAH
tAS
tAS
tAH
Device 4
D3Q2
011 10
WRADD
Dn
D5Q3
100 11
tDS
tDH
tDS
t
DS
100 xx
t
DH
tDH
Wp
Wp+1
Wp+2
Wn+1
D5Q3
Wn
D5 Q3
Wx
D3 Q2
Writes to Previous Q
t
SKEW3
RCLK
RADEN
ESTR
1
2
3
1
2
3
tQS
tQH
tSTS
t
STH
t
ENS
tENH
REN
tAH
tAS
tAS
tAH
RDADD
Device 5
D5Q3
100 11
101 xx
tA
t
A
tA
tA
t
A
Wy+1
D5 Q3
Wy
D5 Q3
Wy+2
D5 Q3
Wy+3
D5 Q3
Device 5 -Qn
Wa
D5 QP
Wa+1
D5 QP
Previous value loaded on to PAE bus
Prev PAEn
tPAEHZ
tPAE
tPAEZL
xxxx1xxx
Device 5
xxxx1xxx
Device 5
Device 5 PAEn
xxxx1xxx
Device 5
xxxx1xxx
Device 5
Previous value loaded on to PAE bus
D5 QP Status
Bus PAEn
t
RAE
tRAE
tRAE
D5 Q3
status
Device 5 PAE
6115 drw28
*FF*
*AA*
*BB*
*CC*
*DD*
*GG*
*EE*
Cycle:
*A* Q3 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA* Q3 of Device 5 is selected for read operations.
A quadrant from another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
*B* Word Wp+1 is written into the previously selected queue.
*BB* Current Word is kept on the output bus since REN is HIGH.
*C* Word Wp+2 is written into the previously selected queue.
*CC* Word Wa+1 of Device 5 Qp is read due to FWFT.
*D* Word, Wn is written into the newly selected queue, Q3 of Device 5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added).
*DD* Word, Wy from the newly selected queue, Q3 will be read out due to FWFT operation.
Device 5 is selected on the PAEn bus. Q3 of Device 5 will therefore have is PAE status output on PAE[0]. There is a single RCLK cycle latency before the PAEn bus changes
to the new selection.
*E* Q2 of Device 3 is selected for write operations.
Word Wn+1 is written into Q3 of Device 5.
*EE* Word, Wy+1 is read from Q3 of Device 5.
*F* No writes occur.
*FF* Word, Wy+2 is read from Q3 of Device 5.
The PAEn bus changes control to Device 5, the PAEn outputs of Device 5 go to Low-Impedance and quadrant 4 is placed onto the outputs. The device of the previously
selected quadrant now places its PAEn outputs into High-Impedance to prevent bus contention.
The discrete PAE flag will go HIGH to show that Q3 of Device 5 is not almost empty. Q3 of Device 5 will have its PAE status output on PAE[0].
*G* Device 4 is selected on the write port for the PAFn bus.
*GG* The PAEn bus updates to show that Q3 of Device 5 is almost empty based on the reading out of word, Wy+1.
The discrete PAE flag goes LOW to show that Q3 of Device 5 is almost empty based on the reading of Wy+1.
*H* Word, Wx is written into Q2 of Device 3.
Figure 24. PAEn - Direct Mode, Flag Operation
44
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK
tQH
tQS
tQS
tQH
RADEN
tSTH
tSTS
ESTR
REN
tAS
tAH
tAH
tAH
tAS
tAS
Device 7
111 xx
RDADD
D6Q2
110 10
D0Q1
000 01
OE
tA
t
A
tA
tA
tOLZ
Qout
W
X
W
X +1
Prev. Q
W
D0 Q1
D - M + 2
W0
D6 Q2
W
D0 Q1
D-M+1
Prev. Q
t
SKEW3
WCLK
FSTR
1
2
3
tSTS
tSTH
tAS
tAH
tAS
tAH
WRADD
Device 0
000 xx
D0 Q1
tENS
tENH
WEN
tQS
tQH
WADEN
Din
t
DS
t
DH
tDS
t
DH
tDS
tDH
W
y+1
Wy+2
Word W
y
D0 Q1
Device 0
Device 0
HIGH-Z
D0 Q1
D0 Q1
t
PAFLZ
t
PAF
t
PAF
Device 0 PAFn
xxxxxx0x
xxxxxx0x
Device 0
Device 0
Device 0
HIGH-Z
D
X
Quad y
Device 0
Bus PAFn
t
PAFHZ
DX
Quad y
Prev.
PAFn
t
PAFLZ
tWAF
Device 0
HIGH - Z
6115 drw29
PAF
*AA*
*BB*
*CC*
*DD*
*EE*
*FF*
*GG*
Cycle:
*A* Q1 of device 0 is selected for read operations.
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected quadrant, Quad Y of device X.
*B* No read operation.
*BB* Queue 1 of device 0 is selected on the write port.
*C* Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*CC* The PAFn bus is updated with the quadrant selected on the previous cycle, Device 0 PAF[1] is LOW showing the status of queue 1.
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*D* Device 7 is selected for the PAFn bus.
Word, Wd-m+1 is read from Q1 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q1. This read will cause the PAF[1] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*DD* No write operation.
*E* No read operations occur, REN is HIGH.
*EE* PAF[1] goes HIGH to show that D0 Q1 is not almost empty due to the read on cycle *C*.
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q1.
*F* Queue 2 of Device 6 is selected for read operations.
*FF* Word, Wy+1 is written into D0 Q1.
*G* Word, Wd-m+2 is read out due to FWFT operation.
*GG* PAF[1] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q1 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q1.
*H* No read operation.
*I* Word, W0 is read from Q6 of D2, selected on cycle *F*, due to FWFT.
Figure 25. PAFn - Direct Mode, Flag Operation
45
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tFSYNC
tFSYNC
tFSYNC
tFSYNC
FSYNC
0
(MASTER)
tFXO
tFXO
tFXO
tFXO
FXO /
0
FXI
1
tFSYNC
tFSYNC
FSYNC
1
(SLAVE)
tFXO
tFXO
FXO /
1
FXI
2
tFSYNC
tFSYNC
FSYNC
2
(SLAVE)
tFXO
tFXO
FXO /
2
FXI
0
tPAF
tPAF
tPAF
tPAF
tPAF
Device 0
Device 1
Device 2
Device 0
PAF[7:0]
6115 drw30
NOTE:
1. This diagram is based on 3 devices connected to expansion mode.
Figure 26. PAFn Bus - Polled Mode
46
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
RCLK
tESYNC
tESYNC
tESYNC
tESYNC
ESYNC
0
tEXO
tEXO
tEXO
tEXO
EXO /
0
EXI
1
tESYNC
tESYNC
ESYNC
1
tEXO
tEXO
EXO /
1
FXI
2
tESYNC
tESYNC
ESYNC
2
tEXO
tEXO
EXO /
2
EXI
0
tPAE
tPAE
tPAE
tPAE
tPAE
Device 0
Device 1
Device 2
Device 0
PAE
n
6115 drw31
Figure 27. PAEn Bus - Polled Mode
47
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
WEN
tDH
tDS
tDH
tDS
tDS
tDH
tDS
WD10
WD11
WD12
WD13
D[39:0]
1ns
(1)
3
1
2
4
RCLK
REN
(7)
PDHZ
(2)
t
tPDLZ
tA
tA
t
A
tA
Hi-Z
WD1
WD2
WD3
WD4
WDH
WDS
Q[39:0]
(2)
PDH
t
(2)
PDH
t
tPDL
PD
tERCLK
Hi-Z
Hi-Z
ERCLK
tEREN
tEREN
EREN
6115 drw32
NOTES:
1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted.
2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.
All input and output signals will also resume after this time period.
3. Set-up and configuration static inputs are not affected during power down.
4. Serial programming and JTAG programming port are inactive during power down.
5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.
6. All flags remain active and maintain their current states.
7. During power down, all outputs will be in high-impedance.
Figure 28. Power Down Operation
48
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Serial Programming Data Input
Serial Enable
SENI
SI FXI EXI
Output Data Bus
Data Bus
Q
-Q
17
D
-D
17
0
0
Read Clock
Write Clock
RCLK
WCLK
Write Enable
Read Enable
WEN
REN
Read Queue Select
Read Address
Write Queue Select
Write Address
RDADD
RADEN
WRADD
WADEN
DEVICE
1
Empty Strobe
Full Strobe
ESTR
FSTR
PAFn
Programmable Almost Full
Programmable Almost Empty
PAEn
Empty Sync 1
Output Valid Flag
Almost Empty Flag
Full Sync1
ESYNC
OV
FSYNC
Full Flag
FF
Almost Full Flag
Serial Clock
PAF
PAE
SCLK
SENO SO FXO EXO
SENI SI FXI EXI
Q
-Q
17
D
-D
17
0
0
WCLK
RCLK
WEN
REN
WRADD
WADEN
RDADD
RADEN
DEVICE
2
FSTR
PAFn
ESTR
PAEn
Empty Sync 2
Full Sync2
FSYNC
ESYNC
FF
OV
PAF
PAE
SCLK
SO FXO EXO
SENO
SENI SI FXI EXI
Q
-Q
17
D
-D
17
0
0
WCLK
RCLK
REN
WEN
WRADD
WADEN
RDADD
RADEN
DEVICE
n
FSTR
PAFn
FSYNC
ESTR
PAEn
Full Sync n
Empty Sync n
ESYNC
FF
OV
PAF
PAE
SCLK
SENO
FXO EXO
DONE
6115 drw33
NOTES:
1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO
outputs are DNC (Do Not Connect).
2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
Figure 29. Multi-Queue Expansion Diagram
49
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T51233/72T51243/
72T51253incorporates thenecessarytapcontrollerandmodifiedpadcellsto
implementtheJTAG facility.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
The Figure belowshows the standardBoundary-ScanArchitecture
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
6115 drw34
Figure 30. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
50
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-IR
Shift-DR
1
1
1
1
Input = TMS
Exit1-IR
Exit1-DR
0
0
0
0
Pause-IR
Pause-DR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-IR
Update-DR
1
0
1
0
6115 drw35
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal Queue operations can begin.
Figure 31. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram.
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overthe Queue andmustbe resetafterpowerupofthe device. See TRST
descriptionformoredetailsonTAPcontrollerreset.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCKfive
times. This is the reasonwhythe TestReset(TRST)pinis optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
51
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
JTAG INSTRUCTION REGISTER
THE INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
•
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions. Instructionsaredecodedasfollows.
TESTDATAREGISTER
Hex
Value
00
01
02
04
0F
Instruction
Function
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
SAMPLE/PRELOAD
IDCODE
HIGH-IMPEDANCE
BYPASS
SelectBoundaryScanRegister
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
JTAG
SelectBypassRegister
JTAG INSTRUCTION REGISTER DECODING
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO.Duringthisinstruction,theboundary-scanregisterisaccessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
THE DEVICE IDENTIFICATION REGISTER
IDCODE
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDI and TDO. The device identification register is a 32-bit shift register
containinginformationregardingtheICmanufacturer,devicetype,andversion
code.Accessingthedeviceidentificationregisterdoesnotinterferewiththe
operationoftheIC.Also,accesstothedeviceidentificationregistershouldbe
immediatelyavailable,viaaTAPdata-scanoperation,afterpower-upofthe
ICoraftertheTAPhasbeenresetusingtheoptionalTRSTpinorbyotherwise
movingtotheTest-Logic-Resetstate.
FortheIDT72T51233/72T51243/72T51253,thePartNumberfieldcon-
tainsthefollowingvalues:
Device
Part# Field (HEX)
0x451
IDT72T51233
IDT72T51243
IDT72T51253
0x452
0x453
SAMPLE/PRELOAD
TherequiredSAMPLE/PRELOADinstructionallowstheICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.This instructionis alsousedtopreloadtestdata
intotheboundary-scanregisterbeforeloadinganEXTESTinstruction.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG DEVICE IDENTIFICATION REGISTER
52
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
HIGH-IMPEDANCE
BYPASS
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand
selects the one-bit bypass register to be connected between TDI and TDO.
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI
toTDOwithoutaffectingtheconditionoftheICoutputs.
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
theIC.
53
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
6115 drw36
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 32. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
Min. Max. Units
SYSTEMINTERFACEPARAMETERS
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
IDT72T51233
IDT72T51243
IDT72T51253
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
54
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Plastic Ball Grid Array (PBGA, BB256-1)
BB
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
5
6
Commercial Only
Commercial and Industrial
Low Power
L
72T51233 589,824 bits 2.5V Multi-Queue Flow-Control Device
72T51243 1,179,648 bits 2.5V Multi-Queue Flow-Control Device
72T51253 2,359,296 bits 2.5V Multi-Queue Flow-Control Device
6115 drw36
NOTE:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
DATASHEETDOCUMENTHISTORY
08/05/2003
11/06/2003
pgs. 1 through 55.
pgs. 1, 4, 15 and 16.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1533
email:Flow-Controlhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
55
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