IDT74ALVC16841PV8 [IDT]
Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56;
| 型号： | IDT74ALVC16841PV8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 20-BIT
BUS-INTERFACE
IDT74ALVC16841
D-TYPE LATCH WITH
3-STATE OUTPUTS
DESCRIPTION:
FEATURES:
This20-bitbus-interfaceD-typelatchisbuiltusingadvanceddualmetalCMOS
technology.TheALVC16841features3-stateoutputsdesignedspecificallyfor
drivinghighlycapacitiverelativelylow-impedanceloads.Thisdeviceisparticu-
larlysuitableforimplementingbufferregisters,unidirectional busdrivers,and
workingregisters.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
TheALVC16841canbeusedastwo10-bitlatchesorone20-bitlatch.The
20latchesaretransparentD-typelatches.Thedevicehasnoninvertingdata(D)
inputsandprovidestruedataatitsoutputs.Whilethelatch-enable(1LEor2LE)
inputishigh,theQoutputsofthecorresponding10-bitlatchfollowtheDinputs.
WhenLEistakenlow,theQoutputsarelatchedatthelevelssetupattheDinputs.
Abufferedoutput-enable(1OEor2OE)inputcanbeusedtoplacetheoutputs
ofthecorresponding10-bitlatchineitheranormallogicstate(highorlowlogic
levels) or a high-impedance state. In the high-impedance state, the outputs
neitherloadnordrivethebuslinessignificantly.OEdoesnotaffecttheinternal
operationofthelatches.Olddatacanberetainedornewdatacanbeentered
whiletheoutputsareinthehigh-impedancestate.
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
TheALVC16841hasbeendesignedwitha±24mAoutputdriver.Thisdriver
is capable of driving a moderate to heavy load while maintaining speed
performance.
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
28
1
2OE
1OE
56
29
1LE
2LE
55
42
1D1
2D1
1D
1D
15
2
2Q1
1Q1
Q
Q
C1
C1
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4746/2
IDT74ALVC16841
3.3VCMOS20-BITBUSINTERFACED-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
1
56
55
54
53
52
51
50
1OE
1LE
1D1
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1Q1
1Q2
2
3
4
5
6
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
1D2
GND
1D3
1D4
Continuous Clamp Current,
VI < 0 or VI > VCC
GND
1Q3
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
1Q4
ICC
ISS
Continuous Current through each
VCC or GND
±100
7
8
9
VCC
1Q5
VCC
1D5
NOTES:
49
48
47
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1Q6
1Q7
1D6
1D7
10
11
12
GND
1Q8
GND
1D8
46
45
44
2. VCC terminals.
3. All terminals except VCC.
1Q9
1Q10
2Q1
13
14
15
16
17
18
1D9
1D10
2D1
43
42
2Q2
2D2
41
40
39
38
37
36
35
34
33
CAPACITANCE (TA = +25°C, F = 1.0MHz)
2Q3
2D3
GND
2D4
2D5
2D6
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
GND
2Q4
2Q5
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
19
20
21
22
23
24
COUT
COUT
2Q6
VCC
2Q7
2Q8
NOTE:
1. As applicable to the device type.
VCC
2D7
2D8
GND
2Q9
25
26
27
28
32
31
30
29
GND
2D9
(1)
FUNCTION TABLE (EACH 10-BIT LATCH)
2Q10
2OE
2D10
Inputs
xLE
H
Outputs
xDx
H
xOE
xQx
H
2LE
L
L
L
H
L
SSOP/ TSSOP/ TVSOP
TOP VIEW
(2)
X
X
L
L
Q0
X
H
Z
NOTES:
PINDESCRIPTION
Pin Names
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Description
Z = High Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
xDx
LE
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Outputs
xOE
xQx
2
IDT74ALVC16841
INDUSTRIALTEMPERATURERANGE
3.3VCMOS20-BITBUSINTERFACED-TYPELATCHWITH3-STATEOUTPUTS
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
±5
±5
µA
µA
µA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
±10
±10
–1.2
—
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
2
1.7
2.2
2.4
2
—
—
—
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74ALVC16841
3.3VCMOS20-BITBUSINTERFACED-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
Typical
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
12
1
20
3
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
—
Max.
Min.
Max.
Unit
PropagationDelay
xDx to xQx
1
5
4.7
1.2
3.9
ns
ns
ns
ns
tPHL
tPLH
PropagationDelay
LE to xQx
1
1
5.6
6.2
5.3
—
—
—
5.1
6
1
1
4.3
4.9
4.1
tPHL
tPZH
tPZL
OutputEnableTime
xOE to xQx
tPHZ
tPLZ
OutputDisableTime
xOE to xQx
1.1
4.3
1.3
tSU
Set-upTime,databeforeLE↑
HoldTime,dataafterLE↑
Pulse Duration, LE HIGH or LOW
OutputSkew(2)
0.9
1.2
3.3
—
—
—
—
—
0.7
1.5
3.3
—
—
—
—
—
1.1
1.1
3.3
—
—
—
ns
ns
ns
ps
tH
tW
—
tSK(O)
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVC16841
INDUSTRIALTEMPERATURERANGE
3.3VCMOS20-BITBUSINTERFACED-TYPELATCHWITH3-STATEOUTPUTS
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
SAME PHASE
INPUT TRANSITION
0V
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
VOH
VT
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
VOL
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VT
Vcc / 2
150
V
VLZ
VHZ
CL
mV
mV
pF
ALVC Link
150
30
Propagation Delay
VLOAD
VCC
Open
DISABLE
tPLZ
ENABLE
VIH
VT
500Ω
500Ω
GND
CONTROL
INPUT
VIN
VOUT
Pulse(1, 2)
Generator
0V
D.U.T.
tPZL
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
RT
VOL + VLZ
VOL
CL
tPHZ
tPZH
OUTPUT
NORMALLY
HIGH
ALVC Link
VOH
VOH - VHZ
SWITCH
OPEN
VT
0V
Test Circuit for All Outputs
0V
DEFINITIONS:
ALVC Link
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
VT
0V
DATA
INPUT
tSU
tH
SWITCHPOSITION
VIH
VT
0V
TIMING
INPUT
Test
Switch
VLOAD
GND
Open Drain
Disable Low
Enable Low
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
VIH
VT
0V
Disable High
Enable High
SYNCHRONOUS
CONTROL
tSU
tH
All Other Tests
Open
ALVC Link
Set-up, Hold, and Release Times
VIH
VT
0V
INPUT
tPLH1
tPHL1
LOW-HIGH-LOW
VOH
VT
VT
PULSE
OUTPUT 1
OUTPUT 2
VOL
tW
tSK (x)
tSK (x)
VOH
HIGH-LOW-HIGH
PULSE
VT
VT
ALVC Link
VOL
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVC16841
3.3VCMOS20-BITBUSINTERFACED-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
XXX
IDT
ALVC
XXX
XX
XX
Bus-Hold
Family Device Type Package
Temp. Range
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
20-Bit Bus-Interface D-Type Latch with 3-State Outputs
841
16
Double-Density, ±24mA
Blank No Bus-Hold
74
–40°C to +85°C
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www.idt.com
6
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