IDT74ALVCH16601PAG [IDT]
Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56;型号: | IDT74ALVCH16601PAG |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56 光电二极管 输出元件 逻辑集成电路 |
文件: | 总7页 (文件大小:73K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT74ALVCH16601
3.3V CMOS 18-BIT UNIVERSAL
BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
This 18-bit universal bus transceiver is built using advanced dual metal
CMOStechnology. TheALVCH16601combinesD-typelatchesandD-type
flip-flopstoallowdataflowintransparent,latched,andclockedmodes.
Dataflowineachdirectioniscontrolledbyoutput-enable(OEABandOEBA),
latch-enable(LEABandLEBA),andclock(CLKABandCLKBA)inputs. The
clockcanbecontrolledbytheclock-enable(CLKENABandCLKENBA)inputs.
ForA-to-Bdataflow,thedeviceoperatesinthetransparentmodewhenLEAB
is high. When LEAB is low, the A data is latched if CLKAB is held at a high or
lowlogiclevel. IfLEABislow,thedataisstoredinthelatch/flip-floponthelow-
to-hightransitionofCLKAB.OutputenableOEABisactivelow.WhenOEABis
low, the outputs are active. When OEAB is high, the outputs are in the high-
impedancestate.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
DataflowforBtoAissimilartothatofAtoBbutusesOEBA,LEBA,CLKBA
and CLKENBA.
The ALVCH16601 has been designed with a ±24mA output driver. This
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed
performance.
The ALVCH16601 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand
eliminatestheneedforpull-up/downresistors.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
1
OEAB
56
CLKENAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
29
CLKENBA
27
OEBA
CE
3
54
1D
C1
A1
B1
CLK
CE
1D
C1
CLK
TO 17 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC-4732/2
IDT74ALVCH16601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1
2
3
4
5
6
7
8
9
OEAB
LEAB
A1
CLKENAB
56
55
54
53
52
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
CLKAB
B1
Continuous Clamp Current,
VI < 0 or VI > VCC
GND
A2
GND
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
B2
B3
ICC
ISS
Continuous Current through each
VCC or GND
±100
A3
51
50
VCC
NOTES:
VCC
B4
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
A4
A5
49
48
B5
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
47
46
45
44
43
B6
2. VCC terminals.
3. All terminals except VCC.
GND
A7
GND
B7
A8
B8
A9
B9
B10
B11
B12
A10
A11
A12
42
41
40
39
38
37
36
35
34
33
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
COUT
CI/O
GND
A13
GND
B13
B14
B15
NOTE:
A14
1. As applicable to the device type.
A15
VCC
A16
A17
VCC
B16
B17
GND
A18
32
31
30
29
GND
B18
PINDESCRIPTION
26
27
28
Pin Names
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Description
CLKBA
OEBA
LEBA
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
CLKENBA
B-to-A Latch Enable Input
SSOP/ TSSOP
TOP VIEW
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
Bx
CLKENAB A-to-B Clock Enable Input (Active LOW)
CLKENBA B-to-A Clock Enable Input (Active LOW)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74ALVCH16601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
FUNCTIONTABLE(1,2)
Inputs
Output
Bx
Z
CLKENAB
OEAB
LEAB
CLKAB
Ax
X
L
X
X
X
H
H
L
H
L
L
L
L
L
L
L
X
H
H
L
X
X
L
X
X
H
X
X
L
H
B(3)
B(3)
L
L
X
L
↑
L
L
↑
H
X
H
B(3)
L
L
L or H
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and
CLKBA, and CLKENBA.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH transition
3. Level of B before the indicated steady-state inputs were established.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
±5
±5
µA
µA
µA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
±10
±10
–1.2
—
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH16601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
µA
µA
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
2
1.7
2.2
2.4
2
—
VCC = 2.3V
—
VCC = 2.7V
—
VCC = 3V
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
Typical
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
41
6
52
6
pF
CPD
4
IDT74ALVCH16601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
Min.
150
1
Max.
—
Min.
150
—
Max.
—
Min.
150
—
Max.
—
Unit
MHz
ns
PropagationDelay
4
4.6
4.1
Ax to Bx or Bx to Ax
PropagationDelay
1
4.6
5.2
5.3
4.9
—
—
—
—
5.3
5.8
6.1
4.8
—
—
—
—
4.7
5
ns
ns
ns
ns
LEAB to Bx or LEBA to Ax
PropagationDelay
1.2
1.1
1.4
CLKAB to Bx or CLKBA to Ax
OutputEnableTime
5.2
4.4
OEAB to Bx or OEBA to Ax
OutputDisableTime
OEAB to Bx or OEBA to Ax
Set-upTime,databeforeCLK↑
Set-up Time, data before LE↓, CLK HIGH
Set-up Time, data before LE↓, CLKLOW
Set-upTime, CLKEN beforeCLK↑
HoldTime,dataafterCLK↑
Hold Time, data after LE↓, CLK HIGH
Hold Time, data after LE↓, CLK LOW
Hold Time, CLKEN after CLK↑
Pulse Width, LE HIGH
2.3
2
—
—
—
—
—
—
—
—
—
—
—
2.4
1.6
1.2
2
—
—
—
—
—
—
—
—
—
—
—
2.1
1.6
1.1
1.7
0.8
1.4
1.7
0.6
3.3
3.3
—
—
—
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
tSU
tSU
1.3
2
tSU
tH
0.7
1.3
1.7
0.3
3.3
3.3
—
0.7
1.6
2
tH
tH
tH
0.5
3.3
3.3
—
tW
tW
Pulse Width, CLK HIGH or LOW
OutputSkew(2)
tSK(o)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2
Skew between any two outputs of the same package and switching in the same direction.
5
IDT74ALVCH16601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
TESTCONDITIONS
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VIH
VT
0V
VT
Vcc / 2
150
V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
Generator
VT
VLZ
VOL
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
VIH
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
DATA
INPUT
VT
0V
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
tSU
tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
SWITCHPOSITION
Test
Switch
VLOAD
GND
tREM
ASYNCHRONOUS
CONTROL
Open Drain
Disable Low
Enable Low
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
ALVC Link
All Other Tests
Open
VIH
Set-up, Hold, and Release Times
VT
INPUT
0V
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
OUTPUT 2
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74ALVCH16601
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
XX
XX
Device Type Package
IDT
ALVC
XXX
XX
Temp. Range
Bus-Hold
Family
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
601 18-Bit Universal Bus Transceiver with 3-State Outputs
16
Double-Density, ±24mA
H
Bus-Hold
-40°C to +85°C
74
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7
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