IDT74FCT162H272ETPF [IDT]
FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER; FAST CMOS 12位同步总线交换器
| 型号： | IDT74FCT162H272ETPF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER |
| 文件： | 总8页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT162H272AT/CT/ET
FAST CMOS
12-BIT SYNCHRONOUS
BUS EXCHANGER
Integrated Device Technology, Inc.
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤ 1µA (max.)
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packagesinclude25milpitchSSOP, 19.6milpitchTSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
• Extended commercial range of -40°C to +85°C
multiplexers for use in synchronous memory interleaving
applications. All registers have a common clock and use a
clock enable (CExxx) on each data register to control data
sequencing. The output enables and mux select (OEA, OEB
and SEL) are also under synchronous control allowing direc-
tion changes to be edge triggered events.
Thetri-portbusexchangerhasthree12-bitports. Datamay
be transferred between the A port and either/both of the B
ports. The clock enable (CE1B, CE2B, CEA1B and CEA2B)
inputs control the data storage. Both B ports have a common
output enable (OEB) to aid in synchronously loading the B
registers from the B port.
• Balanced Output Drivers:
±24mA (commercial)
±16mA (military)
• Reduced system switching noise
The FCT162H272AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times-reducing
the need for external series terminating resistors.
• Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V, TA = 25°C
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull up resistors
The FCT162H272AT/CT/ET have "Bus Hold" which re-
tains the input's last state whenever the input goes to high
impedance. This prevents "floating" inputs and eliminates the
need for pull-up/down resistors.
DESCRIPTION:
The FCT162H272AT/CT/ET synchronous tri-port bus ex-
changers are high-speed, bidirectional,12-bit, registered, bus
FUNCTIONAL BLOCK DIAGRAM
CEA1B
CLK
CE
A-1B
REGISTER
1B1:12
Q
12
D
CE
CE1B
1B-A
REGISTER
12
D
12
SEL
Q
CONTROL
REGISTER
12
OEB
OEA
1
0
M
U
X
A1:12
12
CE
CE2B
2B-A
REGISTER
12
D
Q
12
12
CEA2B
CE
A-2B
REGISTER
2B1:12
Q
12
D
3071 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
5.5
DSC-3071/3
1
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN CONFIGURATIONS
CEA1B
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CE1B
CEA1B
CEA2B
2B3
GND
2B2
2B1
VCC
A1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CE1B
CE2B
2B4
2
CEA2B
2B3
GND
2B2
2B1
VCC
A1
2
CE2B
2B4
3
3
4
GND
2B5
4
GND
2B5
5
5
6
2B6
6
2B6
7
VCC
2B7
7
VCC
2B7
8
8
A2
9
2B8
A2
9
2B8
A3
10
11
12
13
2B9
A3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2B9
GND
A4
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
GND
A4
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
A5
A5
A6
14 SO56-1
SO56-2
15 SO56-3
A6
E56-1
A7
A7
A8
16
17
18
19
20
21
22
23
24
25
26
A8
A9
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
1B8
1B8
1B7
1B7
VCC
1B6
VCC
1B6
1B5
1B5
GND
1B3
GND
1B4
GND
1B4
27
28
OEA
SEL
OEB
CLK
OEA
SEL
OEB
CLK
3071 drw 03
3071 drw 02
SSOP/
TSSOP/TVSOP
TOP VIEW
CERPACK
TOP VIEW
5.5
2
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN DESCRIPTION
Signal
A(1:12)
1B(1:12)
2B(1:12)
CLK
I/O
I/O
I/O
I/O
I
Description
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.(1)
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.(1)
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.(1)
Clock Input.
CEA1B
I
Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked
into register A-1B (Active LOW).
CEA2B
CE1B
CE2B
SEL
I
I
I
I
Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked
into register A-2B (Active LOW).
Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into
register 1B-A (Active LOW).
Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into
register 2B-A (Active LOW).
1B or 2B Path Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to
A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port.
OEA
OEB
I
I
Synchronous Output Enable for A Port (Active LOW).
Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
3071 tbl 01
NOTES:
1. On FCT162H272T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.
FUNCTION TABLES(2)
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Max.
Unit
Inputs
SEL
Output
A
(2) Terminal Voltage with Respect to
V
TERM
TERM
–0.5 to +7.0
V
1B
H
L
2B
X
CLK
CE1B CE2B OEA
GND
H
H
H
L
L
L
X
X
X
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
H
(3) Terminal Voltage with Respect to
GND
V
–0.5 to
CC +0.5
V
X
L
V
X
X
H
X
X
X
X
A(1)
H
TSTG
Storage Temperature
DC Output Current
–65 to +150
°C
X
H
L
I
OUT
–60 to +120 mA
3071 tbl 02
NOTES:
X
L
L
L
A(1)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
X
X
L
H
X
X
X
X
Z
3071 tbl 04
Inputs
CEA1B CEA2B
Outputs
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
A
CLK
1B
H
2B
H
OEB
L
H
L
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
CAPACITANCE (TA = +25°C, F = 1.0MHZ)
L
L
L
L
L
L
Parameter(1)
Conditions
Typ. Max. Unit
H
L
H
H
L
L
H
B(1)
B(1)
H
Symbol
CIN
Input
VIN = 0V
3.5
3.5
6.0
pF
L
L
L
L
Capacitance
I/O
H
H
H
H
X
X
L
B(1)
B(1)
B(1)
Z
CI/O
VOUT = 0V
8.0
pF
L
L
L
L
B(1)
Capacitance
X
H
X
X
L
3071 tbl 03
NOTE:
1. This parameter is measured at characterization but not tested.
X
X
H
L
Z
Active
Active
3071 tbl 05
NOTES:
1. Output level before the indicated steady-state input conditions were
established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
5.5
3
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Input LOW Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
VIL
Guaranteed Logic LOW Level
0.8
V
I
I
I H
Input
Standard Input(5)
V
CC = Max.
V
I
I
= VCC
—
±
1
1
µA
HIGH
Current(4)
Standard I/O(5)
Bus-Hold Input
Bus-Hold I/O
—
±
—
±
100
100
—
±
I L
Input
LOW
Standard Input(5)
Standard I/O(5)
V
= GND
—
±
1
1
—
±
Current(4) Bus-Hold Input
—
±
100
100
—
Bus-Hold I/O
—
±
I
I
BHH
BHL
Bus Hold
Bus-Hold Input
VCC = Min.
V
I
I
= 2.0V
= 0.8V
–50
+50
µ
A
A
Sustain
Current(4)
V
—
I
I
OZH
OZL
High Impedance Output Current
(3-State Output pins)(5,6)
Clamp Diode Voltage
VCC = Max.
V
O
O
= 2.7V
= 0.5V
—
—
—
—
±
1
1
µ
V
±
VIK
V
CC = Min., IIN = –18mA
—
–0.7
–1.2
V
I
OS
Short Circuit Current
V
CC = Max., V
O
= GND(3)
–80
—
–
140
100
5
–
225
mA
mV
V
H
Input Hysteresis
—
—
I
I
I
CCL
CCH
CCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
—
500
µA
3071 tbl 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162H272T
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
I
I
ODL
Output LOW Current
V
CC = 5V, VIN = VIH or VIL,
CC = 5V, VIN = VIH or VIL,
V
OUT = 1.5V(3)
60
–60
2.4
115
200
mA
ODH
Output HIGH Current
Output HIGH Voltage
V
V
OUT = 1.5V(3)
–115 –200
mA
V
V
OH
OL
V
V
V
V
CC = Min.
IN = VIH or VIL
CC = Min.
I
OH = –16mA MIL.
OH = –24mA COM'L.
OL = 16mA MIL.
3.3
0.3
—
I
I
I
V
Output LOW Voltage
—
0.55
V
IN = VIH or VIL
OL = 24mA COM'L.
3071 lnk 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
6. Does not include Bus Hold I/O pins.
5.5
4
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆ICC
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
Quiescent Power Supply Current VCC = Max.
TTL Inputs HIGH
—
0.5
1.5
mA
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current(4) VCC = Max.
VIN = VCC
—
60
100
µA/
Outputs Open
VIN = GND
MHz
One Output Port Enabled
CExx = GND
One Input Bit Toggling
One Output Bit Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
VIN = VCC
VIN = GND
—
0.6
0.9
1.5
2.3
mA
Outputs Open
fi = 10MHz
50% Duty Cycle
One Output Port Enabled
CExx = GND
VIN = 3.4V
VIN = GND
—
One Input Bit Toggling
One Output Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
VIN = VCC
VIN = GND
—
—
1.8
4.8
3.5(5)
50% Duty Cycle
One Output Port Enabled
CExx = GND
VIN = 3.4V
VIN = GND
12.5(5)
Twelve Input Bits Toggling
Twelve Output Bits Toggling
3071 tbl 09
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.5
5
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162H272AT
FCT162H272CT
FCT162H272ET
Com'l.
(2)
Mil.
(2)
Com'l.
(2)
Mil.
(2)
Com'l.
(2)
Mil.
(2)
(1)
Condition
Symbol
Parameter
Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max. Unit
tPLH
tPHL
Propagation Delay
CLK to 1Bx or CLK to 2Bx
Propagation SEL Stable
CL = 50pF 1.5 5.8 1.5 6.2 1.5 5.2 1.5 5.6 1.5 4.8
RL = 500Ω
—
—
—
—
—
—
ns
ns
ns
ns
ns
tPLH
tPHL
1.5 6.0 1.5 6.4 1.5 5.4 1.5 5.8 1.5 5.0
—
—
—
—
Delay
CExB Enabled
SEL Changing
CExB Disabled
SEL Changing
CExB Enabled
CLK to Ax
1.5 6.0 1.5 6.4 1.5 5.4 1.5 5.8 1.5 5.4
1.5 7.6 1.5 7.9 1.5 6.6 1.5 7.0 1.5 5.6
1.5 7.7 1.5 8.1 1.5 6.8 1.5 7.2 1.5 6.0
tPZH
tPZL
Output Enable Time
CLK to Ax, CLK to 1Bx, or
CLK to 2Bx
tPHZ
tPLZ
Output Disable Time
CLK to Ax, CLK to 1Bx, or
CLK to 2Bx
1.5 6.4 1.5 6.8 1.5 6.0 1.5 6.4 1.5 5.6
—
—
ns
tSU
tSU
Set-Up Time, HIGH or LOW
Data to CLK
2.0
2.0
—
—
2.0
2.0
—
—
2.0
2.0
—
—
2.0
2.0
—
—
2.0
2.0
—
—
—
—
—
—
ns
ns
Set-Up Time, OEA to CLK,
OEB to CLK
tSU
tSU
Set-Up Time, SEL to CLK
Set-Up Time, CEA1B to CLK,
2.0
2.0
—
—
2.0
2.0
—
—
2.0
2.0
—
—
2.0
2.0
—
—
2.0
2.0
—
—
—
—
—
—
ns
ns
CE1B to CLK, CE2B to CLK,
or CEA2B to CLK
tH
tH
Hold Time, CLK to Data
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
—
—
—
—
ns
ns
Hold Time, CLK to OEA,
CLK to OEB, CLK to SEL
Hold Time, CLK to CEA1B,
CLK to CE1B, CLK to CE2B,
CLK to CEA2B
0.5
0.5
0.5
0.5
0.5
tH
0
—
0
—
0
—
0
—
0
—
—
—
ns
tW
Pulse Width, CLK HIGH(4)
3.0
—
—
3.0
—
—
3.0
—
—
3.0
—
—
3.0
—
—
—
—
—
—
ns
ns
tSK(o) Output Skew(3)
0.5
0.5
0.5
0.5
0.5
3071 tbl 10
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
5.5
6
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
VCC
7.0V
Enable Low
Open
500Ω
All Other Tests
3032 tbl 11
DEFINITIONS:
V OUT
VIN
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
Pulse
Generator
D.U.T.
50pF
C L
500Ω
R T
3071 lnk 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
INPUT
1.5V
0V
LOW-HIGH-LOW
tSU
t H
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
t W
ASYNCHRONOUS CONTROL
t REM
HIGH-LOW-HIGH
PULSE
1.5V
PRESET
CLEAR
ETC.
3V
1.5V
0V
SYNCHRONOUS CONTROL
3071 lnk 06
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
t
H
t
SU
3071 lnk 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
SAME PHASE
1.5V
0V
INPUT TRANSITION
CONTROL
INPUT
1.5V
0V
tPHL
tPLH
tPZL
tPLZ
VOH
1.5V
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
OUTPUT
SWITCH
CLOSED
VOL
0.3V
0.3V
tPLH
tPHL
tPZH
tPHZ
3V
OPPOSITE PHASE
INPUT TRANSITION
VOH
1.5V
0V
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
3071 lnk 07
3071 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.5
7
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
ORDERING INFORMATION
IDT
Temp. Range
XX
FCT
X
X
XXXX
X
X
Drive Bus Hold Device Type
Package
Process
Commercial
MIL-STD-883, Class B
Blank
B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
PV
PA
PF
E
12-Bit Synchronous Tri-Port Bus Exchanger
272AT
272CT
272ET
H
Bus Hold
162
16-Bit Balanced Drive
-55°C to +125°C
-40°C to +85°C
54
74
3071 drw 09
5.5
8
相关型号：
IDT74FCT162H272ETPFG
Bus Exchanger, FCT Series, 1-Func, 12-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56
IDT
IDT74FCT162H501ATEG
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56
IDT
IDT74FCT162H501ATPA8
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56
IDT
IDT74FCT162H501ATPAG
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56
IDT
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