IDT74FCT162H501ATEG [IDT]

Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56;


型号：	IDT74FCT162H501ATEG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56 CD
文件：	总7页 (文件大小：124K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT54/74FCT162H501AT/CT/ET

FASTCMOS18-BITREGISTEREDTRANSCEIVER

MILITARYANDCOMMERCIALTEMPERATURERANGES

FAST CMOS

IDT54/74FCT162H501AT/CT/ET

18-BIT REGISTERED

TRANSCEIVER

DESCRIPTION:

FEATURES:

−

0.5 MICRON CMOS Technology

High-speed, low-power CMOS replacement for ABT functions

Typical tSK(o) (Output Skew) < 250ps

Low input and output leakage ≤ 1µA (max.)

ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP

and 25 mil pitch CERPACK packages

The FCT162H501AT/CT/ET 18-bit registered transceivers are built

using advanced dual metal CMOS technology. These high-speed, low-

power18-bitregisteredbus transceivers combine D-type latches andD-

typeflip-flopstoallowdataflowintransparent,latchedandclockedmodes.

Data flow in each direction is controlled by output-enable (OEAB and

OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA)

inputs.ForA-to-Bdataflow,thedeviceoperatesintransparentmodewhen

LEABis high.WhenLEABis low,the Adata is latchedifCLKABis heldat

ahighorlowlogiclevel. IfLEABis low,theAbus datais storedinthelatch/

flip-floponthelow-to-hightransitionofCLKAB.OEABis theoutputenable

forthe Bport.Data flowfromthe Bporttothe Aportis similarbutrequires

using OEBA,LEBAandCLKBA.Flow-throughorganizationofsignalpins

simplifieslayout.Allinputsaredesignedwithhysteresisforimprovednoise

margin.

−

Extended commercial range of -40°C to +85°C

Bus Hold retains last active bus state during 3-state

Eliminates the need for external pull up resistors

The FCT162H501AT/CT/EThas "Bus Hold"whichretains the input's

last state whenever the input goes to high impedance. This prevents

"floating"inputs andeliminates the needforpull-up/downresistors.

FUNCTIONALBLOCKDIAGRAM

OEAB

CLKBA

LEBA

OEBA

CLKAB

LEAB

TO 17 OTHER CHANNELS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AUGUST 1999

1999 Integrated Device Technology, Inc.

DSC-5434/-

IDT54/74FCT162H501AT/CT/ET

FASTCMOS18-BITREGISTEREDTRANSCEIVER

MILITARYANDCOMMERCIALTEMPERATURERANGES

PINCONFIGURATION

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

OEAB

LEAB

GND

CLKAB

Symbol

Description

Max

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +7

(3)

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

TSTG

IOUT

Storage Temperature

DC Output Current

–65 to +150

–60 to +120

°C

GND

5v16-link

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

VCC

2. All device terminals except FCT162XXXT Output and I/O terminals.

3. Output and I/O terminals for FCT162XXXT.

GND

CAPACITANCE

Symbol

(TA = +25 C, f = 1.0MHz)

SO56-1

SO56-2

SO56-3

E56-1

Parameter⁽¹⁾

Conditions

Typ.

Max. Unit

A10

A11

A12

GND

A13

A14

A15

VCC

A16

A17

GND

A18

B10

B11

B12

GND

B13

B14

B15

VCC

B16

B17

GND

B18

CLKBA

GND

CIN

Input Capacitance

VIN = 0V

3.5

COUT

Output Capacitance

VOUT = 0V

3.5

5v16-link

NOTE:

1. This parameter is measured at characterization but not tested.

FUNCTIONTABLE^(1,4)

Inputs

Outputs

OEAB

LEAB

CLKAB

↑

OEBA

LEBA

SSOP/ TSSOP/ TVSOP/ CERPACK

TOP VIEW

↑

(2)

(3)

PINDESCRIPTION

NOTES:

Pin Names

OEAB

OEBA

LEAB

LEBA

CLKAB

CLKBA

Description

1. A-to-Bdataflowisshown.B-to-AdataflowissimilarbutusesOEBA, LEBA,

and CLKBA.

A-to-BOutputEnableInput

2. Output level before the indicated steady-state input conditions were

established.

3. Output level before the indicated steady-state input conditions were

established, provided that CLKAB was HIGH before LEAB went LOW.

4. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don't Care

Z = High-Impedance

↑ = LOW-to-HIGH Transition

B-to-AOutputEnableInput(ActiveLOW)

A-to-BLatchEnableInput

B-to-ALatchEnableInput

A-to-B Clock Input

B-to-A Clock Input

A-to-BDataInputsorB-to-A3-StateOutputs⁽¹⁾

B-to-ADataInputsorA-to-B3-StateOutputs⁽¹⁾

NOTE:

1. These pins have “Bus Hold”. All other pins are standard inputs, outputs

or I/Os.

IDT54/74FCT162H501AT/CT/ET

FASTCMOS18-BITREGISTEREDTRANSCEIVER

MILITARYANDCOMMERCIALTEMPERATURERANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Commercial: TA = -40°C to +85°C, VCC = 5.0V ±10%; Military: TA = -55°C to +125°C, VCC = 5.0V ±10%

Symbol

Parameter

Input HIGH Level

Test Conditions⁽¹⁾

Guaranteed Logic HIGH Level

Min.

Typ.⁽²⁾Max.

Unit

VIH

—

0.8

VIL

IIH

Input LOW Level

Input HIGH

Guaranteed Logic LOW Level

VCC = Max.

—

–50

+50

—

–80

—

Standard Input⁽⁵⁾

VI = VCC

—

±1

µA

Current⁽⁴⁾

Standard I/O

—

±1

(5)

Bus-hold Input

—

±100

±1

Bus-hold I/O

—

IIL

Input LOW

Current⁽⁴⁾

Standard Input⁽⁵⁾

VI = GND

—

(5)

Standard I/O

—

±1

Bus-hold Input

Bus-hold I/O

—

±100

—

IBHH

IBHL

IOZH

IOZL

VIK

Bus Hold

Bus-hold Input

VCC = Min.

VI = 2.0V

VI = 0.8V

VO = 2.7V

VO = 0.5V

—

µA

Sustain Current⁽⁴⁾

—

High Impedance Output Current

(3-State Output pins)^{(5, 6)}

Clamp Diode Voltage

VCC = Max.

—

±1

—

±1

VCC = Min., IIN = –18mA

–0.7

–140

100

–1.2

–250

—

(3)

IOS

Short Circuit Current

VCC = Max., VO = GND

µA

Input Hysteresis

—

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = Max.

VIN = GND or VCC

500

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V^CC= 5.0V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

4. Pins with Bus-hold are identified in the pin description.

5. The test limit for this parameter is ±5µA at TA = -55°C.

6. Does not include Bus-hold I/O pins.

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

Test Conditions⁽¹⁾

Min.

Typ.⁽²⁾Max.

Unit

(3)

IODL

Output LOW Current

VCC = 5V, VIN = VIH or VIL, VO = 1.5V

115

–115

3.3

200

–200

—

(3)

IODH

VOH

Output HIGH Current

Output HIGH Voltage

VCC = 5V, VIN = VIH or VIL, VO = 1.5V

–60

2.4

VCC = Min.

IOH = –16mA MIL.

VIN = VIH or VIL

VCC = Min.

IOH = –24mA COM’L.

IOL = 16mA MIL.

VOL

Output LOW Voltage

—

0.3

0.55

VIN = VIH or VIL

IOL = 24mA COM’L

5v16-link

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V^CC= 5.0V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

4. Duration of the condition can not exceed one second.

5. The test limit for this parameter is ±5µA at TA = -55°C.

IDT54/74FCT162H501AT/CT/ET

FASTCMOS18-BITREGISTEREDTRANSCEIVER

MILITARYANDCOMMERCIALTEMPERATURERANGES

POWERSUPPLYCHARACTERISTICS

Symbol

Parameter

Test Conditions⁽¹⁾

Min.

Typ.⁽²⁾

Max.

Unit

∆ICC

Quiescent Power Supply

CurrentTTLInputs HIGH

VCC = Max.

VIN = 3.4V

—

0.5

1.5

(3)

ICCD

Dynamic Power Supply Current⁽⁴⁾

TotalPowerSupplyCurrent⁽⁶⁾

VCC = Max., Outputs Open

OEAB = OEBA = VCC or GND

OneInputToggling

VIN = VCC

VIN = GND

—

120

µA/

MHz

50% Duty Cycle

VCC = Max., Outputs Open

fCP = 10MHz (CLKAB)

50% Duty Cycle

OEAB = OEBA = VCC

LEAB = GND

VIN = VCC

VIN = GND

—

0.8

1.3

1.7

3.2

VIN = 3.4V

VIN = GND

OneBitToggling

fi = 5MHz

50% Duty Cycle

VCC = Max., Outputs Open

fCP = 10MHz (CLKAB)

50% Duty Cycle

OEAB = OEBA = VCC

LEAB = GND

VIN = VCC

VIN = GND

—

3.8

8.5

6.5⁽⁵⁾

(5)

VIN = 3.4V

VIN = GND

20.8

Eighteen BitsToggling

fi = 2.5MHz

50% Duty Cycle

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 5.0V, +25°C ambient.

3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)

ICC = Quiescent Current (ICCL, ICCH and ICCZ)

∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

NCP = Number of Clock Inputs at fCP

fi = Input Frequency

Ni = Number of Inputs at fi

IDT54/74FCT162H501AT/CT/ET

FASTCMOS18-BITREGISTEREDTRANSCEIVER

MILITARYANDCOMMERCIALTEMPERATURERANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT162H501AT

FCT162H501CT

FCT162H501ET

Com'l. Mil.

Symbol

Parameter

Condition⁽¹⁾Min ⁽²⁾Max Min ⁽²⁾Max Min ⁽²⁾Max Min ⁽²⁾Max Min ⁽²⁾Max Min ⁽²⁾Max Unit

—

(4)

fMAX CLKAB or CLKBA frequency

CL = 50pF

RL = 500

—

150

—

150

—

150

—

150

—

150

—

MHz

tPLH Propagation Delay

tPHL Ax to Bx or Bx to Ax

tPLH Propagation Delay

tPHL LEBA to Ax, LEAB to Bx

tPLH Propagation Delay

tPHL CLKBA to Ax, CLKAB to Bx

tPZH Output Enable Time

1.5 5.1 1.5 5.6 1.5 4.6 1.5 4.6 1.5 3.8

Ω

1.5 5.6 1.5

1.5 5.3 1.5 5.6 1.5 4.2

1.5 5.3 1.5 5.4 1.5 4.2

—

1.5

1.5 6.4 1.5 5.6 1.5

1.5 4.8

tPZL

to Ax, OEAB to Bx

OEBA

tPHZ Output Disable Time

to Ax, OEAB to Bx

1.5 5.6 1.5

1.5 5.2 1.5 5.6 1.5 5.2

tPLZ

OEBA

tSU Set-up Time, HIGH or LOW

Ax to CLKAB, Bx to CLKBA

—

2.4

—

Hold Time HIGH or LOW

Ax to CLKAB, Bx to CLKBA

tSU Set-up Time HIGH or LOW Clock LOW

—

Ax to LEAB, Bx to LEBA

Clock HIGH

1.5

0.5

Hold Time, HIGH or LOW

Ax to LEAB, Bx to LEBA

(4)

LEAB or LEBA Pulse Width HIGH

—

(4)

CLKAB or CLKBA Pulse Width HIGH or LOW

(3)

tSK(o) Output Skew

—

0.5

—

0.5

—

0.5

—

0.5

—

0.5

NOTES:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This parameter is guaranteed but not tested.

IDT54/74FCT162H501AT/CT/ET

FASTCMOS18-BITREGISTEREDTRANSCEIVER

MILITARYANDCOMMERCIALTEMPERATURERANGES

TESTCIRCUITSANDWAVEFORMS

SWITCH POSITION

TEST CIRCUITS FOR ALL OUTPUTS

Test

Switch

Closed

Open

V CC

7.0V

Open Drain

Disable Low

Enable Low

All Other Tests

500Ω

V_OUT

VIN

Pulse

Generator

D.U.T.

5v16-link

DEFINITIONS:

50pF

C^L= Load capacitance: includes jig and probe capacitance.

R^T= Termination resistance: should be equal to Z^OUTof the Pulse

Generator.

SET-UP, HOLD, AND RELEASE TIMES

PULSEWIDTH

1.5V

DATA

INPUT

LOW-HIGH-LOW

tSU

1.5V

PULSE

1.5V

TIMING

INPUT

ASYNCHRONOUS CONTROL

tREM

PRESET

CLEAR

ETC.

1.5V

HIGH-LOW-HIGH

PULSE

1.5V

SYNCHRONOUS CONTROL

PRESET

1.5V

CLEAR

CLOCK ENABLE

ETC.

tSU

ENABLEANDDISABLETIMES

PROPAGATIONDELAY

ENABLE

DISABLE

SAME PHASE

INPUT TRANSITION

1.5V

CONTROL

INPUT

1.5V

tPLH

tPHL

tPZL

tPLZ

VOH

1.5V

VOL

OUTPUT

3.5V

1.5V

3.5V

VOL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

tPLH

0.3V

tPZH

tPHZ

OPPOSITE PHASE

INPUT TRANSITION

1.5V

VOH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

1.5V

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t^F≤ 2.5ns; t^R≤ 2.5ns.

IDT54/74FCT162H501AT/CT/ET

FASTCMOS18-BITREGISTEREDTRANSCEIVER

MILITARYANDCOMMERCIALTEMPERATURERANGES

ORDERINGINFORMATION

IDT

FCT XXX

XXXX

Temperature

Range

Family Bus Hold Device Type Package

Process

Blank

Commercial

MIL-STD-883, Class B

Shrink Small Outline Package (SO56-1)

Thin Shrink Small Outline Package (SO56-2)

Thin Very Small Outline Package (SO56-3)

CERPACK (E56-1)

18-Bit Registered Transceiver

501AT

501CT

501ET

Bus-Hold

162

Double-Density 5 Volt Balanced Drive

– 55°C to +125°C

– 40°C to +85°C

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74FCT162H501ATEG [IDT]

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