IDT74FCT163543PF [IDT]
3.3V CMOS 16-BIT LATCHED TRANSCEIVER; 3.3V CMOS 16位锁存收发器
| 型号： | IDT74FCT163543PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS 16-BIT LATCHED TRANSCEIVER |
| 文件： | 总7页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74FCT163543/A/C
ADVANCE INFORMATION
3.3V CMOS
16-BIT LATCHED
TRANSCEIVER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The FCT163543/A/C 16-bit latched transceivers are built
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
using advanced dual metal CMOS technology. These high-
speed,low-powerdevicesareorganizedastwoindependent8-
bit D-type latched transceivers with separate input and output
control to permit independent control of data flow in either
direction. For example, the A-to-B Enable (xCEAB) must be
LOWinordertoenterdatafromtheAportortooutputdatafrom
the B port. xLEAB controls the latch function. When xLEAB is
LOW, the latches are transparent. A subsequent LOW-to-
HIGH transition of xLEAB signal puts the A latches in the
storage mode. xOEAB performs output enable function on the
B port. Data flow from the B port to the A port is similar but
requiresusingxCEBA,xLEBA,andxOEBAinputs.Flow-through
organization of signal pins simplifies layout. All inputs are
designed with hysteresis for improved noise margin.
The FCT163543/A/C have series current limiting resistors.
These offer low ground bounce, minimal undershoot, and
controlled output fall times–reducing the need for external
series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
1
OEBA
CEBA
2OEBA
2CEBA
1
1
LEBA
2LEBA
2OEAB
2CEAB
1
OEAB
1
CEAB
LEAB
2LEAB
1
C
C
D
2A1
1A1
2B1
D
1B1
C
D
C
D
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
3250 drw 01
3250 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
SEPTEMBER 1996
1996 Integrated Device Technology, Inc.
8.7
DSC-3250/2
1
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
Description
PIN CONFIGURATIONS
PIN DESCRIPTION
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xLEAB
xLEBA
xAx
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1LEAB
1CEAB
GND
1A1
1OEBA
1LEBA
1CEBA
GND
1B1
2
B-to-A Enable Input (Active LOW)
3
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
4
5
xBx
1A2
6
1B2
3250 tbl 01
VCC
1A3
7
VCC
1B3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
8
Description
Terminal Voltage with
Respect to GND
Max.
Unit
1A4
9
1B4
(2)
VTERM
–0.5 to +4.6
V
1A5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1B5
GND
1A6
GND
1B6
(3)
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
V
V
(4)
VTERM
Terminal Voltage with
Respect to GND
–0.5 to
VCC + 0.5
–65 to +150
1A7
1B7
1A8
1B8
SO56-1
SO56-2
SO56-3
TSTG
IOUT
Storage Temperature
°C
2A1
2B1
DC Output Current
–60 to +60
mA
3250 lnk 03
2A2
2B2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
2A3
2B3
GND
2A4
GND
2B4
2A5
2B5
2A6
2B6
VCC
2A7
VCC
2B7
FUNCTION TABLE(1, 3)
For A-to-B (Symmetric with B-to-A)
2A8
2B8
GND
GND
Latch
Status
Output
Buffers
2CEAB
2LEAB
2OEAB
2CEBA
2LEBA
2OEBA
Inputs
x
x
x
xAx to xBx
Storing
xBx
High Z
CEAB
LEAB
OEAB
H
X
L
X
H
L
X
X
L
Storing
X
3250 drw 03
SSOP/
Transparent
Current A Inputs
TSSOP/TVSOP
TOP VIEW
L
L
L
H
L
L
H
H
Storing
Transparent
Storing
Previous(2) A Inputs
High Z
H
High Z
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTES:
3250 tbl 02
1. A-to-B data flow shown; B-to-A flow control is the same, except using
xCEBA, x LEBA and xOEBA.
2. Before xLEAB LOW-to-HIGH Transition
3. H = HIGH Voltage Level
Symbol
Parameter(1)
Input
Conditions
IN = 0V
Typ. Max. Unit
CIN
V
3.5
6.0
pF
Capacitance
I/O
L = LOW Voltage Level
X = Don’t Care
CI/O
V
OUT = 0V
3.5
8.0
pF
Capacitance
3250 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
8.7
2
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max. Unit
V
IH
Input HIGH Level (Input pins)
Guaranteed Logic HIGH Level
2.0
—
5.5
CC+0.5
0.8
V
Input HIGH Level (I/O pins)
Input LOW Level
2.0
—
—
V
VIL
Guaranteed Logic LOW Level
–0.5
V
(Input and I/O pins)
I
I
I H
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
V
CC = Max.
V
V
V
V
V
V
I
I
I
I
= 5.5V
= VCC
—
—
—
—
—
—
—
—
±1
±1
±1
±1
±1
±1
µ
A
I L
= GND
= GND
—
—
I
I
OZH
OZL
VCC = Max.
O
O
= VCC
—
µA
= GND
—
V
IK
Clamp Diode Voltage
V
V
V
V
V
CC = Min., IIN = –18mA
—
–
0.7
–
1.2
V
I
I
ODH
ODL
Output HIGH Current
CC = 3.3V, VIN = VIH or VIL,
CC = 3.3V, VIN = VIH or VIL,
V
V
O
O
= 1.5V(3)
= 1.5V(3)
–36
50
–60
90
–110
200
—
mA
mA
V
Output LOW Current
V
OH
OL
Output HIGH Voltage
CC = Min.
I
I
I
OH = –0.1mA
OH = –3mA
OH = –8mA
V
CC–
0.2
—
IN = VIH or VIL
2.4
3.0
3.0
—
V
V
V
CC = 3.0V
IN = VIH or VIL
CC = Min.
2.4(5)
—
V
Output LOW Voltage
I
I
I
I
OL = 0.1mA
OL = 16mA
OL = 24mA
OL = 24mA
—
—
—
—
—
0.2
0.3
0.3
0.2
0.4
V
VIN = VIH or VIL
0.55
0.50
V
V
V
CC = 3.0V
IN = VIH or VIL
I
OS
Short Circuit Current(4)
Input Hysteresis
CC = Max., V
O
= GND(3)
—
–60
—
–
135
150
0.1
–240
—
mA
mV
VH
I
I
I
CCL
CCH
CCZ
Quiescent Power Supply Current
V
V
CC = Max.,
IN = GND or VCC
—
10
µA
3250 lnk 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC –0.6V at rated current.
8.7
3
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
—
2.0
30
µA
VIN = VCC –0.6V(3)
ICCD
Dynamic Power Supply Current(4)
VCC = Max., Outputs Open VIN = VCC
xCEAB and xOEAB = GND VIN = GND
xCEBA = VCC
—
60
100
µA/
MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open VIN = VCC
—
—
—
—
0.6
0.6
2.4
2.4
1.0
1.0
mA
fi = 10MHz
VIN = GND
50% Duty Cycle
xLEAB, xCEAB and
xOEAB= GND
xCEBA = VCC
VIN = VCC –0.6V
VIN = GND
One Bit Toggling
VCC = Max., Outputs Open VIN = VCC
4.0(5)
4.3(5)
fi = 2.5MHz
VIN = GND
50% Duty Cycle
xLEAB, xCEAB and
xOEAB= GND
VIN = VCC –0.6V
VIN = GND
xCEBA = VCC
Sixteen Bits Toggling
3250 tbl 06
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
8.7
4
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
FCT163543A FCT163543C
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4)
FCT163543
Symbol
Parameter
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH Propagation Delay
tPHL Transparent Mode
1.5
8.5
1.5
6.5
1.5
5.3
ns
xAx to xBx or xBx to xAx
tPLH Propagation Delay
tPHL xLEBA to xAx, xLEAB to xBx
tPZH Output Enable Time
1.5
1.5
12.5
12.0
1.5
1.5
8.0
9.0
1.5
1.5
7.0
8.0
ns
ns
tPZL xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
tPHZ Output Disable Time
tPLZ xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
1.5
9.0
1.5
7.5
1.5
6.5
ns
tSU
Set-up Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
Hold Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
xLEBA or xLEAB Pulse Width
LOW
3.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
ns
ns
ns
tH
tW
—
—
—
tSK(o) Output Skew(3)
0.5
0.5
0.5
ns
NOTES:
3250 tbl 07
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
and Enable/Disable times should be degraded by 20%.
8.7
5
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
6V
←
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
V
CC
Open
GND
6V
500Ω
500Ω
GND
V
OUT
V IN
Pulse
Generator
D.U.T.
Open
DEFINITIONS:
50pF
3250 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
R T
C
L
3250 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
INPUT
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
1.5V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
SYNCHRONOUS CONTROL
3250 drw 07
3V
PRESET
CLEAR
CLOCK ENABLE
ETC.
1.5V
0V
tSU
tH
3250 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3V
1.5V
3V
VOL
VOH
OUTPUT
NORMALLY
LOW
SWITCH
6V
tPLH
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
3250 drw 08
0V
3250 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If VCC is below 3V, input voltage swings should be adjusted not to
exceed VCC.
8.7
6
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
X
FCT
XXXX
Device
Type
X
Temperature
Range
Package
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
PV
PA
PF
163543
16-Bit Latched Transceiver
163543A
163543C
74
–40°C to +85°C
3250 drw 10
8.7
7
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