IDT74FCT574DTLG [IDT]
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| 型号： | IDT74FCT574DTLG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 暂无描述 |
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FAST CMOS OCTAL
D REGISTERS (3-STATE)
IDT54/74FCT574/A/C
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IDT54/74FCT574 equivalent to FAST™ speed and drive
TheFCT574isan8-bitregisterbuiltusinganadvanceddualmetalCMOS
technology. TheseregistersconsistofeightD-typeflip-flopswithabuffered
commonclockandbuffered3-stateoutputcontrol.Whentheoutputenable
IDT54/74FCT574A up to 30% faster than FAST
IDT54/74FCT574C up to 50% faster than FAST
IOL = 48mA (commercial) and 32mA (military)
CMOS power levels (1mW typ. static)
Edge triggered master/slave, D-type flip-flops
Buffered common clock and buffered common three-state control
Military product compliant to MIL-STD-883, Class B
Meets or exceeds JEDEC Standard 18 specifications
Available in the following packages:
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−
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(
)is low, the eightoutputs are enabled. Whenthe
inputis high, the
outputs areinthehigh-impedancestate.
Inputdatameetingtheset-upandholdtimerequirements oftheDinputs
istransferredtotheOoutputsonthelow-to-hightransitionoftheclockinput.
The FCT574 has non-inverting outputs with respect to the data at the D
inputs.
•
•
Commercial: SOIC
Military: CERDIP, LCC, CERPACK
D0
D1
D2
D3
D4
D5
D6
D7
CP
D
D
D
D
D
D
D
D
CP
CP
CP
CP
CP
CP
CP
CP
Q
Q
Q
Q
Q
Q
Q
Q
OE
O2
O3
O6
O0
O1
O4
O5
O7
1
c
1999 Integrated Device Technology, Inc.
DSC-5428/-
IDT54/74FCT574/A/C
FASTCMOSOCTALDREGISTER(3-STATE)
MILITARYANDCOMMERCIALTEMPERATURERANGES
VCC
20
19
18
17
16
15
14
13
12
11
1
2
OE
D0
D1
D2
D3
INDEX
O0
O1
O2
O3
O4
3
2
20 19
3
4
1
O1
4
5
6
7
8
18
17
16
15
14
D2
D3
O2
O3
O4
O5
D20-1
SO20-2
E20-1
5
L20-2
D4
D5
D6
D4
D5
D6
D7
6
O5
O6
O7
CP
7
9
10
11 12 13
8
9
GND
10
LCC
TOP VIEW
CERDIP/ SOIC/ CERPACK
TOP VIEW
Symbol
Rating
Commercial
Military
Unit
Pin Names
Description
D Flip-Flop Data Inputs
(2)
VTERM
Terminal Voltage
–0.5 to +7
–0.5 to +7
V
DN
with Respect to GND
CP
Clock Pulse for the register. Enters data on LOW-to-HIGH
transition.
(3)
VTERM
Terminal Voltage
with Respect to GND
–0.5 to VCC
–0.5 to VCC
V
ON
3-State Outputs (true)
TA
Operating Temperature
0 to +70
–55 to +125
–65 to +135
°C
°C
Active LOW 3-state Output Enable Input
TBIAS
Temperature Under
Bias
–55 to +125
TSTG
PT
Storage Temperature
–55 to +125
0.5
–65 to +150
0.5
°C
W
Power Dissipation
DC Output Current
Inputs
CP
Outputs Internal
IOUT
120
120
mA
8-link
Function
OE
DN
ON
QN
NOTES:
Hi-Z
H
H
L
L
H
H
L
H
↑
↑
↑
X
X
L
H
L
Z
Z
L
H
Z
Z
NC
NC
H
L
H
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability. No
terminal voltage may exceed VCC by +.5V unless otherwise noted.
Load Register
↑
H
L
NOTE:
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
NC = No Change
(TA = +25OC, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
↑
= LOW-to-HIGH transition
CIN
Input Capacitance
VIN = 0V
6
10
12
pF
pF
COUT
Output
VOUT = 0V
8
Capacitance
8-link
NOTE:
1. This parameter is measured at characterization but not tested.
2
IDT54/74FCT574/A/C
FASTCMOSOCTALDREGISTER(3-STATE)
MILITARYANDCOMMERCIALTEMPERATURERANGES
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
Typ.(2) Max.
Unit
VIH
2
—
—
—
0.8
5
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
V
Input HIGH Current
VI = VCC
—
µA
VI = 2.7V
VI = 0.5V
VI = GND
VO = VCC
VO = 2.7V
VO = 0.5V
VO = GND
—
—
5(4)
–5(4)
–5
II L
Input LOW Current
—
—
—
—
IOZH
IOZL
Off State (High Impedance)
Output Current
VCC = Max.
—
—
10
µA
—
—
10(4)
–10(4)
–10
–1.2
—
—
—
—
—
VIK
IOS
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
—
–0.7
–120
VCC
VCC
4.3
4.3
GND
GND
0.3
0.3
V
mA
V
–60
VHC
VHC
2.4
2.4
—
VOH
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
—
VCC = Min.
IOH = –300µA
—
VIN = VIH or VIL
IOH = –12mA MIL.
—
IOH = –15mA COM'L.
—
VOL
Output LOW Voltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VLC
V
(4)
VCC = Min.
IOL = 300µA
—
VLC
VIN = VIH or VIL
IOL = 32mA MIL.
IOL = 48mA COM'L.
—
0.5
0.5
—
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
3
IDT54/74FCT574/A/C
FASTCMOSOCTALDREGISTER(3-STATE)
MILITARYANDCOMMERCIALTEMPERATURERANGES
VLC = 0.2V; VHC = VCC - 0.2V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2) Max.
Unit
Quiescent Power Supply Current
VCC = Max.
VIN ≥ VHC; VIN ≤ VLC
ICC
—
0.2
1.5
mA
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V
∆ICC
—
—
0.5
2
mA
(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
= GND
VIN ≥ VHC
VIN ≤ VLC
0.15
0.25
mA/
MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
1.7
2.2
4
6
mA
fCP = 10MHz
50% Duty Cycle
= GND
fi = 5MHz
VIN = 3.4V
VIN = GND
50% Duty Cycle
One Bit Toggling
VCC = Max.
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
4
7.8(5)
Outputs Open
fCP = 10MHz
50% Duty Cycle
= GND
Eight Bits Toggling
fi = 2.5MHz
VIN = 3.4V
VIN = GND
6.2
16.8(5)
50% Duty Cycle
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT574/A/C
FASTCMOSOCTALDREGISTER(3-STATE)
MILITARYANDCOMMERCIALTEMPERATURERANGES
54/74FCT574
Com'l. Mil.
54/74FCT574A
Com'l. Mil.
54/74FCT574C
Com'l. Mil.
(2)
(2)
(2)
(2)
(2)
(2)
Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max.
Symbol
tPLH
Parameter
Propagation Delay
CP to ON
Conditions(1)
CL = 50pF
Unit
2
10
2
11
2
6.5
2
7.2
2
5.2
2
6.2
ns
tPHL
RL = 500Ω
tPZH
tPZL
tPHZ
tPLZ
tSU
Output Enable Time
1.5
1.5
2
12.5
8
1.5
1.5
2
14
8
1.5
1.5
2
6.5
5.5
—
—
—
1.5
1.5
2
7.5
6.5
—
—
—
1.5
1.5
2
5.5
5
1.5
1.5
2
6.2
5.7
—
—
—
ns
ns
ns
ns
ns
Output Disable Time
Set-up Time HIGH
or LOW, DN to CP
Hold Time HIGH
or LOW, DN to CP
CP Pulse Width
HIGH or LOW
—
—
—
—
—
—
—
—
—
tH
1.5
7
1.5
7
1.5
5
1.5
6
1.5
5
1.5
6
tW
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
5
IDT54/74FCT574/A/C
FASTCMOSOCTALDREGISTER(3-STATE)
MILITARYANDCOMMERCIALTEMPERATURERANGES
Test
Switch
Closed
Open
V CC
7.0V
Open Drain
Disable Low
Enable Low
All Other Tests
500Ω
500Ω
V OUT
VIN
Pulse
D.U.T.
Generator
8-link
50pF
DEFINITIONS:
T
R
L
C
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
Octal link
3V
1.5V
0V
DATA
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
Octal link
CLEAR
CLOCK ENABLE
ETC.
tSU
tH
Octal link
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
OUTPUT
3.5V
1.5V
3.5V
VOL
1.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
0.3V
0.3V
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
Octal link
0V
Octal link
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; Zo ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
6
IDT54/74FCT574/A/C
FASTCMOSOCTALDREGISTER(3-STATE)
MILITARYANDCOMMERCIALTEMPERATURERANGES
IDT
XX
FCT
XXXX
XX
X
Temp. Range
Package
Process
Device Type
Blank
B
Commercial
MIL-STD-883, Class B
Commercial Options
Small Outline IC (SO20-2)
SO
Military Options
D
E
L
CERDIP (D20-1)
CERPACK (E20-1)
Leadless Chip Carrier (L20-2)
Fast CMOS Octal D Register (3-State)
574
574A
574C
54
74
– 55°C to +125°C
– 40°C to +85°C
CORPORATE HEADQUARTERS
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
7
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