IDT74FCT841ATPY8 [IDT]
Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, SSOP-24;
| 型号： | IDT74FCT841ATPY8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, SSOP-24 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总7页 (文件大小：61K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS BUS
IDT74FCT841AT/CT
INTERFACE LATCH
FEATURES:
DESCRIPTION:
• A and C grades
The FCT841T series is built using an advanced dual metal CMOS
technology.
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Power off disable outputs permit "live insertion"
• Available in SOIC, SSOP, and QSOP packages
The FCT841T bus interface latches are designed to eliminate the extra
packages required to buffer existing latches and provide extra data width
for wider address/data paths or buses carrying parity. The FCT841T are
buffered, 10-bit wide versions of the popular FCT373T function. They are
ideal for use as an output port requiring high IOL/IOH.
All of the FCT841T high-performance interface family can drive large
capacitiveloads,whileprovidinglow-capacitancebusloadingatbothinputs
and outputs. All inputs have clamp diodes to ground and all outputs are
designed for low-capacitance bus loading in high-impedance state.
FUNCTIONALBLOCKDIAGRAM
D0
D1
D2
D3
D4
D5
D8
D9
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
LE
LE
LE
LE
LE
LE
LE
LE
LE
OE
Y0
Y1
Y2
Y3
Y4
Y5
Y8
Y9
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-2571/9
IDT74FCT841AT/CT
FASTCMOSBUSINTERFACELATCH
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +7
(3)
24
23
22
21
20
19
18
17
16
15
14
13
1
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
OE
D0
VCC
Y0
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
°C
mA
2
3
4
D1
D2
Y1
Y2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
D3
D4
D5
Y3
Y4
Y5
5
6
7
8
9
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
D6
D7
Y6
Y7
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
D8
D9
Y8
Y9
LE
10
11
CIN
VIN = 0V
6
8
10
12
pF
pF
COUT
VOUT = 0V
GND
12
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ SSOP/ QSOP
TOP VIEW
PINDESCRIPTION
FUNCTIONTABLE(1)
Pin Names
I/O
Description
Inputs
Internal
Output
OE
LE
H
H
L
Dx
L
Qx
L
Yx
Z
Function
High Z
Dx
I
I
Latch Data Inputs
H
LE
Latch Enable Input. The latches are transparent when
LE is HIGH. Input data is latched on the HIGH-to-
LOW transition.
H
H
X
L
H
Z
High Z
H
N C
L
Z
Latched(HighZ)
Transparent
Transparent
Latched
Y x
O
I
3-State Latch Outputs
L
H
H
L
L
OE
Output Enable Control. When OE is LOW, the
outputs are enabled. When OE is HIGH, the outputs
Yx are in high-impedance (off) state.
L
L
H
X
H
H
N C
N C
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
NC = No Change
2
IDT74FCT841AT/CT
INDUSTRIALTEMPERATURERANGE
FASTCMOSBUSINTERFACELATCH
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
Symbol
VIH
VIL
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
Unit
V
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
—
—
—
—
—
—
0.8
±1
±1
±1
±1
±1
–1.2
—
V
IIH
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current(4)
VI = 2.7V
VI = 0.5V
VI = 2.7V
VI = 0.5V
—
µA
µA
µA
IIL
VCC = Max.
—
IOZH
IOZL
II
VCC = Max., VI = VCC (Max.)
—
—
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
—
µA
V
VIK
VH
–0.7
200
0.01
—
mV
mA
ICC
Quiescent Power Supply Current
VCC = Max.
1
VIN = GND or VCC
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
IOH = –8mA
Min.
2.4
2
Typ.(2)
3.3
3
0.3
Max.
—
—
Unit
VOH
Output HIGH Voltage
VCC = Min
V
VIN = VIH or VIL
VCC = Min
IOH = –15mA
IOL = 48mA
VOL
Output LOWVoltage
—
0.5
V
VIN = VIH or VIL
VCC = Max., VO = GND(3)
IOS
Short Circuit Current
Input/Output Power Off Leakage(5)
–60
—
–120
—
–225
mA
µA
IOFF
VCC = 0V, VIN or VO ≤ 4.5V
±1
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
3
IDT74FCT841AT/CT
FASTCMOSBUSINTERFACELATCH
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
2
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
Outputs Open
OE = GND
LE = VCC
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fi = 10MHz
VIN = VCC
VIN = GND
—
—
1.5
1.8
3.5
4.5
mA
mA
50% Duty Cycle
OE = GND
LE = VCC
VIN = 3.4V
VIN = GND
One Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
VIN = VCC
VIN = GND
—
—
3
5
6(5)
50% Duty Cycle
OE = GND
LE = VCC
VIN = 3.4V
VIN = GND
14(5)
Eight Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT74FCT841AT/CT
INDUSTRIALTEMPERATURERANGE
FASTCMOSBUSINTERFACELATCH
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
74FCT841AT
74FCT841CT
Min.(2)
Symbol
tPLH
Parameter
Condition(1)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 5pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
RL = 500Ω
Min.(2)
Max.
Max.
Unit
PropagationDelay
Dx to Yx (LE = HIGH)
1.5
9
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
5.5
ns
tPHL
1.5
1.5
1.5
1.5
1.5
1.5
1.5
13
12
13
6.4
15
6.5
12
5.7
6
tPLH
tPHL
PropagationDelay
LE to Yx
ns
ns
ns
16
tPZH
tPZL
OutputEnableTime,
11.5
23
OE to Yx
tPHZ
tPLZ
OutputDisableTime,
7
OE to Yx
18
tSU
tH
DatatoLESet-upTime
Data to LE Hold Time
LE Pulse Width HIGH(3)
2.5
2.5
4
—
—
—
2.5
2.5
4
—
—
—
ns
ns
ns
tW
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. This condition is guaranteed but not tested.
5
IDT74FCT841AT/CT
FASTCMOSBUSINTERFACELATCH
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VCC
SWITCHPOSITION
7.0V
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
VOUT
VIN
Pulse
Generator
D.U.T
.
All Other Tests
50pF
500Ω
T
R
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
L
C
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
Octal link
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Octal link
Set-Up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
VOH
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
Octal link
0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT841AT/CT
INDUSTRIALTEMPERATURERANGE
FASTCMOSBUSINTERFACELATCH
ORDERINGINFORMATION
IDT
XX
FCT
XXXX
X
Temp. Range
Device Type
Package
SO
PY
Q
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
841AT 10-Bit Non-Inverting Latch
841CT
74
- 40°C to +85°C
DATASHEETDOCUMENTHISTORY
6/25/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
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www.idt.com
7
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