IDT74LVC16541APF8 [IDT]
Bus Driver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.40 MM PITCH, TVSOP-48;型号: | IDT74LVC16541APF8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Bus Driver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.40 MM PITCH, TVSOP-48 驱动 光电二极管 输出元件 逻辑集成电路 电视 |
文件: | 总6页 (文件大小:65K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT74LVC16541A
3.3V CMOS
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
DESCRIPTION:
FEATURES:
This 16-bit buffer/driver is built using advanced dual metal CMOS
technology. This device is composed of two 8-bit sections with separate
output-enablesignals.Foreither8-bitbuffersection,thetwooutput-enable
(1OE1and1OE2or2OE1and2OE2)inputsmustbelowforthecorrespond-
ing Y outputs to be active. If either output-enable input is high, the outputs
ofthat8-bitbuffersectionareinthehighimpedancestate.Toensurethehigh-
impedancestateduringpowerup orpowerdown,OEshouldbetiedtoVcc
through a pullup resistor; the minimum value of the resistor is determined
by the current sinking capability of the driver.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V
devices. Thisfeatureallowstheuseofthisdeviceasatranslatorinamixed
3.3V/5V supply system.
The LVC16541A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
1
24
1OE1
2OE1
48
25
1OE2
2OE2
47
2
36
13
1Y1
2Y1
1A1
2A1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4701/2
IDT74LVC16541A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
°C
mA
mA
1
2
48
47
46
45
44
1OE2
1OE1
1Y1
IOUT
DC Output Current
1A1
1A2
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
3
1Y2
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
GND
4
5
6
GND
1A3
1Y3
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1Y4
1A4
43
42
41
40
VCC
7
VCC
1A5
8
1Y5
1Y6
9
1A6
GND
1A7
1A8
2A1
10
CAPACITANCE (TA = +25°C, F = 1.0MHz)
39
38
37
36
GND
1Y7
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
11
12
13
14
15
16
17
18
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
1Y8
COUT
CI/O
6.5
2Y1
2Y2
6.5
NOTE:
35
34
2A2
1. As applicable to the device type.
GND
GND
2A3
33
2Y3
2Y4
32
31
30
2A4
VCC
PINDESCRIPTION
Pin Names
VCC
2A5
2Y5
2Y6
Description
19
20
21
22
23
xOEx
3-StateOutputEnableInputs(ActiveLOW)
DataInputs
29
28
27
26
25
2A6
xAx
GND
GND
2A7
xYx
3-StateOutputs
2Y7
2Y8
2A8
24
2OE1
2OE2
(1)
FUNCTION TABLE (EACH 8-BIT BUFFER)
SSOP/ TSSOP/ TVSOP
TOP VIEW
Inputs
Outputs
xOE1
xOE2
xAx
L
xYx
L
L
L
L
L
H
H
H
X
X
H
X
Z
X
Z
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2
IDT74LVC16541A
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
µA
IOZH
IOZL
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
±50
µA
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
3.6 ≤ VIN ≤ 5.5V(2)
—
—
—
—
10
500
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2.2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74LVC16541A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
PowerDissipationCapacitanceperBuffer/DriverOutputsenabled
PowerDissipationCapacitanceperBuffer/DriverOutputsdisabled
CL = 0pF, f = 10Mhz
35
4
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
Max.
Unit
PropagationDelay
xAx to xYx
—
5
1.1
4.2
ns
ns
ns
ps
tPHL
tPZH
OutputEnableTime
xOEx to xYx
—
—
—
6.9
7.4
—
1.5
1.9
—
5.6
6.8
500
tPZL
tPHZ
OutputDisableTime
tPLZ
xOEx to xYx
OutputSkew(2)
tSK(o)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC16541A
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
tPHL
VLOAD
VIH
6
6
2 x Vcc
Vcc
tPLH
VOH
VT
VOL
OUTPUT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VT
Vcc / 2
150
V
tPHL
tPLH
VLZ
VHZ
CL
mV
mV
pF
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
150
30
LVC Link
VLOAD
Open
GND
Propagation Delay
VCC
DISABLE
ENABLE
VIH
VT
500Ω
CONTROL
INPUT
VIN
VOUT
0V
Pulse (1, 2)
tPZL
tPLZ
D.U.T.
Generator
VLOAD/2
VT
VLOAD/2
VOL+VLZ
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
500Ω
RT
CL
tPHZ
tPZH
VOH
VOH-VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
LVC Link
VT
0V
Test Circuit for All Outputs
0V
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
SWITCHPOSITION
DATA
INPUT
VT
0V
Test
Switch
VLOAD
GND
tSU
tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
Open Drain
Disable Low
Enable Low
tREM
ASYNCHRONOUS
CONTROL
Disable High
Enable High
SYNCHRONOUS
CONTROL
All Other Tests
Open
tSU
tH
LVC Link
VIH
VT
0V
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
VOH
LOW-HIGH-LOW
VT
VOL
VT
PULSE
OUTPUT 1
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
LVC Link
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC16541A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
X
XX
XXXX
XX
LVC
IDT
Bus-Hold
Family Device Type Package
Temp. Range
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
541A 16-Bit Buffer/Driver with 3-State Outputs
16
Double-Density with Resistors, ±24mA
No Bus-hold
Blank
74
-40°C to +85°C
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www.idt.com
6
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