IDT74LVC16952APVG [IDT]
Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56;型号: | IDT74LVC16952APVG |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56 光电二极管 |
文件: | 总6页 (文件大小:80K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT74LVC16952A
3.3V CMOS 16-BIT
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
This 16-bit registered transceiver is built using advanced dual metal
CMOStechnology.This high-speed,lowpowerdeviceis organizedas two
independent8-bitD-type registeredtransceivers withseparate inputand
outputcontrolforindependentcontrolofdata flowineitherdirection. For
example,theA-to-BEnable(CEAB)mustbeLOWtoenterdatafromtheA
port.CLKABcontrolstheclockingfunction.WhenCLKABtogglesfromLOW-
to-HIGH, the data present on the A port will be clocked into the register.
OEABperformstheoutputenablefunctionontheBport. Dataflowfromthe
BporttoAportissimilarbutrequiresusingCEBA,CLKBA,andOEBAinputs.
Full16-bitoperationisachievedbytyingthe controlpinsoftheindependent
transceivers together.
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
Allpins canbedrivenfromeither3.3Vor5Vdevices.This featureallows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC16952A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
54
31
1CEBA
2CEBA
55
30
1CLKBA
2CLKBA
28
1
1OEAB
2OEAB
3
26
1CEAB
2CEAB
27
2
1CLKAB
2CLKAB
29
56
1OEBA
2OEBA
C
CE
D
C
CE
D
15
5
1A1
2A1
52
42
1B1
2B1
C
C
CE
CE
D
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4492/3
IDT74LVC16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
1
2
3
56
55
54
53
52
1OEAB
CLKAB
1CEAB
1OEBA
° C
mA
mA
1
1CLKBA
IOUT
DC Output Current
1
CEBA
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
4
5
6
GND
1A1
GND
1B1
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
51
50
49
48
1A2
VCC
1B2
NOTE:
7
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VCC
1B3
1B4
1B5
8
1A3
1A4
1A5
9
10
47
46
45
44
11
12
13
14
15
16
17
18
GND
1B6
GND
1A6
1A7
1A8
1B7
43
42
PINDESCRIPTION
1B8
2A1
2A2
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xCLKAB
xCLKBA
xAx
Description
2B1
2B2
41
A-to-BOutputEnable Inputs (Active LOW)
B-to-AOutputEnable Inputs (Active LOW)
A-to-B Clock Enable Inputs (Active LOW)
B-to-A Clock Enable Inputs (Active LOW)
A-to-B Clock Inputs
40
39
38
2A3
2B3
GND
GND
2B4
2B5
2B6
19
20
21
22
23
A
2
4
37
36
35
34
2A5
2A6
VCC
B-to-A Clock Inputs
A-to-BDataInputsorB-to-A3-StateOutputs
B-to-ADataInputsorA-to-B3-StateOutputs
xBx
VCC
2B7
2A7
24
25
26
27
33
32
2A8
2B8
GND
GND
2CEAB
31
30
29
CEBA
2
FUNCTIONTABLE(1,2)
CLKAB
2OEAB
2
CLKBA
2
28
OEBA
2
Inputs
Outputs
xBx
xCEAB
xCLKAB
xOEAB
xAx
X
(3)
H
X
L
X
L
↑
↑
X
L
L
L
L
H
B
SSOP/ TSSOP/ TVSOP
TOP VIEW
(3)
X
B
L
L
H
Z
L
H
X
X
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
NOTES:
Symbol
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA,
and xOEBA.
2. H = HIGH Voltage Level
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
COUT
CI/O
6.5
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
6.5
NOTE:
1. As applicable to the device type.
3. Output level of B before the indicated steady-state input conditions were established.
2
IDT74LVC16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
5
µA
µ A
IOZH
IOZL
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
10
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
50
µ A
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
(2)
3.6 ≤ VIN ≤ 5.5V
—
—
—
—
10
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
500
µ A
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2.2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74LVC16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
87
Unit
CPD
PowerDissipationCapacitanceperLatchOutputsenabled
PowerDissipationCapacitanceperLatchOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
43
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
Max.
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Min.
Max.
Unit
PropagationDelay
—
7.6
1.6
6.6
ns
ns
ns
tPHL
xCLKAB, xCLKBA to xBx, xAx
tPZH
tPZL
tPHZ
tPLZ
tSU
OutputEnableTime
—
—
8
1.1
1.9
6.6
6.7
xOEBA, xOEAB to xAx, xBx
OutputDisableTime
7.1
xOEBA, xOEAB to xAx, xBx
Set-up Time, HIGH or LOW
3.4
0.5
1.8
1.1
—
—
—
—
2.8
0.5
1.4
1.9
—
—
—
—
ns
ns
ns
ns
xAx, xBx before xCLKAB↑, xCLKBA↑
Hold Time, HIGH or LOW
tH
tSU
tH
xAx, xBx after xCLKAB↑, xCLKBA↑
Set-up Time, HIGH or LOW
xCEAB, xCEBA before xCLKAB↑, xCLKBA↑
Hold Time, HIGH or LOW
xCEAB, xCEBA after xCLKAB↑, xCLKBA↑
xLE Pulse Width HIGH or LOW, xCLKAB or xCLKBA
tW
3.3
—
—
—
3.3
—
—
ns
ps
(2)
tSK(o)
OutputSkew
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V Unit
tPHL
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
V
tPLH
VOH
VT
VOL
OUTPUT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
VT
Vcc / 2
150
V
tPHL
tPLH
VLZ
VHZ
CL
mV
mV
pF
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
150
30
LVC Link
VLOAD
Open
GND
Propagation Delay
VCC
DISABLE
ENABLE
VIH
VT
0V
500Ω
CONTROL
INPUT
VIN
VOUT
Pulse (1, 2)
tPZL
tPLZ
D.U.T.
Generator
VLOAD/2
VT
VLOAD/2
VOL+VLZ
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
500Ω
RT
CL
tPHZ
tPZH
VOH
VOH-VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
LVC Link
VT
0V
Test Circuit for All Outputs
0V
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
SWITCHPOSITION
DATA
INPUT
VT
0V
Test
Switch
VLOAD
GND
Open
tSU
tH
VIH
TIMING
INPUT
Open Drain
Disable Low
Enable Low
VT
0V
tREM
VIH
ASYNCHRONOUS
CONTROL
VT
Disable High
Enable High
0V
VIH
SYNCHRONOUS
CONTROL
All Other Tests
VT
tSU
0V
tH
LVC Link
VIH
VT
0V
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
VOH
LOW-HIGH-LOW
VT
VOL
VT
PULSE
OUTPUT 1
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
LVC Link
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC16952A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
Device Type Package
X
XX
XXXX
IDT
XX
LVC
Temp. Range
Bus-Hold
Family
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
16-Bit Registered Transceiver
952A
16
Double-Density, 24mA
Blank No Bus-hold
74
-40°C to +85°C
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6
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