IDT74LVCH16601APF8 [IDT]

Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56;


型号：	IDT74LVCH16601APF8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56 光电二极管输出元件逻辑集成电路电视
文件：	总7页 (文件大小：144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

EXTENDEDCOMMERCIALTEMPERATURERANGE

3.3V CMOS 18-BIT

UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS,

IDT74LVCH16601A

5 VOLT TOLERANT I/O, BUS-HOLD

FEATURES:

Data flow in each direction is controlled by output-enable (OEAB and

tSK(0)

(Output Skew) < 250ps

–

Typical

OEBA),latched-enable(LEABandLEBA),andclock(CLKABandCLKBA)

inputs. The clock can be controlled by the clock-enable (CLKENAB and

CLKENBA)inputs.

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

0.635mm pitch SSOP, 0.50mm pitch TSSOP

and 0.40mm pitch TVSOP packages

–

ForA-to-Bdata flow,the device operates inthe transparentmode when

LEABis high. WhenLEABis low, the Adata is latchedifCLKABis heldat

a highorlowlogiclevel.IfLEABis low,the A-bus data is storedinthe latch/

flip-floponthelow-to-hightransitionofCLKAB.OutputenableOEABisactive

low. When OEAB is low, the outputs are active. When OEAB is high, the

outputsareinthehigh-impedancestate. DataflowforBtoAissimilartothat

of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.

–

Extended commercial range of -40°C to +85°C

VCC = 3.3V ±0.3V, Normal Range

VCC = 2.7V to 3.6V, Extended Range

CMOS power levels (0.4µW typ. static)

All inputs, outputs and I/O are 5 Volt tolerant

Supports hot insertion

Drive Features for LVCH16601A:

–

High Output Drivers: ±24mA

Reduced system switching noise

Allpins canbedrivenfromeither3.3Vor5Vdevices. This featureallows

the use of this device as a translator in a mixed 3.3V/5V supply system.

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

The LVCH16601Ahas beendesignedwitha ±24mAoutputdriver.This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

DESCRIPTION

The LVCH16601A has “bus-hold” which retains the inputs’ last state

whenevertheinputgoes toahighimpedance.This prevents floatinginputs

andeliminates the needforpull-up/downresistors.

The LVCH16601A 18-bit universal bus transceiver is built using ad-

vanced dual metal CMOS technology. The LVCH16601A combines D-

typelatches andD-typeflip-flops toallowdataflowintransparent,latched

andclockedmodes.

FunctionalBlockDiagram

OEAB

CLKAB

LEAB

LEBA

CLKENBA

EXTENDED COMMERCIAL TEMPERATURE RANGE

MARCH 1999

1999 Integrated Device Technology, Inc.

DSC-4074/1

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

EXTENDEDCOMMERCIALTEMPERATURERANGE

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

PINCONFIGURATION

Symbol

Description

Max.

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

– 0.5 to +6.5

OEAB

LEAB

CLKENAB

CLKAB

B¹

(3)

VTERM

Terminal Voltage with Respect to GND

Storage Temperature

– 0.5 to +6.5

– 65 to +150

– 50 to +50

– 50

TSTG

IOUT

°C

A¹

DC Output Current

GND

A²

GND

B²

IIK

Continuous Clamp Current,

VI < 0 or VO < 0

IOK

ICC

A³

B³

Continuous Current through

±100

V^CC

B⁴

I_SS

each V_CCor GND

A⁴

A⁵

A⁶

LVC Link

NOTES:

B⁵

B⁶

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

2. V^CCterminals.

GND

A⁷

GND

B⁷

A⁸

B⁸

B⁹

SO56-1

SO56-2

SO56-3

A⁹

3. All terminals except V^CC.

A¹⁰

A¹¹

B¹⁰

B¹¹

A¹²

GND

A¹³

CAPACITANCE (T^A= +25^OC, f = 1.0MHz)

Symbol

B¹²

GND

B¹³

Parameter⁽¹⁾

Conditions

Typ. Max. Unit

CIN

Input Capacitance

VIN = 0V

4.5

A¹⁴

A¹⁵

B¹⁴

COUT

CI/O

Output

Capacitance

I/O Port

VOUT = 0V

VIN = 0V

6.5

B¹⁵

V^CC

B¹⁶

V^CC

A¹⁶

6.5

Capacitance

LVC Link

A¹⁷

B¹⁷

NOTE:

GND

1. As applicable to the device type.

GND

B¹⁸

A¹⁸

FUNCTION TABLE ^{(1, 2)}

CLKBA

OEBA

LEBA

CLKENBA

Inputs

Outputs

CLKENAB

OEAB

LEAB

CLKAB

SSOP/ TSSOP/ TVSOP

TOP VIEW

B₀⁽³⁾

PIN DESCRIPTION

Pin Names

Description

↑

B₀⁽³⁾

OEAB

OEBA

A-to-B Output Enable Input (Active LOW)

B-to-A Output Enable Input (Active LOW)

A-to-B Latch Enable Input

B₀⁽⁴⁾

LEAB

LEBA

B-to-A Latch Enable Input

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

↑ = LOW-to-HIGH Transition

2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,

LEBA, CLKBA and CLKENBA.

3. Output level before the indicated steady-state input conditions were

established.

CLKAB

CLKBA

A-to-B Clock Input

B-to-A Clock Input

A-to-B Data Inputs or B-to-A 3-State Outputs⁽¹⁾

B-to-A Data Inputs or A-to-B 3-State Outputs⁽¹⁾

A-to-B Clock Enable Input (Active LOW)

B-to-A Clock Enable Input (Active LOW)

CLKENAB

CLKENBA

NOTE:

4. Output level before the indicated steady-state input conditions were

established, provided that CLKAB was HIGH before LEAB went LOW.

1. These pins have “Bus-hold”. All other pins are standard inputs,

outputs, or I/Os.

1998 Integrated Device Technology, Inc.

DSC-123456

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

EXTENDEDCOMMERCIALTEMPERATURERANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: T = –40 C to +85 C

Symbol

Parameter

Test Conditions

Min.

Typ.⁽¹⁾

Max. Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 3.6V

1.7

—

VIL

Input LOW Voltage Level

Input Leakage Current

—

0.7

0.8

±5

IIH

VI = 0 to 5.5V

µA

IIL

IOZH

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOZL

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

VCC = 2.3V, IIN = – 18mA

VCC = 3.3V

—

– 0.7

100

—

±50

– 1.2

—

µA

Input Hysteresis

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

(2)

—

3.6 ≤ VIN ≤ 5.5V

∆ICC

Quiescent Power Supply

Current Variation

One input at VCC - 0.6V

other inputs at VCC or GND

500

µA

LVC Link

NOTES:

1. Typical values are at V^CC= 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLD CHARACTERISTICS

Symbol

Parameter⁽¹⁾

Test Conditions

Min.

Typ.⁽²⁾

Max.

Unit

IBHH

Bus-Hold Input Sustain Current

VCC = 3.0V

VCC = 2.3V

VCC = 3.6V

VI = 2.0V

VI = 0.8V

VI = 1.7V

VI = 0.7V

VI = 0 to 3.6V

– 75

—

µA

IBHL

IBHH

IBHL

Bus-Hold Input Sustain Current

Bus-Hold Input Overdrive Current

—

µA

—

IBHHO

IBHLO

—

± 500

µA

LVC Link

NOTES:

1. Pins with Bus-hold are identified in the pin description.

2. Typical values are at V^CC= 3.3V, +25°C ambient.

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

EXTENDEDCOMMERCIALTEMPERATURERANGE

OUTPUT DRIVE CHARACTERISTICS

Symbol

Parameter

Output HIGH Voltage

Test Conditions⁽¹⁾

IOH = – 0.1mA

Min.

Max.

Unit

VOH

VCC = 2.3V to 3.6V

VCC = 2.3V

VCC – 0.2

—

IOH = – 6mA

IOH = – 12mA

—

VCC = 2.3V

1.7

2.2

2.4

2.2

—

VCC = 2.7V

—

VCC = 3.0V

—

VCC = 3.0V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

Output LOW Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

0.2

0.4

0.7

0.4

0.55

IOL = 12mA

I_OL= 12mA

IOL = 24mA

V_CC= 2.7V

VCC = 3.0V

LVC Link

NOTE:

1. V^IHand V^ILmust be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the

appropriate V^CCrange. T^A= – 40°C to +85°C.

OPERATING CHARACTERISTICS, V

= 3.3V ± 0.3V, T = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

Power Dissipation Capacitance per transceiver Outputs enabled

Power Dissipation Capacitance per transceiver Outputs disabled

CL = 0pF, f = 10Mhz

CPD

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

EXTENDEDCOMMERCIALTEMPERATURERANGE

SWITCHING CHARACTERISTICS ⁽¹⁾

VCC = 2.7V

VCC = 3.3V±0.3V

Symbol

Parameter

Propagation Delay

Ax to Bx or Bx to Ax

Min.

Max.

Min.

Max.

Unit

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

5.4

4.6

—

Propagation Delay

LEBA to Ax, LEAB to Bx

Propagation Delay

CLKBA to Ax, CLKAB to Bx

Output Enable Time

OEBA to Ax, OEAB to Bx

Output Disable Time

OEBA to Ax, OEAB to Bx

Set-up Time, HIGH or LOW

Ax to CLKAB, Bx to CLKBA

Hold Time HIGH or LOW

Ax after CLKAB, Bx after CLKBA

6.2

6.3

6.8

5.2

5.3

5.6

5.2

—

1.5

—

1.5

—

0.8

tSU

Set-up Time

HIGH or LOW

Clock

LOW

Clock

HIGH

Ax to LEAB,

Bx to LEBA

tSU

Set-up Time,

CLKENAB to CLKAB

Set-up Time,

CLKENBA to CLKBA

Hold Time, HIGH or LOW

Ax after LEAB, Bx after LEBA

Hold Time,

CLKENAB after CLKAB

Hold Time,

CLKENBA after CLKBA

LEAB or LEBA Pulse Width

HIGH

2.1

1.8

0.5

2.1

1.8

0.5

CLKAB or CLKBA Pulse Width

HIGH or LOW

—

(2)

tSK(o) Output Skew

500

—

NOTES:

1. See test circuits and waveforms. T^A= – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

EXTENDEDCOMMERCIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

PROPAGATIONDELAY

TESTCONDITIONS

VIH

(1)

(2)

VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V

SAME PHASE

Symbol

Unit

INPUT TRANSITION

VLOAD

2 xVcc

Vcc

tPHL

tPLH

VOH

VIH

2.7

1.5

300

2.7

1.5

300

OUTPUT

VCC / 2

150

VOL

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

TEST CIRCUITS FOR ALL OUTPUTS

ENABLEANDDISABLETIMES

DISABLE

ENABLE

VLOAD

VIH

VCC

CONTROL

INPUT

Open

GND

t^PZL

tPLZ

500Ω

VIN

VLOAD/2

VOUT

VLOAD/2

OUTPUT

NORMALLY

LOW

Pulse ^{(1, 2)}

Generator

SWITCH

CLOSED

D.U.T.

VLZ

VOL

tPHZ

tPZH

VOH

VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

DEFINITIONS:

LVC Link

C^L= Load capacitance: includes jig and probe capacitance.

R^T= Termination resistance: should be equal to Z^OUTof the Pulse

Generator.

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

NOTE:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t^F≤ 2.5ns; t^R≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; t^F≤ 2ns; t^R≤ 2ns.

SET-UP, HOLD, AND RELEASE TIMES

VIH

DATA

INPUT

SWITCHPOSITION

tSU

Test

Switch

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other tests

VLOAD

tREM

VIH

ASYNCHRONOUS

CONTROL

GND

Open

VIH

V^T

SYNCHRONOUS

CONTROL

tSU

LVC Link

OUTPUT SKEW - tsk (x)

LVC Link

VIH

PULSEWIDTH

INPUT

tPLH1

tPHL1

VOH

LOW-HIGH-LOW

PULSE

OUTPUT 1

OUTPUT 2

VOL

tSK (x)

VOH

HIGH-LOW-HIGH

PULSE

VOL

LVC Link

tPLH2

tPHL2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For t^SK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

EXTENDEDCOMMERCIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

LVC

Device Type Package

XXXX

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package (SO56-1)

Thin Shrink Small Outline Package (SO56-2)

Thin Very Small Outline Package (SO56-3)

18-Bit Universal Bus Transceiver with 3-State Outputs

Double-Density with Resistors, ±24mA

601A

Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74LVCH16601APF8 [IDT]

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