IDT74LVCR16543APA [IDT]

Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56;


型号：	IDT74LVCR16543APA
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56 输入元件光电二极管输出元件逻辑集成电路
文件：	总6页 (文件大小：129K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCR16543A

EXTENDEDCOMMERCIALTEMPERATURERANGE

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

3.3V CMOS 16-BIT

IDT74LVCR16543A

REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS

AND 5 VOLT TOLERANT I/O

ADVANCE

INFORMATION

DESCRIPTION:

FEATURES:

tSK(0)

(Output Skew) < 250ps

–

Typical

The LVCR16543A16-bitregisteredtransceiveris builtusingadvanced

dualmetalCMOStechnology. The LVCR16543Adevice canbe usedas

two independent 8-bit transceivers or one 16-bit transceiver. Separate

latch-enable (LEAB orLEBA)andoutput-enable (OEAB orOEBA)inputs

are provided for each register to permit independent control in either

direction of data flow. The A-to-B enable (CEAB) must be low in order to

enterdata fromAortooutputdata fromB.IfCEAB is lowandLEABis low,

the A-to-Blatches are transparent;a subsequentlow-to-hightransitionof

LEAB puts the Alatches inthe storage mode. WithCEAB andOEABboth

low,the3-stateBoutputsareactiveandreflectthedatapresentattheoutput

oftheAlatches.DataflowfromBtoAissimilar,butrequiresusingtheCEBA,

LEBA,andOEBAinputs.Toensurethehigh-impedancestateduringpower

uporpowerdown,OE shouldbe tiedtoVccthrougha pullupresistor;the

minimumvalueoftheresistorisdeterminedbythecurrentsinkingcapability

of the driver.

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

0.635mm pitch SSOP, 0.50mm pitch TSSOP

and 0.40mm pitch TVSOP packages

Extended commercial range of -40°C to +85°C

VCC = 3.3V ±0.3V, Normal Range

VCC = 2.7V to 3.6V, Extended Range

CMOS power levels (0.4µW typ. static)

All inputs, outputs and I/O are 5 Volt tolerant

Supports hot insertion

–

Drive Features for LVCR16543A:

–

Balanced Output Drivers: ±12 mA

Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

Inputs canbe drivenfromeither3.3Vor5Vdevices.This feature allows

the use of this device as a translator in a mixed 3.3V/5V supply system.

TheLVCR16543Aisideallysuitedfordrivinghighcapacitanceloadsand

low-impedance backplanes. The outputbuffers are designedwithpower

off disable capability to allow “live insertion” of boards when used as

backplane drivers.

The LVCR16543Ahas beendesignedwitha ±12mAoutputdriver.This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

FUNCTIONALBLOCKDIAGRAM

2OEBA

1OEBA

2CEBA

1CEBA

2LEBA

2OEAB

1LEBA

1OEAB

2CEAB

2LEAB

1CEAB

1LEAB

2A1

1A1

2B1

1B1

TO SEVEN OTHER CHANNELS

EXTENDED COMMERCIAL TEMPERATURE RANGE

OCTOBER 1999

1999 Integrated Device Technology, Inc.

DSC-4601/-

IDT74LVCR16543A

EXTENDEDCOMMERCIALTEMPERATURERANGE

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Max.

Unit

Terminal Voltage with Respect to GND

Storage Temperature

– 0.5 to +6.5

– 65 to +150

1OEAB

1OEBA

LEBA

°C

1LEAB

1CEAB

I_OUT

DC Output Current

– 50 to +50

– 50

1CEBA

GND

Continuous Clamp Current,

VI < 0 or VO < 0

IOK

ICC

1A1

1A2

V^CC

1A3

1B1

1B2

V^CC

Continuous Current through

±100

ISS

each VCC or GND

LVC Link

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

1A4

1A5

1B4

1B5

GND

1B6

1A7

1A8

1B7

1B8

SO56-1

SO56-2

SO56-3

2A1

2A2

2A3

2B1

2B2

2B3

CAPACITANCE (T^A= +25^oC, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

Typ. Max. Unit

GND

CIN

Input Capacitance

VIN = 0V

4.5

2A4

2A5

2A6

V^CC

2A7

2A8

2B4

2B5

2B6

V^CC

2B7

2B8

COUT

CI/O

Output

Capacitance

I/O Port

VOUT = 0V

VIN = 0V

6.5

Capacitance

LVC Link

NOTE:

1. As applicable to the device type.

GND

2CEBA

2LEBA

2CEAB

2LEAB

2OEBA

OEAB

FUNCTION TABLE ^(1,2)

SSOP/ TSSOP/ TVSOP

TOP VIEW

Inputs

Latch Status

Output Buffers

xCEAB xLEAB xOEAB

xAx to xBx

xBx

Storing

High Z

Storing

Transparent

Storing

Current A Inputs

Previous⁽³⁾A Inputs

High Z

PIN DESCRIPTION

Pin Names

xOEAB

xOEBA

xCEAB

xCEBA

xLEAB

xLEBA

xAx

Description

Transparent

Storing

A-to-B Output Enable Inputs (Active LOW)

B-to-A Output Enable Inputs(Active LOW)

A-to-B Enable Inputs (Active LOW)

High Z

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

2. A-to-B data flow shown; B-to-A flow control is the same, except using

xCEBA, xLEBA and xOEBA.

B-to-A Enable Inputs (Active LOW)

A-to-B Latch Enable Inputs (Active LOW)

B-to-A Latch Enable Inputs (Active LOW)

A-to-B Data Inputs or B-to-A 3-State Outputs

B-to-A Data Inputs or A-to-B 3-State Outputs

3. Before xLEAB LOW-to-HIGH Transition

xBx

1998 Integrated Device Technology, Inc.

DSC-123456

IDT74LVCR16543A

EXTENDEDCOMMERCIALTEMPERATURERANGE

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: T^A= –40^OC to +85^OC

Symbol

Parameter

Test Conditions

Min.

Typ.⁽¹⁾

Max. Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 3.6V

1.7

—

VIL

Input LOW Voltage Level

Input Leakage Current

—

0.7

0.8

±5

IIH

VI = 0 to 5.5V

µA

IIL

IOZH

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOZL

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

VCC = 2.3V, IIN = – 18mA

VCC = 3.3V

—

– 0.7

100

—

±50

– 1.2

—

µA

Input Hysteresis

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

(2)

—

3.6 ≤ VIN ≤ 5.5V

∆ICC

Quiescent Power Supply

Current Variation

One input at VCC - 0.6V

other inputs at VCC or GND

500

µA

LVC Link

NOTES:

1. Typical values are at V^CC= 3.3V, +25°C ambient.

2. This applies in the disabled state only.

OUTPUT DRIVE CHARACTERISTICS

Symbol

Parameter

Output HIGH Voltage

Test Conditions⁽¹⁾

Min.

Max.

Unit

VOH

VCC = 2.3V to 3.6V

VCC = 2.3V

IOH = – 0.1mA

IOH = – 4mA

IOH = – 6mA

IOH = – 4mA

IOH = – 8mA

IOH = – 6mA

IOH = – 12mA

IOL = 0.1mA

IOL = 4mA

VCC – 0.2

1.9

1.7

2.2

—

VCC = 2.7V

VCC = 3.0V

—

2.4

—

VOL

Output LOW Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.55

0.4

0.6

0.55

0.8

—

IOL = 6mA

—

VCC = 2.7V

VCC = 3.0V

IOL = 4mA

—

IOL = 8mA

—

IOL = 6mA

—

IOL = 12mA

—

LVC Link

NOTE:

1. V^IHand V^ILmust be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the

appropriate V^CCrange. T^A= – 40°C to +85°C.

IDT74LVCR16543A

EXTENDEDCOMMERCIALTEMPERATURERANGE

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

OPERATING CHARACTERISTICS, V

= 3.3V ± 0.3V, T = 25°C

Symbol

Parameter

Test Conditions

CL = 0pF, f = 10Mhz

Typical

Unit

CPD

Power Dissipation Capacitance per transceiver Outputs enabled

Power Dissipation Capacitance per transceiver Outputs disabled

CPD

SWITCHING CHARACTERISTICS ⁽¹⁾

_VCC= 2.7V

CC = 3.3V±0.3V

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPZH

tPZL

tPHZ

tPLZ

tPHZ

tPLZ

tSU

Propagation Delay

xAx to xBx or xBx to xAx

Propagation Delay

xLEBA to xAx, xLEAB to xBx

Output Enable Time

xCEBA or xCEAB to xAx or xBx

Output Enable Time

xOEBA or xOEAB to xAx or xBx

Output Disable Time

xCEBA or xCEAB to xAx or xBx

Output Disable Time

xOEBA or xOEAB to xAx or xBx

Set-up Time, data before CE↑

1.5

7.5

6.5

—

tSU

Set-up Time, data before LE↑, CE LOW

Hold Time, data after CE↑

—

Hold Time, data after LE↑, CE LOW

xLEBA or xLEAB Pulse Width LOW

—

(2)

tSK(o)

Output Skew

—

500

NOTES:

1. See test circuits and waveforms. T^A= – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCR16543A

EXTENDEDCOMMERCIALTEMPERATURERANGE

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

TESTCIRCUITSANDWAVEFORMS:

PROPAGATIONDELAY

TESTCONDITIONS

Symbol

(1)

(2)

VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V

Unit

VLOAD

2 xVcc

Vcc

VIH

SAME PHASE

INPUT TRANSITION

VIH

2.7

1.5

300

2.7

1.5

300

tPHL

VCC / 2

150

tPLH

VOH

OUTPUT

VLZ

VHZ

VOL

150

VIH

LVC Link

OPPOSITE PHASE

INPUT TRANSITION

LVC Link

TEST CIRCUITS FOR ALL OUTPUTS

VLOAD

ENABLEANDDISABLETIMES

VCC

Open

GND

DISABLE

ENABLE

VIH

500Ω

CONTROL

INPUT

VIN

VOUT

Pulse ^{(1, 2)}

Generator

tPZL

tPLZ

D.U.T.

VLOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

VOL+VLZ

VOL

tPHZ

tPZH

VOH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

VOH-VHZ

DEFINITIONS:

C^L= Load capacitance: includes jig and probe capacitance.

R^T= Termination resistance: should be equal to Z^OUTof the Pulse

Generator.

LVC Link

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t^F≤ 2.5ns; t^R≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; t^F≤ 2ns; t^R≤ 2ns.

SWITCHPOSITION

SET-UP, HOLD, AND RELEASE TIMES

Test

Switch

VIH

DATA

INPUT

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other tests

VLOAD

tSU

VIH

TIMING

INPUT

GND

Open

tREM

VIH

ASYNCHRONOUS

CONTROL

LVC Link

VIH

SYNCHRONOUS

CONTROL

OUTPUT SKEW - tsk (x)

tSU

LVC Link

VIH

INPUT

PULSEWIDTH

tPLH1

tPHL1

VOH

LOW-HIGH-LOW

PULSE

OUTPUT 1

OUTPUT 2

VOL

tSK (x)

VOH

HIGH-LOW-HIGH

PULSE

VOL

LVC Link

tPLH2

tPHL2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For t^SK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCR16543A

EXTENDEDCOMMERCIALTEMPERATURERANGE

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

ORDERINGINFORMATION

Device Type Package

XXXX

IDT

LVC

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package (SO56-1)

Thin Shrink Small Outline Package (SO56-2)

Thin Very Small Outline Package (SO56-3)

16-Bit Registered Transceiver with

3-State Outputs and 5 Volt Tolerant I/O

543A

R16

Double-Density with Resistors, ±12mA

Blank

No Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

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Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74LVCR16543APA [IDT]

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