IDT79RC64T575-333DP8 [IDT]
RISC Microprocessor, 64-Bit, 333MHz, PQFP208, 28 X 28 X 3.40 MM, PLASTIC, QFP-208;
| 型号： | IDT79RC64T575-333DP8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | RISC Microprocessor, 64-Bit, 333MHz, PQFP208, 28 X 28 X 3.40 MM, PLASTIC, QFP-208 时钟 外围集成电路 |
| 文件： | 总27页 (文件大小：645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RC64574™
RC64575™
Advanced 64-bit
Microprocessors
Product Family
Preliminary Information*
◆
◆
Big- or Little-endian capability
RC5000 compatible memory management
ꢀꢁꢂꢃꢄꢅꢁꢆ
◆
High-performance 64-bit embedded Microprocessor
–
On-chip 48-entry, 96-page TLB, for advanced operating
system support
–
–
–
–
–
333MHz operating frequency
>440 Dhrystone MIPS performance
666MFLOPS/s floating-point performance
Up to 125 million multiply accumulate per second (MAC/s)
MIPS-IV Instruction Set Architecture (ISA), with integer DSP
and 3-operand integer multiply extensions
–
Compatible with major operating systems:
Windows®CE, VxWorks, and others
◆
Bus compatible with IDT 64-bit microprocessor families
–
Pipeline runs at 2 to 8 times the bus frequency
Bus speeds to 125MHz
32-bit bus option, for lower cost systems
Enhanced timing protocol for SyncDRAM systems (compatible
with IDT79RC64474/475)
–
Limited dual-issue microarchitecture
–
–
–
◆
Compatible with RC4640 and RC32364 DSP extensions
–
–
–
DSP Extensions, for consumer applications
2-cycle repeat rate, on atomic Multiply-add
Multiply-subtract (MSUB) support, for complex number
processing
◆
◆
RC64574:
–
–
–
32-bit SysAd bus, for low-cost systems
Pin compatible with RC4640 and RC64474
128-pin QFP package
–
Count-leading-zero/one support, for string searches and
normalization
◆
High-performance on-chip cache subsystem
RC64575:
–
32kB, two-set associative instruction cache (I-cache)
32kB, two-set associative data cache (D-cache)
Write-through and write-back data cache operations
High-performance cache-ops, bandwidth management
–
–
–
64-bit SysAd bus interface
Pin compatible with RC4650 and RC64475
208-pin QFP package
–
–
–
◆
◆
JTAG Boundary Scan Interface
◆
◆
I-cache and D-cache locking capability (per line), provides
improved real-time support
2.5V operation with 3.3V tolerant I/O
Joint TLB on-chip, for virtual-to-physical address mapping
ꢇꢈꢉꢊꢋꢌꢍꢎꢂꢏꢅꢂꢐꢌ
PLL
64-bit
Integer
Execution Unit
666 MFIOPS
IEEE 1284
Floating-Point
Accelerator
DSP
Accelerator
RC5000
Compatible
System Control
Coprocessor
Dual-Is sue Instruction Fetch Unit
Primary Cache Controller
48-entry
96-page
TLB
32kB
32kB
2 set-associative
Data
2 s et-associative
Instruction
Cache
Cache
(Lockable)
(Lockable)
64-bit/32-bit
RC64474/475 Compatible
System Interface
ClkIn
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.
1 of 27
October 14, 1999
DSC 5607
1999 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
ꢔꢕꢆꢃꢅꢄꢊꢃꢎꢉꢕꢌꢔꢆꢆꢄꢁꢌꢖꢁꢊꢗꢂꢕꢎꢆꢐ
ꢍꢁꢑꢎꢊꢁꢌꢒꢑꢁꢅꢑꢎꢁꢓ
The RC64574 and RC64575 are limited dual-issue super-scalar
machines that use a traditional 5-stage integer pipeline, as shown in the
pipeline diagram on Page 3. For multi-issue operations, these devices
recognize the following two general classes of instructions:
IDT’s 79RC64574/575 processors serve a wide range of perfor-
mance-critical embedded applications that include high-end internet-
working systems, digital set-top boxes, web browsers, color printers,
and graphics terminals.
◆
Floating-point ALU
The RC64574/575 allow a socket compatible upgrade path for IDT’s
RC4640/50 and RC64474/475 processors. This unprecedented upgrad-
ability allows a 2:1 range of frequencies; 4:1 range of cache size; 15:1
range of floating-point; and 4:1 range of DSP performance in a single
socket.
◆
All others
Such a broad separation of instruction classes insure that there are
no data dependencies to restrict multi-issue performance. As they are
brought on-chip, these instruction classes are pre-decoded by the
RC64574/575, and the class information is then stored in the instruction
cache. Assuming there are no pending resource conflicts, the devices
can issue one instruction per class per pipeline clock cycle.
With special emphasis on system bandwidth, floating- point and DSP
operations, the RC64574/575 have been optimized for high-perfor-
mance applications through the integration of high-performance compu-
tational units and a high-performance memory hierarchy. The result is a
low-cost CPU that is capable of more than 400 Dhrystone MIPS.
Through the RC64574/64575 processors IDT offers:
However, longer latency resources—in either the floating-point ALU
(for example, division or square root instructions) or integer unit (such as
multiply)—can restrict the issue of instructions. Note that these proces-
sors do not perform out-of-order or speculative execution; instead, the
pipeline slips until the required resource becomes available.
◆
High-performance upgrade paths to existing embedded
customers in the internetworking, office automation and
visualization markets.
On dual-issue instruction pairs, there are no alignment restrictions,
and the RC64574/575 fetch two instructions from the cache per cycle.
Thus, for optimal performance, compilers should attempt to align branch
targets to allow dual-issue on the first target cycle, because the instruc-
tion cache only performs aligned fetches.
◆
Significant floating-point performance improvements over
currently available, moderately priced MIPS CPUs.
◆
Performance improvements through the use of the MIPS-IV
ISA.
◆
High-performance DSP acceleration
1.
Detailed system operation information is provided in the RC64574/RC64575
user’s manual.
64-bit RISCore4000
w/ DSP extensions
64-bit RISCore4000
>330MIPS
64-bit RISCore5000
>440MIPS
64-bit RISCore4000
w/ DSP extensions
64-bit RISCore4000
>330MIPS
64-bit RISCore5000
>440MIPS
CPU
>350MIPS
>350MIPS
Performance
FPA
89 mflops, single pre-
cision only
125 mflops, single and
double precision
666 mflops, single and
double precision
89 mflops, single pre-
cision only
125 mflops, single
and double precision
666 mflops, single
and double precision
8kB/8kB, 2-way, lock-
able by set
16kB/16kB, 2-way,
lockable by set
32kB/32kB, 2-way,
lockable by set
8kB/8kB, 2-way, lock-
able by set
16kB/16kB, 2-way,
lockable by set
32kB/32kB, 2-way,
lockable by set
Caches
32-bit
32-bit, Superset pin
compatible w/RC4640
32-bit, Superset pin
compatible w/RC4640,
RC64474
32- or 64-bit
32-or 64-bit, Super-
set pin compatible w/
RC4650
32-or 64-bit, Super-
set pin compatible w/
RC4650, RC64475
External Bus
3.3V
3.3V
2.5V
3.3V
3.3V
2.5V
Voltage
100-267 MHz
128 PQFP
Base-Bounds
180-250 MHz
128 QFP
200-333 MHz
128 QFP
100-267 MHz
208 QFP
180-250 MHz
208 QFP
250-333 MHz
208 QFP
Frequencies
Packages
MMU
96 page TLB
96 page TLB
Base-Bounds
96 page TLB
96 page TLB
Cache locking, on-
chip MAC, 32-bit
external bus
Cache locking, JTAG,
syncDRAM mode, 32-
bit external bus
Cache locking, JTAG,
syncDRAM mode, 32-
bit external bus
Cache locking, on-
chip MAC, 32-bit & 64
bit bus option
Cache locking, JTAG,
syncDRAM mode, 32-
64- bit bus option
Cache locking, JTAG,
syncDRAM mode, 32-
64- bit bus option
Key Features
Table 1 RISCore4000/RISCore5000 Processor Family
2 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
Load and branch latencies are minimized by the short pipeline of the
RC64574/575, and the caches contain special logic that will allow any
combination of loads and stores to execute in back-to-back cycles
without requiring pipeline slips or stalls, assuming the operation does
not miss in the cache.
ꢔꢕꢆꢃꢅꢄꢊꢃꢎꢉꢕꢌꢘꢁꢃꢌꢙꢅꢊꢗꢎꢃꢁꢊꢃꢄꢅꢁ
The RC64574/575 implement a superset of the MIPS-IV 64-bit ISA,
including CP1 and CP1X functional units and their instruction set. Both
32- and 64-bit data operations are performed by utilizing thirty-two
general purpose 64-bit registers (GPR) that are used for integer opera-
tions and address calculation. The complete on-chip floating-point co-
processor (CP1)—which includes a floating-point register file and execu-
tion units—forms a “seamless” interface, decoding and executing
instructions in parallel with the integer unit.
ꢚꢉꢐꢛꢄꢃꢂꢃꢎꢉꢕꢂꢈꢌꢜꢕꢎꢃꢆ
The RC64574/575 implement a full, single-cycle 64-bit arithmetic
logic unit (ALU), for Integer ALU functions other than multiply and
divide. Bypassing is used to support back-to-back ALU operations at the
full pipeline rate, without requiring stalls for data dependencies.
CP1’s floating-point execution units support both single and
double precision arithmetic—as specified in the IEEE Standard 754—
and are separated into a multiply unit and a combined add/convert/
divide/square root unit. Overlap of multiplies and add/subtract is
supported, and the multiplier is partially pipelined, allowing the initiation
of a new multiply instruction every fourth pipeline cycle. The floating-
point register file is made up of thirty-two 64-bit registers. The floating-
point unit can take advantage of the 64-bit wide data cache and issue a
co-processor load or store doubleword instruction in every cycle.
To allow the longer latency operations to run in parallel with other
operations, the Integer Multiply/Divide unit of the RC64574/ 575 is
separated from the primary ALU. The pipeline stalls only if an attempt to
access the HI or LO registers is made before an operation completes.
The Floating-point ALU unit is responsible for all of the CP1/CP1X
ALU operations—other than DIV/SQRT operations—and is pipelined to
allow a single-cycle repeat rate for single-precision operations.
The system control coprocessor (CP0) registers are also incorpo-
rated on-chip and provide the path through which the virtual memory
system’s page mapping is examined and changed, exceptions are
handled, and any operating mode selections are controlled. A secure
user processing environment is provided through the user, supervisor,
and kernel operating modes of virtual addressing to system software.
Bits in a status register determine which of these modes is used.
The Floating-point DIV/SQRT unit is separated from the floating-
point ALU, to ensure that these longer latency operations do not prevent
the issue of other floating-point operations. Separate logical units are
also provided on the RC64574/575 to implement load, store, and branch
operations.
Intended to enhance the performance of DSP algorithms such as fast
fused multiply-adds, multiply-subtracts and three operand multiply oper-
ations, new instructions have been added over and above the MIPS-IV
ISA.
The integer instruction execution speed is tabulated—in number of
pipeline clocks—as follows:
ꢘꢝꢆꢃꢁꢐꢌꢔꢕꢃꢁꢅꢞꢂꢊꢁꢆ
The RC64575 supports a 64-bit system interface that is pin and
bus compatible with the RC4650 and RC64475 system interface. The
system interface consists of a 64-bit Address/Data bus with eight parity-
check bits and a 9-bit command bus.
Load
2
1
Store
2
1
MULT/MULTU
DMULT/DMULTU
DIV/DIVU
4
3
During 64-bit operation, RC64575 system address/data (SysAD)
transfers are protected with an 8-bit parity check bus, SysADC. When
initialized for 32-bit operation, the RC64575’s SysAD can be viewed as a
32-bit multiplexed bus that is protected by four parity-check bits.
6
5
36
68
3
36
68
2
DDIV/DDIVU
MAD/MADU
MSUB/MSUBU
Other Integer ALU
Branch
The RC64574 supports a 32-bit system interface that is pin and
bus compatible with the RC4640 and RC64474. During 32-bit operation,
SysAD transfers are performed on a 32-bit multiplexed bus (SysAD
31:0) that is protected by 4 parity check bits (SysADC 6:0).
4
3
1
1
Writes to external memory—whether they are cache miss write-
backs, stores to uncached or write-through addresses—use the on-chip
write buffer. The write buffer holds a maximum of four 64-bit addresses
and 64-bit data pairs. The entire buffer is used for a data cache write-
back and allows the processor to proceed in parallel with memory
updates.
2
2
Jump
2
2
Table 2 Integer Instruction Execution Speed
To insure that the maximum frequency of operation is not limited by
the speed of the multiplier unit, a “fast multiply” disable reset mode bit
(see Table 2) is featured. When this bit is asserted, each multiply opera-
tion shown in Table 1 has its latency and repeat rate increased by one
cycle.
Included in the system interface are six handshake signals:
RdRdy*, WrRdy*, ExtRqst*, Release*, ValidOut*, and ValidIn*; six inter-
rupt inputs, and a simple timing specification that is capable of trans-
3 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
ferring data between the processor and memory at a peak rate of
1000MB/sec. A boot-time selectable option to run the system interface
as 32-bits wide—using basically the same protocols as the 64-bit
system—is also supported.
11
TimerIntEn
Timer interrupt settings:
0: Enable Timer Interrupt on Int(5)
1: Disable Timer Interrupt on Int(5)
A boot-time mode control interface initializes fundamental
processor modes and is a serial interface that operates at a very low
frequency (SysClock divided by 256). This low-frequency operation
allows the initialization information to be kept in a low-cost EPROM;
alternatively, the twenty-or-so bits could be generated by the system
interface ASIC or a simple PAL. The boot-time serial stream is shown in
Table 3.
12
System Interface Interface bus width control settings:
Bus Width.
0: 64-bit system interface
1: 32-bit system interface
13:14
Drv_Out
Bit 14 is MSB
Slew rate control of the output drivers:
10: 100% strength (fastest)
11: 83% strength
00: 67% strength
01: 50% strength (slowest)
15:17
Write address to From 0 to 7 SysClk cycles:
0
Reserved
Must be set to 0.
write data delay. 0: AD...
1: AxD...
1:4
Transmit-data-pat- 64-bit bus width:
tern.
Bit 4 is MSB
2: AxxD...
3: AxxxD...
4: AxxxxD...
5: AxxxxxD...
6: AxxxxxxD...
7: AxxxxxxxD...
0: DDDD
1: DDxDDx
2: DDxxDDxx
3: DxDxDxDx
4: DDxxxDDxxx
5: DDxxxxDDxxxx
6: DxxDxxDxxDxx
7: DDxxxxxxDDxxxxxx
8: DxxxDxxxDxxxDxxx
9-15: Reserved. Must not be selected.
18
19
Reserved
User must select ‘0’
Extend
Multiplication
Repeat Rate.
Initial setting of the “Fast Multiply” bit.
0: Enable Fast Multiply
1: Do not Enable Fast Multiply
32-bit bus width:
0: WWWWWWWW
1: WWxWWxWWxWWx
Note: For pipeline speeds >250MHz, this bit must
be set to ‘1’.
2: WWxxWWxxWWxxWWxx
3: WxWxWxWxWxWxWxWx
20:24
25:26
Reserved
System
User must select ‘0’
Software visible in processorConfig[21:20]
4: WWxxxWWxxxWWxxxWWxxx
5: WWxxxxWWxxxxWWxxxxWWxxxx
6: WxxWxxWxxWxxWxxWxxWxxWxx
7: WWxxxxxxWWxxxxxxWWxxxxxxWWxxxxxx
8: WxxxWxxxWxxxWxxxWxxxWxxxWxxxWxxx
9-15: Reserved. Must not be selected.
configuration iden- 0: Config[21:20] = Mode Bit [25:26]
tifier.
27:256 Reserved
User must select ‘0’
Table 3 Boot-time Mode Stream (Page 2 of 2)
The clocking interface allows the CPU to be easily mated with
external reference clocks. The CPU input clock is the bus reference
clock and can be between 33 and 125MHz. An on-chip phase-locked-
loop (PLL) generates the pipeline clock (PClock) through multiplication
of the system interface clock by values of 2,3,4,5,6,7 or 8, as defined at
system reset. This allows the pipeline clock to be implemented at a
significantly higher frequency than the system interface clock. The
RC64574/575 support both single data (one byte through full CPU bus
width) and 8-word block transfers on the SysAD bus.
5:7
PClock-to-SysClk- 0: 2
Ratio.
1: 3
Bit 7 is MSB
2: 4
3: 5
4: 6
5: 7
6: 8
7: Reserved
8
Endianness
0: Little endian
1: Big endian
The RC64574/575 implement additional write protocols that
double the effective write bandwidth. The write re-issue has a repeat
rate of 2 cycles per write. Pipelined writes have the same 2-cycle per
write repeat rate, but can issue an additional write after WrRdy* de-
asserts.
9:10
Non-block write
Mode. Bit 10 is
MSB
00: R4400 compatible
01: Reserved
10: Pipelined-Write-Mode
11: Write-Reissue-Mode
Table 3 Boot-time Mode Stream (Page 1 of 2)
4 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
To lock critical sections of code and/or data into the caches for quick
access, a per line “cache locking” feature has been implemented.
Once enabled, a cache is said to be locked when a particular piece of
code or data is loaded into the cache and that cache location will not be
selected later for refill by other data.
Choosing a 32- or 64-bit wide system interface dictates whether a
cache line block transaction requires 4 double word data cycles or 8
single word cycles as well as whether a single data transfer—larger than
4 bytes—must be divided into two smaller transfers.
As shown in Table 3, the bus delay can be defined as 0 to 7
SysClock cycles and is activated and controlled through mode bit
(17:15) settings selected during the reset initialization sequence. The
‘000’ setting provides the same write operations timing protocol as the
RC4640, RC4650, and RC5000 processors.
ꢉꢓꢁꢅꢌꢖꢂꢕꢂꢏꢁꢐꢁꢕꢃ
Executing the WAIT instruction enables the processor to enter
Standby mode. The internal clocks will shut down, thus freezing the
pipeline. The PLL, internal timer, and some of the input pins (Int[5:0]*,
NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. Once in
Standby Mode, any interrupt, including the internally generated timer
interrupt, will cause the CPU to exit Standby Mode.
To facilitate discrete interface to SyncDRAM, the RC64574/575 bus
interface is enhanced during write cycles with a programmable delay
that is inserted between the write address and the write data (for both
block and non-block writes).
Board-level testing during Run-Time mode is facilitated through the
full JTAG boundary scan facility. Five pins—TDI, TDO, TMS, TCK,
TRST*—have been incorporated to support the standard JTAG inter-
face.
!ꢗꢁꢅꢐꢂꢈꢌꢚꢉꢕꢆꢎ"ꢁꢅꢂꢃꢎꢉꢕꢆ
The RC64574 is packaged in a 128-pin QFP footprint package and
uses a 32-bit external bus, offering the ideal combination of 64-bit
processing power and 32-bit low-cost memory systems. The RC64575
is packaged in a 208-pin QFP footprint package and uses the full 64-bit
external bus. The RC64575 is ideal for applications requiring 64-bit
performance and 64-bit external bandwidth.
The RC64574/575 devices offer a direct migration path for designs
that are based on IDT’s RC4640/RC4650 and RC64474/RC64475
processors2, through full pin and socket compatibility. Full 64-bit-family
software and bus protocol compatibility ensures the RC64574/575
processors access to an existing market and development infrastruc-
ture, allowing quicker time to market.
Both devices are guaranteed in a case temperature range of 0° to
+85° C, for commercial temperature devices. Package type, speed
(power) of the device, and air flow conditions affect the equivalent
ambient temperature conditions that will meet these specifications.
An array of hardware and software tools is available to assist system
designers in the rapid development of RC64574/575 based systems.
This accessibility allows a wide variety of customers to take full advan-
tage of the device’s high-performance features while addressing today’s
aggressive time-to-market demands.
Using the thermal resistance from case to ambient ( CA) of the
given package, the equivalent allowable ambient temperature, TA, can
be calculated. The following equation relates ambient and case temper-
atures:
TA = TC - P * CA
where P is the maximum power consumption at hot temperature,
calculated by using the maximum ICC specification for the device.
Typical values for CA at various air flow are shown in Table 4. Note
that the RC64574/575 processor implements advanced power manage-
ment, which substantially reduces the typical power dissipation of the
device.
ꢚꢂꢊꢗꢁꢌꢖꢁꢐꢉꢅꢝ
To keep the high-performance pipeline of the RC64574/575 full and
operating efficiently, on-chip instruction and data caches have been
incorporated. Each cache has its own data path and can be accessed in
the same single pipeline clock cycle.
The 32kB two-way set associative instruction cache is virtually
indexed, physically tagged, and word parity protected. Because this
cache is virtually indexed, the virtual-to-physical address translation
occurs in parallel with the cache access, further increasing performance
by allowing both operations to occur simultaneously. The instruction
cache provides a peak instruction bandwidth of 2667MB/sec at 333MHz.
128 QFP
208 QFP
16
20
10
13
9
7
9
6
8
5
7
10
The 32kB two-way set associative data cache is byte parity
protected and has a fixed 32-byte (eight words) line size. Its tag is
protected with a single parity bit. To allow simultaneous address transla-
tion and data cache access, the D-cache is virtually indexed and physi-
cally tagged. The data cache can provide 8 bytes each clock cycle, for a
peak bandwidth of 2667MB/s.
Table 4 Thermal Resistance ( CA) at Various Airflows
2.
To ensure socket compatibility, refer to Table 8 and Table 9.
5 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
#ꢁꢑꢎꢆꢎꢉꢕꢌ$ꢎꢆꢃꢉꢅꢝ
July 22, 1999: Original data sheet.
September 9, 1999: Made several changes in JTAG Interface
section of Table 5. Added information on Pin 63 in Table 5.
October 14, 1999: Revised data in the Power Consumption tables
for RC64574 and RC64575.
This space intentionally reserved for future revisions.
ꢎꢕꢌꢍꢁꢆꢊꢅꢎꢛꢃꢎꢉꢕꢌ!ꢂ%ꢈꢁ
The following is a list of system interface pins available on the RC64574/575. Pin names ending with an asterisk (*) are active when low.
System Interface
ExtRqst*
I
External request
An external agent asserts ExtRqst* to request use of the System interface. The processor grants the request
by asserting Release*.
Release*
O
Release interface
In response to the assertion of ExtRqst* or a CPU read request, the processor asserts Release* and signals
to the requesting device that the system interface is available.
RdRdy*
WrRdy*
ValidIn*
I
I
I
Read Ready
The external agent asserts RdRdy* to indicate that it can accept a processor read request.
Write Ready
An external agent asserts WrRdy* when it can now accept a processor write request.
Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command
or data identifier on the SysCmd bus.
Table 5 Pin Descriptions (Page 1 of 3)
6 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
ValidOut*
O
Valid Output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or
data identifier on the SysCmd bus.
SysAD(63:0)
I/O
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent. In 64 bit
interface mode, during address phases only, SysAd(35:0) contains invalid address information. The remain-
ing SysAD(63:36) pins are not used. The whole 64-bit SysAD(63:0) may be used during the data transfer
phase. For all double-word accesses (read or write), the low-order 3 bits (SysAD[2:0]) will always be output as
zero during the address phase.
In 32-bit interface mode and in the RC64574, SysAD(63:32) is not used, regardless of Endianness. A 32-bit
address and data communication between processor and external agent is performed via SysAD(31:0).
SysADC(7:0)
I/O
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.
In 32-bit mode and in the RC64574, SysADC(7:4) is not used. The SysADC(3:0) contains check bits for
SysAD(31:0).
SysCmd(8:0)
SysCmdP
I/O
I/O
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
System Command Parity
A single, even-parity bit for the Syscmd bus. This signal is always driven low.
Clock/Control Interface
SysClock
I
SystemClock
The system clock input establishes the processor and bus operating frequency. It is multiplied internally by
2,3,4,5,6,7, or 8 to generate the pipeline clock (PClock).
V P
I
I
Quiet VCC for PLL
Quiet VCC for the internal phase locked loop.
CC
V P
Quiet V for PLL
SS
SS
Quiet VSS for the internal phase locked loop.
Interrupt Interface
Int*(5:0)
I
I
Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
NMI*
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
Initialization Interface
V
CCOk
I
V is OK
CC
When asserted, this signal indicates to the processor that the power supply has been above the Vcc minimum
for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the initialization
sequence.
ColdReset*
Reset*
I
I
Cold reset
This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchro-
nously with SysClock.
Reset
This signal must be asserted for any reset sequence. It can be asserted synchronously or asynchronously for
a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with
SysClock.
ModeClock
O
Boot-mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six.
Table 5 Pin Descriptions (Page 2 of 3)
7 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
ModeIn
I
Boot-mode data in
Serial boot-mode data input.
JTAG Interface
TDI
I
JTAG Data In
On the rising edge of TCK, serial input data are shifted into either the Instruction register or Data register,
depending on the TAP controller state. An external pull-up resistor is required.
TDO
O
I
JTAG Data Out
On the falling edge of TCK, the TDO is serial data shifted out from either the instruction or data register. When
no data is shifted out, the TDO is tri-stated (high impedance).
TCK
JTAG Clock Input
An input test clock used to shift into or out of the boundary-scan register cells. TCK is independent of the sys-
tem and processor clock with nominal 40-60% duty cycle.
TMS
I
JTAG Command Select
The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is
sampled on the rising edge of TCK. An external pull-up resistor is required.
TRST*
I
JTAG Reset
The TRST* pin is an active-low signal used for asynchronous reset of the debug unit, independent of the pro-
cessor logic. During normal CPU operation, the JTAG controller will be held in the reset mode, asserting this
active low pin.
When asserted low, this pin will also tristate the TDO pin. An external pull-down resistor is required.
JTAG32*
I
I
JTAG 32-bit scan
This pin is used to control length of the scan chain for SysAD (32-bit or 64-bit) for the JTAG mode. When set
to Vss, 32-bit bus mode is selected. In this mode, only SysAD(31:0) are part of the scan chain. When set to
Vcc, 64-bit bus mode is selected. In this mode, SysAD(63:0) are part of the scan chain. This pin has a built-in
pull-down device to guarantee 32-bit scan, if it is left un connected.
JR_V
JTAG VCC
cc
This pin has an internal pull-down to continuously reset the JTAG controller (if left unconnected) bypassing
the TRst* pin. When supplied with Vcc, the TRst* pin will be the primary control for the JTAG reset.
Table 5 Pin Descriptions (Page 3 of 3)
8 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
&ꢉꢏꢎꢊꢌꢍꢎꢂꢏꢅꢂꢐꢌ'ꢌ#ꢚ()*+),#ꢚ()*+*
Figure 1 illustrates the direction and functional groupings for the processor signals.
64
SysAD(63:0)
SysADC(7:0)
SysClock
8
9
V P
CC
SysCmd(8:0)
SysCmdP
V P
SS
TDI
RC64574/
RC64575
Logic
VCCOK
TDO
TMS
TRST*
ColdReset*
Reset*
Symbol
ModeClock
ModeIn
TCK
JTag32*
JR_Vcc
RdRdy*
NMI*
WrRdy*
6
Int*(5:0)
ExtRqst*
Release*
ValidIn*
ValidOut*
Figure 1 Logic Symbol for RC64574/RC64575
9 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
#ꢚ()*+*ꢌ-./0ꢛꢎꢕꢌ1ꢀ ꢌ ꢂꢊꢋꢂꢏꢁꢌ ꢎꢕ0ꢉꢄꢃꢌ
Pin names followed by an asterisk (*) are active when low. For maximum flexibility and compatibility with future designs, N.C. pins should be left
floating.
1
N.C.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
JTAG32*
N.C.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
N.C.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
N.C.
2
N.C.
N.C.
N.C.
3
N.C.
N.C.
N.C.
SysAD59
ColdReset*
SysAD28
4
N.C.
N.C.
N.C.
5
N.C.
SysCmd2
SysAD36
SysAD4
SysCmd1
N.C.
6
N.C.
N.C.
V
cc
7
N.C.
N.C.
V
ss
8
N.C.
N.C.
SysAD60
Reset*
9
N.C.
V
N.C.
ss
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SysAD11
V
SysAD52
ExtRqst*
SysAD29
SysAD61
SysAD30
cc
V
SysAD35
SysAD3
ss
V
V
cc
cc
SysCmd8
SysAD42
SysAD10
SysCmd7
SysCmd0
SysAD34
V
V
ss
cc
SysAD21
SysAD53
RdRdy*
Modein
V
ss
V
SysAD62
SysAD31
SysAD63
ss
V
cc
V
SysAD2
Int5*
ss
V
SysAD22
SysAD54
V
cc
cc
SysAD41
SysAD9
SysAD33
SysAD1
V
ss
V
OK
V
cc
cc
SysCmd6
SysAD40
V
V
SysADC3
SysADC7
N.C.
ss
ss
V
Release*
SysAD23
SysAD55
NMI*
cc
V
Int4*
ss
V
SysAD32
SysAD0
Int3*
TDI
cc
SysAD8
TRst*
TCK
SysCmd5
SysADC4
SysADC0
V
cc
V
V
TMS
ss
ss
V
SysADC2
SysADC6
SysAD24
TDO
cc
V
Int2*
P
P
V
ss
cc
SysAD16
SysAD48
Int1*
V
V
ss
cc
SysCmd4
SysAD39
V
SysClock
cc
V
V
ss
cc
Table 6 RC64575 208-pin QFP Package Pin-Out (Page 1 of 2)
10 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
SysAD7
SysCmd3
85
V
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
SysAD56
SysAD25
SysAD57
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
V
ss
ss
86
V
SysADC5
SysADC1
cc
V
87
SysAD17
SysAD49
Int0*
ss
V
88
V
V
cc
cc
cc
SysAD38
SysAD6
89
V
V
ss
ss
90
SysAD18
N.C
SysAD47
SysAD15
SysAD46
ModeClock
WrRdy*
91
V
SysAD26
SysAD58
N.C.
ss
92
V
cc
SysAD37
SysAD5
93
SysAD50
ValidIn*
V
cc
94
V
V
ss
cc
V
95
SysAD19
SysAD51
V
SysAD14
SysAD45
SysAD13
SysAD44
ss
ss
V
96
SysAD27
N.C.
cc
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
97
V
ss
98
V
JR_
V
cc
cc
99
ValidOut*
SysAD20
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
V
ss
100
101
102
103
104
V
cc
SysAD12
SysCmdP
SysAD43
N.C.
N.C.
N.C.
N.C.
Table 6 RC64575 208-pin QFP Package Pin-Out (Page 2 of 2)
11 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
#ꢚ()*+)ꢌ2-/0ꢛꢎꢕꢌ ꢂꢊꢋꢂꢏꢁꢌ ꢎꢕ0ꢉꢄꢃ
N.C. pins should be left floating for maximum flexibility as well as for compatibility with future designs. An asterisk (*) identifies a pin that is active
when low.
1
JTAG32*
SysCmd2
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
V
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
V
97
V
cc
cc
cc
2
V
SysAD28
ColdReset*
SysAD27
98
V
ss
ss
3
V
SysAD13
SysAD14
99
SysAD19
ValidIn*
cc
4
V
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
ss
5
SysAD5
WrRdy*
ModeClock
SysAD6
V
V
V
ss
ss
cc
6
V
V
V
cc
cc
ss
7
SysAD15
JR_V
SysAD18
Int0*
cc
8
V
SysAD26
N.C.
ss
9
V
V
SysAD17
cc
cc
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
SysADC1
V
V
cc
ss
ss
SysCmd3
SysAD7
V
V
V
ss
ss
cc
V
SysAD25
Int1*
cc
SysCmd4
SysClock
V
SysAD16
Int2*
ss
V
V P
V
cc
cc
ss
V
V P
SysAD24
SysADC2
V
ss
cc
cc
SysADC0
SysCmd5
SysAD8
TDO
TMS
TCK
TRst*
TDI
V
ss
V
Int3*
ss
V
SysAD0
Int4*
cc
V
NMI*
cc
V
SysAD23
Release*
V
ss
cc
SysCmd6
SysAD9
V
V
ss
ss
SysADC3
V
SysAD1
Int5*
ss
V
V OK
V
cc
cc
cc
V
V
SysAD22
Modein
SysAD2
ss
ss
SysCmd7
SysAD10
SysCmd8
Vcc
V
cc
SysAD31
RdRdy*
SysAD21
V
ss
V
SysCmd0
SysAD3
ss
V
V
V
ss
cc
cc
V
SysAD30
SysAD29
Reset*
V
V
ss
cc
cc
SysAD11
SysCmdP
SysAD12
ExtRqst*
SysAD20
ValidOut*
V
ss
SysCmd1
SysAD4
V
ss
Table 7 RC64574 128-Pin Package
12 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
#ꢚ()*+)ꢌꢘꢉꢊꢋꢁꢃꢌꢚꢉꢐꢛꢂꢃꢎ%ꢎꢈꢎꢃꢝꢌꢃꢉꢌ#ꢚ())+)ꢌ3ꢌ#ꢚ)().ꢌ
The RC64574/575 is 100% pin compatible with the RC64474/475 with the supply voltage being the only difference. RC64474/475 requires a 3.3V
supply, while RC64574/575 requires a 2.5V supply.
To ensure socket compatibility between the RC64574/RC64474 and the RC4640 devices, several pin changes are required, as shown in the tables
below. Note: The RC64574/575 are 2.5V parts and as such all Vcc must be at the correct voltage for a given part.
1
N.C
JTAG32*
TDO
Yes.
Yes.
Pin has an internal pull-down, to enable 32-bit scan.
Can also be left a N.C.
48
V
Can be driven with V , if JTAG is not needed. Is tristated when
ss
ss
TRst* is low.
49
50
51
52
71
V
TMS
TCK
TRst*
TDI
Yes.
Yes.
Yes.
Yes.
Yes.
Can be driven with V if JTAG is not needed.
ss
ss
V
Can be driven with V if JTAG is not needed.
ss
ss
V
Can be driven with V if JTAG is not needed.
ss
ss
V
Can be driven with V if JTAG is not needed.
ss
ss
N.C.
JR_V
Can be left N.C. in RC64574, if JTAG is not need. If JTAG is
cc
needed, it must be driven to V .
cc
Table 8 RC64574 Socket Compatibility to RC64474 and R4640
#ꢚ()*+*ꢌꢘꢉꢊꢋꢁꢃꢌꢚꢉꢐꢛꢂꢃꢎ%ꢎꢈꢎꢃꢝꢌꢃꢉꢌ#ꢚ())+*ꢌ3ꢌ#ꢚ)(*.
53
N.C.
N.C.
JTAG32*
No Connect
No Connect
JTAG32*
Yes
In 32-bit, this pin can be left uncon-
nected because of internal pull-down.
In 64-bit, this assumes that JTAG will
not be used. If using JTAG, this pin
must be at V .
cc
150
JR_V
JR_V
Yes
In RC64475, can be left a N.C, if
cc
cc
JTAG is not need. If JTAG is needed,
it must be driven to V .
cc
180
181
182
183
184
N.C.
N.C.
N.C.
N.C.
N.C.
TDI
No Connect
No Connect
No Connect
No Connect
No Connect
TDO
TRsT*
TCK
TMS
Yes
Yes
Yes
Yes
Yes
If JTAG is not needed, can be left a
N.C.
TRsT*
TCK
TMS
TDO
If JTAG is not needed, can be left a
N.C.
If JTAG is not needed, can be left a
N.C.
If JTAG is not needed, can be left a
N.C.
TDIO
If JTAG is not needed, can be left a
N.C.
Table 9 RC64575 Socket Compatibility to RC64475 & RC4650
13 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
ꢙ%ꢆꢉꢈꢄꢃꢁꢌꢖꢂ4ꢎꢐꢄꢐꢌ#ꢂꢃꢎꢕꢏꢆ
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
V
Terminal Voltage with respect to GND
Operating Temperature (case)
Case Temperature Under Bias
Storage Temperature
–0.51 to +4.0
0 to +85
–55 to +125
–55 to +125
202
V
TERM
TC
°C
°C
°C
mA
mA
TBIAS
TSTG
I
DC Input Current
IN
IOUT
DC Output Current
503
1.
V minimum = –2.0V for pulse width less than 15ns. V should not exceed VCC +0.5 Volts.
In
IN
2.
3.
When V < 0V or V > V .
CC
IN
IN
Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
#ꢁꢊꢉꢐꢐꢁꢕ"ꢁ"ꢌꢒꢛꢁꢅꢂꢃꢎꢉꢕꢌ!ꢁꢐꢛꢁꢅꢂꢃꢄꢅꢁꢌꢂꢕ"ꢌꢘꢄꢛꢛꢈꢝꢌ5ꢉꢈꢃꢂꢏꢁ
Commercial
0 C to +85 C (Case)
0V
2.5V±5%
°
°
14 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
ꢍꢚꢌ6ꢈꢁꢊꢃꢅꢎꢊꢂꢈꢌꢚꢗꢂꢅꢂꢊꢃꢁꢅꢎꢆꢃꢎꢊꢆ
Commercial Temperature Range—RC64574/575
±
( V = 2.5V 5%; Tcase = 0°C to +85°C)
cc
1
V
—
0.1V
—
—
0.1V
—
—
0.1V
—
—
0.1V
—
|IOUT|= 20uA
|IOUT|= 4mA
OL
V
V - 0.1V
V - 0.1V
V - 0.1V
V - 0.1V
OH
cc
cc
cc
cc
V
—
0.4V
—
—
0.4V
—
—
0.4V
—
—
0.4V
—
OL
V
2.0V
–0.5V
2.0V
–0.5V
2.0V
–0.5V
2.0V
–0.5V
OH
V
0.2V
0.2V
0.2V
0.2V
cc
—
IL
cc
cc
cc
V
0.7 V
3.3V
0.7 V
3.3V
±10uA
10pF
10pF
10pF
20uA
0.7 V
3.3V
0.7 V
3.3V
—
IH
cc
cc
cc
cc
I
—
—
—
—
—
±10uA
10pF
10pF
10pF
20uA
—
—
—
—
—
—
—
—
—
—
±10uA
10pF
10pF
10pF
20uA
—
—
—
—
—
±10uA
10pF
10pF
10pF
20uA
0 ≤ VIN ≤ VCC
IN
C
—
—
IN
C
IO
Cclk
I/OLEAK
Input/Output Leakage
1.
At pipeline speeds >250MHz, the “Fast Multiply” bit must be disabled.
1
1
1
2
2
2
2
ICC
stand-
by
—
—
60 mA
—
—
60 mA
—
—
100 mA
—
—
100 mA
CL = 0pF3
CL = 50pF
2
2
2
2
120 mA
120 mA
120 mA
120 mA
2
2
2
2
2
2
2
2
active 500 mA
600 mA
550mA
700 mA
700 mA
800mA
750 mA
900mA
CL = 0pF
No SysAd
activity3
Vcc = 2.63V
2
2
2
2
2
2
2
2
550mA
650 mA
650 mA
800 mA
800mA
1000mA
850mA
1100mA
CL = 50pF
R4x00 compati-
ble writes,
TC = 25oC
Vcc = 2.63V
2
4
2
4
2
2
2
2
680 mA
850 mA
800 mA
1000 mA
950mA
1200mA
1000mA
1300mA
CL = 50pF
Pipelined writes
or write re-issue,
TC = 25oC3
Vcc = 2.63V
1.
Typical integer instruction mix and cache miss rates
15 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
2.
These are not tested. They are the results of engineering analysis and are provided for reference only
3.
Guaranteed by design.
4.
These are the specifications IDT tests to insure compliance.
1
1
2
2
2
ICC
stand-by
—
—
60 mA
—
—
60 mA
—
—
100 mA
CL = 0pF3
CL = 50pF
120 m2A
120 mA
120 mA
2
2
2
2
2
2
2
2
active,
64-bit
bus
550 mA
700 mA
700 mA
800 mA
800 mA
1000 mA
CL = 0pF
No SysAd activity3
Vcc = 2.63V
option4
2
2
2
2
2
2
800 mA
1000 mA
850 mA
1100 mA
900mA
1200mA
CL = 50pF
R4x00 compatible
writes,
TC = 25oC
Vcc = 2.63V
2
5
2
5
2
2
850 mA
1200 mA
950 mA
1300 mA
1200 mA
1500 mA
CL = 50pF
Pipelined writes or write
re-issue,
TC = 25oC3
Vcc = 2.63V
1.
Typical integer instruction mix and cache miss rates
2.
3.
4.
5.
These are not tested. They are the results of engineering analysis and are provided for reference only.
Guaranteed by design.
In 32-bit bus option, use RC64474 power consumption values.
These are the specifications IDT tests to insure compliance.
16 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
!ꢎꢐꢎꢕꢏꢌꢚꢗꢂꢅꢂꢊꢃꢁꢅꢎꢆꢃꢎꢊꢆ'#ꢚ()*+),#ꢚ()*+*
1
2
3
4
Cycle
SysClock
t
SysClk
t
SysClkLow
t
SysClkP
SysAD,SysCmd Driven
SysADC
D
D
D
t
t
DOH
t
DM
DZ
t
DO
SysAD,SysCmd Received
SysADC
D
D
D
D
t
DS
t
DH
Control Signal CPU driven
ValidOut*
t
DO
Release
*
t
DOH
Control Signal CPU received
RdRdy*
WrRdy*
ExtRqst*
ValidIn*
NMI*
t
t
DS
DH
Int*(5:0)
* = active low signal
Figure 2 System Clocks Data Setup, Output, and Hold timing
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October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
t
TCK
TCK
t5
t3
t1
t2
TDI/
TMS
tDS
tDH
TDO
TDO
TDO
t
DO
Notes to diagram:
TRST*
t1 = tTCKlow
t2 = tTCKHIGH
t3 =
t
TCKFALL
t4
t4 = T
(reset pulse width)
RST
> = 25 ns
t5 = t
TCKRise
Figure 3 Standard JTAG Timing
ꢘꢝꢆꢃꢁꢐꢌꢔꢕꢃꢁꢅꢞꢂꢊꢁꢌ ꢂꢅꢂꢐꢁꢃꢁꢅꢆ
Data Output
t
DM= Min
mode14..13 = 10
(fastest)
1.01
1.02
1.0
5
1.01
1.02
1.0
4.7
7
1.0
1.0
1.0
4.7
7
1.0
1.0
1.0
4.7
7
ns
ns
ns
tDO = Max
mode14..13 = 01
(slowest)
8
2
Data Output Hold
Data Input
tDOH
mode14..13 = 10
(fastest)
—
—
—
—
tDS
trise = 3ns
tfall = 3ns
2
—
—
2
—
—
2
—
—
2
—
—
ns
ns
tDH
1.0
1.0
1.0
1.0
1.
Guaranteed by design
2.
50 pf loading on external output signals
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October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
ꢇꢉꢉꢃ0ꢃꢎꢐꢁꢌꢔꢕꢃꢁꢅꢞꢂꢊꢁꢌ ꢂꢅꢂꢐꢁꢃꢁꢅꢆ
Mode Data Setup tDS
Mode Data Hold tDH
—
—
4
0
—
—
4
0
—
—
4
0
—
—
4
0
—
—
SysClock Cycle
SysClock Cycle
VCC
SysClock
ColdReset*
Reset*
ModeBit[9:0]
>= 64 SysClk
cycles
>= 100 ms
>= 10 ms
Figure 4 Mode Configuration Interface Reset Sequence
19 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
ꢙꢚꢌ6ꢈꢁꢊꢃꢅꢎꢊꢂꢈꢌꢚꢗꢂꢅꢂꢊꢃꢁꢅꢎꢆꢃꢎꢊꢆ
±
(V = 2.5V 5%; Tcase = 0°C to +85°C)
cc
Pipeline Clock Frequency PCLk
—
100
3
200
—
—
100
30
2
100
3
250
—
—
125
30
2
100
3
300
—
—
125
30
2
100
3
333
—
—
125
30
2
MHz
ns
System Clock HIGH
System Clock LOW
System Clock Frequency
System Clock Period
System Clock Rise Time
System Clock Fall Time
ModeClock Period
tSCHIGH
tSCLOW
Transition ≤ 3ns
Transition ≤ 3ns
3
3
3
3
ns
—
—
—
—
—
33
10
—
—
—
33
8
33
8
33
8
MHz
ns
—
tSCP
tSCRise
tSCFall
—
—
—
—
—
—
—
—
—
ns
2
2
2
2
ns
tModeCKP
256
256
256
256
ns
tSCP
tSCP
tSCP
tSCP
JTAG Clock Input Period
JTAG Clock HIGH
tTCK
—
—
—
—
—
—
—
—
—
—
100
40
40
5
—
—
—
—
—
100
40
40
5
—
—
—
—
—
100
40
40
5
—
—
—
—
—
100
40
40
5
ns
ns
ns
ns
ns
tTCKHIGH
tTCKLOW
tTCKRise
tTCKFall
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
5
5
5
5
Load Derate
CLD
—
—
2
—
2
—
2
—
2
ns/25pF
20 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
+4mA
To Device
Under Test
–
VREF
+1.5V
+
C
LD
–4mA
All Signals
50 pF
21 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
#ꢚ()*+*ꢌ-./0ꢛꢎꢕꢌ ꢂꢊꢋꢂꢏꢁꢌꢍꢎꢂꢏꢅꢂꢐ
The RC64575 is available in a 208-pin QFP package.
22 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
23 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
#ꢚ()*+)ꢌ2-/0ꢛꢎꢕꢌ ꢂꢊꢋꢂꢏꢁꢌꢍꢎꢂꢏꢅꢂꢐꢌ7ꢛꢂꢏꢁꢌ2ꢌꢉꢞꢌ89
The RC64574 is available in a 128-pin QFP package.
24 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
25 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
26 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
RC64574™ RC64575™
ꢒꢅ"ꢁꢅꢎꢕꢏꢌꢔꢕꢞꢉꢅꢐꢂꢃꢎꢉꢕ
YY
XXXX
A
999
A
IDT79RCXX
Product
Type
Operating
Voltage
Device
Type
Temp range/
Process
Package
Speed
Commercial Temperature
(0°C to +85°C Case)
Blank
DZ
DP
128-pin QFP
208-pin QFP
200 MHz Pipeline Clk
250 MHz Pipeline Clk
200
250
300 MHz Pipeline Clk
333 MHz Pipeline Clk
300
333
Embedded Processor
574
575
T
2.5V +/-5%
64-bit Embedded
Microprocessor
79RC64
IDT79RC64T574 - 200, 250, 300, 333 DZ
IDT79RC64T575 - 250, 300, 333 DP
128-pin QFP package, Commercial Temperature
208-pin QFP package, Commercial Temperature
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
27 of 27
October 14, 1999
*Notice: The information in this document is subject to change without notice
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