IDTCV111IPAG8 [IDT]
Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56;
| 型号： | IDTCV111IPAG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总19页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV111I
DESCRIPTION:
FEATURES:
IDTCV111I is a 56 pin clock device, complying the latest Intel CK410M
requirements, for Intel advance P4 processors. The CPU output buffer is
designedtosupportupto400MHzprocessor. ThischiphasthreePLLsinside
forCPU,SRC/PCI,and48MHz/DOT96IOclocks. Thisdevicealsoimplements
Band-gapreferencedIREF toreducetheimpactofVDD variationondifferential
outputs,whichcanprovidemorerobustsystemperformance. EachCPU/SRC
hasitsownSpreadSpectrumselection.
• Power management control suitable for notebook applications
• One high precision PLL for CPU, SCC and N programming
• One high precision PLL for SRC/PCI, supports 100MHz output
frequency, SCC and N programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a slower frequency to
conserve power when an application is less execution-
intensive
OUTPUTS:
• Available in TSSOP package
• 2*0.7V current –mode differential CPU CLK pair
• 7*0.7V current –mode differential SRC CLK pair
• One CPU_ITP/SRC selectable CLK pair
• 6*PCI, 2 free running, 33.3MHz
• 1*96MHz,1*48MHz
KEYSPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 250ps
• 1*REF
FUNCTIONALBLOCKDIAGRAM
PLL1
SSC
N Programmable
CPU CLK
CPU[1:0]
Output Buffers
Stop Logic
XTAL_IN
XTAL
CPU_ITP/SRC7
IREF
Osc Amp
REF
XTAL_OUT
ITP_EN
SDATA
SM Bus
Controller
SCLK
SRC CLK
Output Buffer
Stop Logic
PLL2
SSC
N Programmable
SRC[6:0]
VTT_PWRGD#/PD
Watch Dog
Timer
PCI[5:2], PCIF[1:0]
IREF
FSA.B.C
Control
Logic
PCI_STOP#
48MHz
CPU_STOP#
48MHz/96MHz
Output BUffer
PLL3
DOT96
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
JUNE 2005
1
© 2005 Integrated Device Technology, Inc.
DSC-6509/10
IDTCV111I
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VDDA
Description
Min
Max
4.6
Unit
V
3.3V Core Supply Voltage
VDD_PCI
VSS_PCI
PCI3
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2
VDD
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
2
PCI_STOP#
CPU_STOP#
FSC
TSTG
Storage Temperature
–65
0
+150
+70
+115
° C
° C
° C
V
3
TAMBIENT
TCASE
Ambient Operating Temperature
Case Temperature
PCI4
4
PCI5
5
REF
ESD Prot Input ESD Protection
Human Body Model
NOTE:
2000
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
6
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SDA
7
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VTT_PWRGD#/PD
VDD48
SCL
USB48/FSA
VSS48
VSS_CPU
CPU0
DOT96
CPU0#
DOT96#
FSB
VDD_CPU
CPU1
SRC0
CPU1#
SRC0#
IREF
SRC1
VSSA
SRC1#
VDDA
VDD_SRC
SRC2
CPU2_ITP/SRC7
CPU2_ITP#/SRC7#
VDD_SRC
SRC2#
SRC3
SRC6
SRC3#
SRC6#
SRC5
SRC4
SRC4#
SRC5#
VSS_SRC
VDD_SRC
TSSOP
TOP VIEW
FREQUENCYSELECTIONTABLE
FSC, B, A
101
CPU
100
SRC[7:0]
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
DOT
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
001
133
100
48
96
011
166
100
48
96
010
200
100
48
96
000
266
100
48
96
100
333
100
48
96
110
400
100
48
96
111
Reserve
100
48
96
2
IDTCV111I
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PINDESCRIPTION
Pin Number
Name
VDD_PCI
VSS_PCI
PCI1
Type
PWR
GND
OUT
OUT
OUT
GND
PWR
I/O
Description
1
2
3.3V
GND
3
PCI clock
PCI clock
PCI clock
GND
4
PCI2
5
PCI3
6
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
7
3.3V
8
PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2.
PCI clock, free running
9
OUT
IN
10
VTT_PWRGD#/PD
Level-sensitivestrobeusedtolatchtheFSA,FSB,FSC/TEST_SEL,andPCIF0/ITP_ENinputs. After
VTT_PWRGD#assertion,becomes areal-timeinputforassertingpowerdown(activeHIGH).
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VDD48
USB48/FSA
VSS48
PWR
I/O
3.3V
48MHz clock for CPU frequency selection
GND
OUT
OUT
IN
GND
DOT96
96MHz0.7currentmodedifferentialclockoutput
DOT96#
FSB
96MHz0.7currentmodedifferentialclockoutput
CPUfrequencyselection.
SRC0
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
GND
OUT
OUT
OUT
PWR
Differentialserialreferenceclock
SRC0#
SRC1
Differentialserialreferenceclock
Differentialserialreferenceclock
SRC1#
VDD_SRC
SRC2
Differentialserialreferenceclock
3.3V
Differentialserialreferenceclock
SRC2#
SRC3
Differentialserialreferenceclock
Differentialserialreferenceclock
SRC3#
SRC4
Differentialserialreferenceclock
Differentialserialreferenceclock
SRC4#
VDD_SRC
VSS_SRC
SRC5#
SRC5
Differentialserialreferenceclock
3.3V
GND
Differentialserialreferenceclock
Differentialserialreferenceclock
SRC6#
SRC6
Differentialserialreferenceclock
Differentialserialreferenceclock
VDD_SRC
CPU2_ITP#/SRC7#
CPU2_ITP/SRC7
VDDA
3.3V
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#.
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7.
3.3V
VSSA
GND
IREF
Referencecurrentfordifferentialoutputbuffer
Host0.7currentmodedifferentialclockoutput
Host0.7currentmodedifferentialclockoutput
3.3V
CPU1#
CPU1
VDD_CPU
3
IDTCV111I
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(CONT.)
Pin Number
Name
CPU0#
CPU0
Type
OUT
OUT
GND
IN
Description
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Host0.7currentmodedifferentialclockoutput
Host0.7currentmodedifferentialclockoutput
VSS_CPU
SCL
GND
SMBus clock
SDA
I/O
SMBus data
VDD_REF
XTAL_OUT
XTAL_IN
VSS_REF
REF
PWR
OUT
IN
3.3V
XTALoutput
XTALinput
GND
OUT
IN
GND
14.318MHzreferenceclockoutput
CPUfrequencyselection.
Stop all stoppable CPU CLK
Stop all stoppable PCI, SRC CLK
PCI clock
FSC
CPU_STOP#
PCI_STOP#
PCI0
IN
IN
OUT
INDEXBLOCK WRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
untilNthbyte(bytecountbit30-37).
Bit
1
# of bits
From
Master
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
Bit
1
# of bits
From
Master
Master
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
D2h
11-18
19
Master
Slave
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
Master
Slave
11-18
19
Master
Slave
29-36
37
Master
Slave
20
Master
Master
Slave
21-28
29
D3h
38-45
46
Master
Slave
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Slave
Byte count, N (block read back of N
bytes), power on is 8
38
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
39-46
47
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
INDEX BYTE READ
INDEX BYTE WRITE
Settingbit[11:18]=startingaddress. Afterreadingbackthe firstdata byte,
masterissuesStopbit.
Settingbit[11:18]=startingaddress,bit[20:27]=01h.
4
IDTCV111I
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
CONTROLREGISTERS
N PROGRAMMING PROCEDURE
•
•
Use Index byte write.
For N programming, the user only needs to access Byte17, Byte 25, and Byte8.
1.
2.
3.
Write Byte17forCPUPLLN, CPUf=N*Resolution, see resolutiontable belowByte17.
Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3.
Enable N Programming bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly.
•
•
Center spread only works when the N Programming bit is enabled. Down spread is OK even N Programming bit is disabled
Itis OKtochange Nvalue toanyvalue onthe benchtestboard. Inthe system, IDTrecommends the steppingchange. Itis unknownhowmuch
thesystemcansustainforeachsteppingchange;theestimateis about5.IftheNchanges toomuchinonestep,thesystemwilllikelyhang.
Note that SATA is with SRC PLL. This SATA Hard Drive might not operate during SRC N programming.
•
MostoftheBytes,fromByte8-Byte31,areusedtoadjustoutputwaveformsandSSCmodulationprofiles.Thepoweronsettingwillbechangedaccording
toeachpoweronfrequencyselection.Toavoidmistakes,don’twriteonthosebyte(becarefulaboutBlockWrite). ItissuggestedtousetheIndexByte
writetoaccessbytes.
SSC MAGNITUDE CONTROL FOR CPU, FREQUENCYSELECTIONTABLE
FS_C, B, A
101
CPU
100
SRC, AND SMC
SMC[2:0]
000
001
133
-0.25
-0.5
011
166
001
010
200
010
-0.75
-1
000
266
011
100
333
100
±0.125
±0.25
±0.375
±0.5
110
400
101
111
RESERVE
110
111
RESOLUTION
CPU (MHz)
100
Resolution
0.666667
0.666667
1.333333
1.333333
1.333333
2.666667
2.666667
N =
150
200
125
150
200
125
150
133
166
200
266
333
400
5
IDTCV111I
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
CONTROLREGISTERS
For all Reserved bits, X = Don't Care
BYTE 0
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC0, SRC0#
SRC1, SRC1#
SRC2, SRC2#
SRC3, SRC3#
SRC4, SRC4#
SRC5, SRC5#
SRC6, SRC6#
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
CPU2, CPU2#/
SRC7, SRC7#
BYTE 1
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
0
CPU[2:0], SRC[7:0],
PCI[5:0], PCIF[1:0]
SpreadSpectrummodeenable
Spreadoff
Spreadon
RW
0
1
2
3
4
5
6
7
CPU0, CPU0#
CPU1, CPU1#
Reserved
REF
OutputEnable
OutputEnable
Tristate
Tristate
Enable
Enable
RW
RW
X
1
1
X
1
1
1
1
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
RW
RW
RW
RW
USB48
DOT96
PCIF0
BYTE 2
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
PCIF1
Reserved
Reserved
Reserved
PCI2
OutputEnable
Tristate
Enable
RW
X
1
X
X
X
1
X
X
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
RW
RW
RW
RW
PCI3
1
PCI4
1
PCI5
1
BYTE 3
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC0
SRC1
SRC2
SRC3
SRC4
SRC5
SRC6
SRC7
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Allowcontrolledby
Freerunning,not
Stoppedwith
PCI_STOP#
PCI_STOP# assertion
affected by PCI_STOP#
6
IDTCV111I
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 4
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
CPU0, CPU0#
Allow control of CPU0
Notstopped
Stoppedwith
RW
1
with assertion of CPU_STOP#
by CPU_STOP#
CPU_STOP#
1
2
CPU1, CPU1#
CPU2, CPU2#
Allow control of CPU1
with assertion of CPU_STOP#
Notstopped
by CPU_STOP#
Stoppedwith
CPU_STOP#
RW
RW
1
1
Allow control of CPU2
Notstopped
Stoppedwith
with assertion of CPU_STOP#
by CPU_STOP#
CPU_STOP#
3
4
5
6
7
PCIF0
PCIF1
Allowcontrolledby
Notstopped
Stoppedwith
PCI_STOP#
RW
RW
X
0
PCI_STOP# assertion
by PCI_STOP#
0
Reserved
DOT96
X
0
DOT96powerdowndrive mode
Driven in power down
Tristate
RW
X
Reserved
X
BYTE 5
Bit
0
Output(s)Affected
CPU0, CPU0#
CPU1, CPU1#
CPU2, CPU2#
SRC[7:0], SRC[7:0]#
CPU0
Description / Function
CPU0 PD drive mode
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
Driven in power down
Driven in power down
Driven in power down
Driven in power down
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
0
0
0
0
0
0
0
0
1
CPU1 PD drive mode
2
CPU2 PD drive mode
3
SRC PD drive mode
4
CPU0 CPU_STOP drive mode
CPU1 CPU_STOP drive mode
CPU2 CPU_STOP drive mode
SRC PCI_STOP drive mode
Driven in CPU_STOP# Tristatewhenstopped
Driven in CPU_STOP# Tristatewhenstopped
Driven in CPU_STOP# Tristatewhenstopped
5
CPU1
6
CPU2
7
SRC[7:0], SRC[7:0]#
Driven in PCI_STOP
Tristatewhenstopped
BYTE 6
Bit
0
Output(s)Affected
CPU[2:0]
Description / Function
FSA latched value on power up
FSB latched value on power up
FSC latched value on power up
0
1
Type
R
Power On
Latched
Latched
Latched
1
1
CPU[2:0]
R
2
CPU[2:0]
R
3
PCI, SRC
SoftwarePCI_STOPcontrolfor
PCI and SRC CLK
Stop all PCI, PCIF, and
SRC which can be stopped
by PCI_STOP#
SoftwareSTOP
Disabled
RW
4
5
REF
REFdrivestrength
1x drive
2x drive
1
Reserved
Reserved
X
X
X
6
7
X
0
CPU, SRC, PCI
PCIF, REF,
Only valid when Byte 6, Bit 7
is HIGH
Hi-Z
REF/N
USB48, DOT96
7
IDTCV111I
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 7
Bit
0
Output(s)Affected
Description / Function
VendorID
0
1
Type
R
Power On
1
0
1
0
0
0
0
0
1
VendorID
R
2
VendorID
R
3
VendorID
R
4
Revision ID
Revision ID
Revision ID
Revision ID
R
5
R
6
R
7
R
BYTE 8
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
One cycle read
disable
Disable
enable
enable
RW
RW
X
0
1
X
0
1
0
0
0
NProgrammingenable
Reserved
USB48
USB48Strengthcontrol
USB PLL power down
SRC PLL power down
CPU PLL power down
1x
2x
RW
RW
RW
RW
RW
normal
normal
normal
disable
Power down
Power down
Power down
enable
SRC, PLL2, SSC enable Only valid when Byte1 bit0 is 1
BYTE 9
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC SMC0
SRC SMC1
SRC SMC2
Reserved
SRC/PCI SSC control
see SMC table
RW
RW
RW
RW
RW
RW
RW
RW
0
1
0
0
0
1
1
1
CPU SMC0
CPU SMC1
CPU SMC2
CPU PLL SSC control
see SMC table
8
IDTCV111I
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTES 10-16: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
BYTE17
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
CPU_N0, LSB
CPU_N1
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
0
0
0
0
CPU_N2
CPU_N3
CPU CLK = N* Resolution
seeResolutiontable
CPU_N4
CPU_N5
CPU_N6
CPU_N7, MSB
BYTES 18-24: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
BYTE25
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC_N0, LSB
SRC_N1
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
SRC_N2
SRC f = N*SRC Resolution
Resolution=0.666667
100MHz N= 150
SRC_N3
SRC_N4
SRC_N5
SRC_N6
SRC_N7, MSB
BYTES 26-31: OUTPUT WAVEFORM ADJUSTMENT. DON'T WRITE OVER.
9
IDTCV111I
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
Test Conditions
Min.
2
Typ.
—
Max.
Unit
V
3.3V ± 5%
3.3V ± 5%
VDD + 0.3
VIL
Input LOW Voltage
VSS - 0.3
0.7
VSS - 0.3
–5
—
0.8
V
VIH_FS
VIL_FS
IIH
LOW Voltage, HIGH Threshold
LOW Voltage, LOW Threshold
Input HIGH Current
For FSA.B.C test_mode
For FSA.B.C test_mode
VIN = VDD
—
VDD + 0.3
V
—
0.35
5
V
—
µ A
µ A
µ A
mA
mA
IIL1
Input LOW Current
VIN = 0V, inputs with no pull-up resistors
VIN = 0V, inputs with pull-up resistors
Full active, CL = full load
All differential pairs driven
All differential pairs tri-stated
VDD = 3.3V
–5
—
—
—
400
70
12
—
7
IIL2
Input LOW Current
–200
—
—
IDD3.3OP
IDD3.3PD
Operating Supply Current
Powerdown Current
—
—
—
—
—
(1)
FI
Input Frequency
—
14.31818
—
MHz
nH
LPIN
Pin Inductance(2)
—
CIN
Logic inputs
—
—
5
COUT
CINX
TSTAB
Input Capacitance(2)
Clock Stabilization(2,3)
Output pin capacitance
—
—
6
pF
XTAL_IN and XTAL_OUT pins
From VDD power-up or de-assertion of PD to first clock
Triangular modulation
—
—
5
—
—
1.8
33
15
300
5
ms
KHz
ns
(2)
Modulation Frequency
30
—
TDRIVE_SRC(2)
SRC output enable after PCI_STOP# de-assertion
CPU output enable after PD de-assertion
Fall time of PD
—
—
(2)
TDRIVE_PD
—
—
us
(2)
TFALL_PD
—
—
ns
(2)
TRISE_PD
Rise time of PD
—
—
5
ns
TDRIVE_CPU_STOP#(2)
TFALL_CPU_STOP#(2)
TRISE_CPU_STOP#(2)
CPU output enable after CPU_STOP# de-assertion
Fall time of CPU_STOP#
—
—
10
5
us
—
—
ns
Rise time of CPU_STOP#
—
—
5
ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
10
IDTCV111I
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
ZO
Parameter
Test Conditions
Min.
3000
2.4
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
Ω
Current Source Output Impedance(2) VO = VX
VOH3
VOL3
Output HIGH Voltage
Output LOW Voltage
IOH = -1mA
IOL = 1mA
—
V
—
0.4
V
(2)
VHIGH
VLOW
VOVS
Voltage HIGH
Statistical measurement on single-ended signal using
oscilloscope math function
660
–300
—
1150
150
1150
—
mV
(2)
Voltage LOW
Max Voltage(2)
Min Voltage(2)
Measurement on single-ended signal using absolute value
mV
VUDS
–300
250
—
VCROSS(ABS) Crossing Voltage (abs)(2)
550
140
mV
mV
ppm
d - VCROSS
ppm
Crossing Voltage (var)(2)
Variation of crossing over all edges
(2,3)
Long Accuracy
See TPERIOD Min. - Max. values
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
–300
—
—
—
—
300
2.5133
3.016
3.77
2.4993
2.9991
3.7489
TPERIOD
Average Period(3)
200MHz nominal / -0.5% spread
4.9985
—
5.0266
ns
166.66MHz nominal / -0.5% spread
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
5.9982
7.4978
9.997
—
—
—
6.032
7.54
10.0533
96MHz nominal
10.4135
2.4143
2.9141
3.6639
—
—
—
—
10.4198
—
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
—
—
200MHz nominal / -0.5% spread
166.66MHz nominal / -0.5% spread
4.9135
5.9132
—
—
—
—
TABSMIN
Absolute Min Period(2,3)
ns
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
96MHz nominal
7.4128
9.912
10.1635
175
—
—
—
—
—
—
—
—
—
—
—
tR
tF
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
VOL = 0.175V, VOH = 0.525V
700
700
125
125
55
ps
ps
ps
ps
%
Fall Time(2)
175
d-tR
Rise Time Variation(2)
Fall Time Variation(2)
Duty Cycle(2)
—
d-tF
—
dT3
Measurement from differential waveform
45
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
11
IDTCV111I
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR,CONTINUED(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
Max.
100
Unit
(2)
Skew, CPU[1:0]
tSK3
Skew, CPU2(2)
VT = 50%
—
—
250
ps
Skew, SRC(2)
—
—
—
—
—
—
250
85
(2)
Jitter, Cycle to Cycle, CPU[1:0]
Jitter, Cycle to Cycle, CPU2(2)
tJCYC-CYC
Measurement from differential waveform
100
ps
Jitter, Cycle to Cycle, SRC(2)
Jitter, Cycle to Cycle, DOT96(2)
—
—
—
—
125
250
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
Max.
Unit
ppm
ns
(1,2)
ppm
StaticError
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
30.009
30.1598
—
TPERIOD
ClockPeriod(2)
29.991
29.991
2.4
—
VOH
VOL
IOH
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
IOL
OutputLOWCurrent
30
—
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
1
4
V/ns
V/ns
ns
Fallingedgerate
1
4
tR1
tF1
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
ns
dT1
Duty Cycle(1)
55
%
(1)
tSK1
Skew
VT = 1.5V
—
500
500
ps
tJCYC-CYC
Jitter, Cycle to Cycle(1)
VT = 1.5V
—
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
12
IDTCV111I
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICALCHARACTERISTICS,48MHZ,USB
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
ppm
StaticError(1,2)
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
TPERIOD
VOH
ClockPeriod(2)
20.8257
2.4
—
20.834
—
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-29
—
mA
-23
—
IOL
OutputLOWCurrent
29
mA
—
27
EdgeRate(1)
1
2
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
2
tR1
tF1
RiseTime(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.5
0.5
45
1.2
1.2
55
FallTime(1)
ns
dT1
Duty Cycle(1)
%
tJCYC-CYC
Jitter, Cycle to Cycle
—
350
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS-REF-14.318MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
14.318MHzoutputnominal
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
(1)
ppm
LongAccuracy
TPERIOD
VOH
Clock Period
69.827
2.4
—
69.855
—
OutputHIGHVoltage(1)
OutputLOWVoltage(1)
Output HIGH Current
V
VOL
IOL = 1mA
0.4
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
1
4
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
4
tR1
tF1
Rise Time(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
55
Fall Time(1)
ns
dT1
Duty Cycle(1)
Jitter, Cycle to Cycle(1)
%
tJCYC-CYC
VT = 1.5V
—
1000
ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
13
IDTCV111I
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PCISTOPFUNCTIONALITY
ThePCI_STOP#signalisonanactivelowinputcontrollingPCIandSRCoutputs.IfPCIF[1:0]andSRCclockscanbesettobefree-runningthroughSMBus
programming, theywillignore boththe PCI_STOP#pinandthe PCI_STOPregisterbit.
PCI_STOP#
CPU
CPU#
Normal
Normal
SRC
Normal
SRC#
Normal
Low
PCIF/PCI
33MHz
Low
USB
DOT96
Normal
Normal
DOT96#
Normal
Normal
REF
1
0
Normal
Normal
48MHz
48MHz
14.318MHz
14.318MHz
IREF * 6 or float
PCI_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
TheclocksamplesthePCI_STOP#signalonarisingedgeofPCIFclock.AfterdetectingthePCI_STOP#assertionlow,allPCI[6:0]andstoppablePCIF[1:0]
clocks willlatchlowontheirnexthightolowtransition. Afterthe PCIclocks are latchedlow, the SRCclock, (ifsettostoppable)willlatchhighatIREF *6(or
tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below.
tSU
PCI_STOP#
PCIF[1:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP#-DE-ASSERTION
Thede-assertionofthePCI_STOP#signalistobesampledontherisingedgeofthePCIFfreerunningclockdomain.AfterdetectingPCI_STOP#de-assertion,
allPCI[6:0], stoppable PCIF[1:0]andstoppable SRCclocks willresume ina glitchfree manner.
tSU
tDRIVE_SRC
PCI_STOP#
PCIF[1:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
14
IDTCV111I
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
CPUSTOPFUNCTIONALITY
The CPU_STOP#signalis anactive lowinputcontrollingthe CPUoutputs. This signalcanbe assertedasynchronously.
CPU_STOP#
CPU
Normal
CPU#
Normal
Low
SRC
SRC#
Normal
Normal
PCIF/PCI
33MHz
USB
DOT96
Normal
Normal
DOT96#
Normal
Normal
REF
1
0
Normal
Normal
48MHz
48MHz
14.318MHz
14.318MHz
IREF * 6 or float
33MHz
CPU_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
AssertingCPU_STOP#pinstopsallCPUoutputsthataresettobestoppableaftertheirnexttransition.WhentheI2CCPU_STOPtri-statebitcorresponding
totheCPUoutputofinterestisprogrammedtoa‘0’,CPUoutputwillstopCPU_True=HighandCPU_Complement=Low.WhentheI2CCPU_STOP#tri-
statebitcorrespondingtotheCPUoutputofinterestisprogrammedtoa‘1’,CPUoutputswillbetri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - DE-ASSERTION (TRANSITION FROM ‘0’ TO ‘1’)
Withthede-assertionofCPU_STOP#allstoppedCPUoutputswillresumewithoutaglitch.Themaximumlatencyfromthede-assertiontoactiveoutputs
istwotosixCPUclockperiods.Ifthecontrolregistertristatebitcorrespondingtotheoutputofinterestisprogrammedto‘1’,thenthestoppedCPUoutputswill
be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.
CPU_STOP#
CPU
CPU#
CPU Internal
tDRIVE_CPU_Stop
10nS > 200mV
15
IDTCV111I
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PD, POWER DOWN
PDisanasynchronousactivehighinputusedtoshutoffallclockscleanlypriortoclockpower. WhenPDisassertedhighallclockswillbedrivenlowbefore
turningofftheVCO.InPDde-assertionallclockswillstartwithoutglitches.
PD
0
CPU
Normal
CPU#
Normal
Float
SRC
Normal
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
USB
48MHz
Low
DOT96
Normal
DOT96#
Normal
Float
REF
14.318MHz
Low
1
IREF * 2 or float
IREF * 2 or float
IREF * 2 or float
PDASSERTION
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
16
IDTCV111I
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PDDE-ASSERTION
tSTABLE <1.8mS
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PWRDWN
<300μS, <200mV
17
IDTCV111I
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
DIFFERENTIALCLOCKTRISTATE
Tominimizepowerconsumption,CPU[2:0]clockoutputsareindividuallyconfigurablethroughSMBustobedrivenortristatedduringPDandCPU_STOP#
modeandtheSRCclockis configurabletobedrivenortristatedduringPCI_STOP#andPD mode.Eachdifferentialclock(SRC,CPU[2:0])outputcanbe
disabledbysettingthecorrespondingoutput’sregisterOEbitto“0”(disable).Disabledoutputsaretobetristatedregardlessof“CPU_STOP”,“SRC_STOP”
and“PD”registerbitsettings.
Signal
CPU
CPU
CPU
CPU
CPU
Pin PD
Pin CPU_STOP#
CPU_STOPTristate Bit
PD Tristate Bit
Non-StoppableOutputs Stoppable Outputs
0
0
0
1
1
1
X
0
X
X
X
0
Running
Running
Running
Driven at IREF x 6
Tristate
0
0
1
Running
X
X
X
X
Driven at IREF x 2
Tristate
Driven at IREF x 2
Tristate
1
NOTES:
1. Each output has four corresponding control register bits; OE, PD, CPU_STOP, and “Free Running”.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
Signal
SRC
SRC
SRC
SRC
SRC
Pin PD
Pin PCI_STOP#
PCI_STOPTristate Bit
PD Tristate Bit
Non-StoppableOutputs Stoppable Outputs
0
0
0
1
1
1
X
0
X
X
X
0
Running
Running
Running
Driven at IREF x 6
Tristate
0
0
1
Running
X
X
X
X
Driven at IREF x 2
Tristate
Driven at IREF x 2
Tristate
1
NOTES:
1. SRC output has four corresponding control register bits; OE, PD, SRC_STOP, and “Free Running”.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
TRISTATEDOT96CLOCKCONTROL
Signal
DOT96
DOT96
DOT96
Pin PD
PD Tristate Bit
Output
1
0
0
X
0
Running
Driven at IREF x 2
Tristate
1
NOTES:
1. DOT output has two corresponding control register bits; OE and PD.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
18
IDTCV111I
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ORDERINGINFORMATION
IDTCV
XXX
XX
X
Device Type
Package
Grade
Commercial Temperature Range
Blank
(0°C to +70°C)
Thin Small Shrink Outline Package
TSSOP - Green
PA
PAG
Programmable FlexPC Clock for P4 Processor
111I
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6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
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for Tech Support:
logichelp@idt.com
19
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