IDTCV169NLG [IDT]
Processor Specific Clock Generator, 400MHz, GREEN, VFQFPN-64;
| 型号： | IDTCV169NLG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 400MHz, GREEN, VFQFPN-64 时钟 外围集成电路 晶体 |
| 文件： | 总20页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV169
DESCRIPTION:
FEATURES:
IDTCV169isa64pinclockdevice,complyingwithIntelCK410Mrequirements
forInteladvanceP4processors.TheCPUoutputbufferisdesignedtosupport
upto400MHzprocessor. ThisdevicealsoimplementsBand-gapreferenced
IREF to reduce the impact of VDD variation on differential outputs, which can
providemorerobustsystemperformance.
• Power management control suitable for notebook applications
• One high precision PLL for CPU/SRC/PCI, SSC and N program-
ming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength
• Smooth transition for N programming
• Available in VFQFPN package
OUTPUTS:
• 2*0.7V current –mode differential CPU CLK pair
• 9*0.7V current –mode differential SRC CLK pair
• One CPU_ITP/SRC selectable CLK pair
• 5*PCI, 1 free running, 33.3MHz
• 1*96MHz,1*48MHz
KEYSPECIFICATIONS:
• CPU CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 250ps
• 1*REF
FUNCTIONALBLOCKDIAGRAM
CPU[1:0]
CPU CLK
Output Buffer
PLL1
SSC
N Programmable
Stop Logic
XTAL_IN
XTAL
CPU_ITP/SRC7
IREF
Osc Amp
REF
XTAL_OUT
ITP_EN
SDATA
SM Bus
SRC CLK
Controller
Output Buffer
SCLK
SRC[10:8], [6:5], [3:0]
Stop Logic
PCI[3:0], PCIF0
VTT_PWRGD#/PD
IREF
OE6#, OE3#,
OE1#, OE0#
OE[B:A]#
Control
48MHz
Logic
48MHz/96MHz
Output BUffer
FSA.B.C
PLL2
PCI_STOP#
CPU_STOP#
DOT96
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 2005
1
© 2005 Integrated Device Technology, Inc.
DSC 6903/2
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
1
VSS48
SRC0LP
SRC0LP#
(1)OE0#
48
47
46
VDD_PCI
REF
2
3
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SDA
45
4
SRC1LP
SRC1LP#
(1) OEA#
44
43
42
5
6
7
8
SRC2LP
SRC2LP#
VDD_SRC
VSS_SRC
(1) OE3#
41
40
39
SCL
9
CPU_STOP#
CPU0LP
CPU0LP#
VSS_CPU
VDD_CPU
CPU1LP
CPU1LP#
VSS_SRC
10
11
12
13
14
15
16
38
37
36
35
SRC3LP
SRC3LP#
(1) OE6#
34
33
PCI_STOP#
VFQFPN
TOP VIEW
NOTE:
1. Internal pull-up.
2
IDTCV169
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PINDESCRIPTION
Name
Type
GND
O
Pin#
1
Description
VSS_48
Groundpin
SRC0LP(1)
SRC0LP#(1)
OE0#
2
DifferentialSerialreferenceclocks
DifferentialSerialreferenceclocks
O
3
I
4
3.3VLVTTLinputforCLKREQ#(activelow)withinternalpull-upresistor(100Kohm)
DifferentialSerialreferenceclocks
SRC1LP(1)
SRC1LP#(1)
OEA#
O
5
O
6
DifferentialSerialreferenceclocks
I
7
3.3VLVTTLinputforCLKREQ#(activelow)withinternalpull-upresistor(100Kohm)
DifferentialSerialreferenceclocks
SRC2LP(1)
SRC2LP#(1)
VDD_SRC
VSS_SRC
O
8
O
9
DifferentialSerialreferenceclocks
PWR
GND
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3.3V
GND
OE3#
3.3VLVTTLinputforCLKREQ#(activelow)withinternalpull-upresistor(100Kohm)
DifferentialSerialreferenceclocks
SRC3LP(1)
SRC3LP#(1)
OE6#
O
O
DifferentialSerialreferenceclocks
I
3.3VLVTTLinputforCLKREQ#(activelow)withinternalpull-upresistor(100Kohm)
3.3V LVTTL input for PCI_STOP# (active low)
3.3V
PCI_STOP#
VDD_SRC
SRC5LP(1)
SRC5LP#(1)
SRC6LP#(1)
SRC6LP(1)
SRC8LP(1)
SRC8LP#(1)
OEB#
I
PWR
O
DifferentialSerialreferenceclocks
O
DifferentialSerialreferenceclocks
O
DifferentialSerialreferenceclocks
O
DifferentialSerialreferenceclocks
O
DifferentialSerialreferenceclocks
O
DifferentialSerialreferenceclocks
I
3.3VLVTTLinputforCLKREQ#(activelow)withinternalpull-upresistor(100Kohm)
DifferentialSerialreferenceclocks
SRC9LP#(1)
SRC9LP(1)
SRC10LP(1)
SRC10LP#(1)
VDD_SRC
VSS_SRC
O
O
DifferentialSerialreferenceclocks
O
DifferentialSerialreferenceclocks
O
DifferentialSerialreferenceclocks
PWR
GND
O
3.3V
GND
CPU2_ITPLP#/SRC7LP#(1)
Selectable DifferentialCPUorSRCclockoutput.ITP_EN=0@VTT_PWRGD#assertion=SRCITP_EN=1@
VTT_PWRGD# assertion = CPU.
CPU2_ITPLP/SRC7LP(1)
O
32
Selectable DifferentialCPUorSRCclockoutput.ITP_EN=0@VTT_PWRGD#assertion=SRCITP_EN=1@
VTT_PWRGD# assertion = CPU.
VSS_SRC
CPU1LP#(1)
CPU1LP(1)
VDD_CPU
VSS_CPU
CPU0LP#(1)
CPU0LP(1)
CPU_STOP#
SCL
GND
O
33
34
35
36
37
38
39
40
41
42
43
44
45
46
GND
DifferentialCPUclockoutputs
DifferentialCPUclockoutputs
3.3V
O
PWR
GND
O
GND
DifferentialCPUclockoutputs
DifferentialCPUclockoutputs
3.3V LVTTL input for CPU_STOP# (active low)
SMBus compatible SCLOCK
SMBus compatible SDATA
3.3V
O
I
I
SDA
I/O
PWR
I/O
I
VDD_REF
XTAL_OUT
XTAL_IN
14.41818MHzcrystaloutput
14.41818MHzcrystalinput
GND
VSS_REF
GND
NOTE:
1. Buffer type should be the push-pull type. No external Pull-down and damping resistors are recommended.
3
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION
Name
REF
Type
O
Pin#
47
48
49
50
51
52
53
54
55
56
Description
3.3V14.41818MHzcrystaloutput
3.3V
VDD_PCI
PCI3
PWR
O
33.33333MHzclocksPCIoutputs shouldbe designedtodrive atleasttwodevices
33.33333MHzclocksPCIoutputs shouldbe designedtodrive atleasttwodevices
33.33333MHzclocksPCIoutputs shouldbe designedtodrive atleasttwodevices
33.33333MHzclocksPCIoutputs shouldbe designedtodrive atleasttwodevices
33.33333 MHz clock / CPU2 select (sampled on VTT_PWRGD# assertion) High = CPU2
3.3V
PCI2
O
PCI1
O
PCI0
O
PCIF0/ITP_EN
VDD_PCI
VSS_PCI
VTT_PWRGD#/PWRDWN
IO
PWR
GND
I
GND
3.3VLVTTLinputisalevel-sensitivestrobeusedtolatchtheUSB_48/FA_A,FS_B,FS_C/TEST_SELandPCIF0/
ITP_ENinputs(activeLOW). AfterVTT_PWRGD#assertion,becamesareal-timeinputforassertingpowerdown
(active HIGH).
FS_C/TEST_SEL
I
57
3.3VtolerantinputforCPUfrequencyselection. Selectstestmodeifpulledto3.3VwhenVTT_PWRGD#isasserted
LOW.
USB_48/FA_A
VSS_48
O
GND
PWR
O
58
59
60
61
62
63
64
Fixed 48MHz clock output. 3.3V tolerant input for CPU frequency selection.
GND
VDD_48
3.3V
DOT_96LP(1)
DOT_96LP#(1)
FS_B/TEST_MODE
OE1#
Fixed 96MHz clock output
O
Fixed 96MHz clock output
I
3.3VtolerantinputforCPUfrequencyselection. Selects Ref/NorHi-Zwhenintestmode. 0=Hi-Z, 1=Ref/N
3.3VLVTTLinputforCLKREQ#(activeLOW)withinternalpull-upresistor(100KΩ)
I
NOTE:
1. Buffer type should be the push-pull type. No external Pull-down and damping resistors are recommended.
4
IDTCV169
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
VDDA
Description
Min
Max
4.6
Unit
V
3.3V Core Supply Voltage
VDD
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
TSTG
Storage Temperature
–65
0
+150
+70
+115
° C
° C
° C
V
TAMBIENT
TCASE
Ambient Operating Temperature
Case Temperature
ESD Prot Input ESD Protection
Human Body Model
NOTE:
2000
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
FREQUENCYSELECTIONTABLE
FSC, B, A
101
CPU
100
SRC
100
100
100
100
100
100
100
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
DOT
REF
96
96
96
96
96
96
96
96
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
001
133
48
011
166
48
010
200
48
000
266
48
100
333
48
110
400
48
111
Reserve
48
5
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
INDEXBLOCKWRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
untilNthbyte(bytecountbit30-37).
Bit
1
# of bits
From
Master
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
Bit
1
# of bits
From
Master
Master
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
D2h
11-18
19
Master
Slave
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
Master
Slave
11-18
19
Master
Slave
29-36
37
Master
Slave
20
Master
Master
Slave
21-28
29
D3h
38-45
46
Master
Slave
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Slave
Byte count, N (block read back of N
bytes)
38
39-46
47
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
S.E.CLOCKSTRENGTHSELECTION
(PCI, REF)
SSC MAGNITUDE CONTROL FOR CPU,
SRC, AND SMC
SMC[2:0]
Str[1:0]
Level
000
001
010
011
100
101
110
111
-0.25
-0.5
00
1
01
0.8
0.6
1.2
-0.75
-1
10
11
±0.125
±0.25
±0.375
±0.5
6
IDTCV169
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
CONTROLREGISTERS
BYTE 0
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CPU2_ITP/SRC7
SRC6
OutputEnable
OutputEnable
OutputEnable
Hi-Z
Hi-Z
Hi-Z
Enable
Enable
Enable
RW
RW
RW
1
1
1
1
1
1
1
1
SRC5
Reserved
SRC3
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Enable
Enable
Enable
Enable
RW
RW
RW
RW
SRC2
SRC1
SRC0
BYTE 1
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PCI_F0
DOT96
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Enable
Enable
Enable
Enable
RW
RW
RW
RW
1
1
1
1
1
1
1
0
USB48
REF
Reserved
CPU1
OutputEnable
OutputEnable
Hi-Z
Hi-Z
Enable
Enable
RW
RW
RW
CPU0
CPUCLK/SRC/PCICLK
SpreadSpectrumMode
Spreadoff
Spreadon
BYTE 2
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Reserved
Reserved
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
BYTE 3
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC7, OEB#
Reserved
OEB# controls SRC7 select
NotControl
Control
RW
0
0
0
0
0
0
0
0
SRC5, OEB#
Reserved
OEB# controls SRC5 select
OEB# controls SRC2 select
NotControl
NotControl
Control
RW
RW
Reserved
SRC2, OEB#
Reserved
Control
Reserved
7
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 4
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
Reserved
DOT96T
Reserved
Reserved
PCIF0
RW
RW
RW
RW
RW
0
0
0
0
0
DOT96powerdowndrive mode
Driven
Tristate
Allowcontrolledby
PCI_STOP# assertion
Freerunning
Freerunning
2
1
0
CPU2
CPU1
CPU0
Allow control of CPU_2
with assertion of CPU_STOP#
RW
RW
RW
1
1
1
Stoppable
Allow control of CPU_1
with assertion of CPU_STOP#
Allow control of CPU_0
with assertion of CPU_STOP#
BYTE 5
Bit
7
Output(s)Affected
Reserved
CPU2
Description / Function
0
1
Type
Power On
0
0
0
0
0
0
0
0
6
CPU2 CPU_STOP# drive mode
CPU1 CPU_STOP# drive mode
CPU0 CPU_STOP# drive mode
SRC Pwrdwn drive mode
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
RW
RW
RW
RW
RW
RW
RW
5
CPU1
4
CPU0
3
SRCs
2
CPU2
CPU2 Pwrdwn drive mode
CPU1 Pwrdwn drive mode
CPU0 Pwrdwn drive mode
1
CPU1
0
CPU0
BYTE 6
Bit
7
Output(s)Affected
Description / Function
REF/NorTristateSelect
0
1
Type
Power On
Tristate
REF/N
RW
RW
0
0
0
1
1
6
Test Clock Mode Entry Control
Normaloperation
REF/N or Tristate Mode
5
Reserved
REF
4
REFOutputDriveStrength
1x
2x
RW
RW
3
SoftwarePCI_STOPfunction
Software PCI_STOP
StopstoppablePCI/F0
normal
controlforallstoppablePCI
2
1
CPUCLKs
CPUCLKs
FS_CReflects thevalueofthe
FS_C pin sampled on power up
0 = FS_C was low
R
duringVTT_PWRGD#assertion
FS_BReflects thevalueofthe
R
FS_B pin sampled on power up
0 = FS_B was low
duringVTT_PWRGD#assertion
0
CPUCLKs
FS_AReflects thevalueofthe
R
FS_A pin sampled on power up
0 = FS_A was low
duringVTT_PWRGD#assertion
8
IDTCV169
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 7
Bit
7
Output(s)Affected
Description / Function
Revision ID
Revision ID
Revision ID
Revision ID
VendorID
0
1
Type
Power On
0
0
0
0
0
1
0
1
6
5
4
3
2
VendorID
1
VendorID
0
VendorID
BYTE 8
Bit
Output(s)Affected
Reserved
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
RW
RW
RW
RW
0
1
1
1
0
0
0
0
SRC10
SRC9
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Enable
Enable
Enable
SRC8
Reserved
SRC10
SRC9
OEA# controls SRC10 select
OEB# controls SRC9 select
OEA# controls SRC8 select
NotControl
NotControl
NotControl
Control
Control
Control
RW
RW
RW
SRC8
BYTE 9
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PCI3
PCI2
PCI3OutputDriveStrength
PCI2OutputDriveStrength
PCI1OutputDriveStrength
PCI0OutputDriveStrength
PCIF0OutputDriveStrength
CLUCLK2OutputDrive Strength
CLUCLK1OutputDrive Strength
CLUCLK0OutputDrive Strength
1x
1x
2x
2x
2x
2x
2x
1x
1x
1x
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
PCI1
1x
PCI0
1x
PCIF0
1x
CPUCLK2
CPUCLK1
CPUCLK0
0.75x
0.75x
0.75x
BYTE10
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC7
SRC6
SRC7OutputDriveStrength
SRC6OutputDriveStrength
SRC5OutputDriveStrength
0.75x
0.75x
0.75x
1x
1x
1x
RW
RW
RW
1
1
1
1
1
1
1
1
SRC5
Reserved
SRC3
SRC3OutputDriveStrength
SRC2OutputDriveStrength
SRC1OutputDriveStrength
SRC0OutputDriveStrength
0.75x
0.75x
0.75x
0.75x
1x
1x
1x
1x
RW
RW
RW
RW
SRC2
SRC1
SRC0
9
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE11
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
SRC10
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
SRC10OutputDriveStrength
SRC9OutputDriveStrength
SRC8OutputDriveStrength
0.75x
0.75x
0.75x
1x
1x
1x
SRC9
SRC8
BYTE 12 - RESERVED
BYTE13
Bit
7
Output(s)Affected
CPU_N8
Description / Function
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
6
CPU_N7
5
CPU_N6
4
CPU_N5
CPU CLK = N* Resolution
FSLatch
3
CPU_N4
2
CPU_N3
1
CPU_N2
0
CPU_N1
BYTE14
Bit
7
Output(s)Affected
CPUN0
Description / Function
fine tune CPUfrequency
Enablebit
0
1
Type
R/W
R/W
R/W
R/W
Power On
FSlatch
6
IB1
See IB table
Disable
0
0
0
0
0
0
0
5
IB0
4
NProgramming
Reserved
Reserved
Reserved
Reserved
Enable
3
2
1
0
BYTES 15, 16, 17 - PLL1 SPREAD SPECTRUM ADJUSTMENT
(DEFAULT 99.75 +/- 0.2%)
CONTROLREGISTERS
BYTE63 DEVICE ID
BIT[7:4] = 1H, BIT[3:0] = 6H
BYTE62 DEVICE ID+ REV
BIT[7:4] = 9H, BIT[3:0] = 0H
10
IDTCV169
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
Test Conditions
Min.
2
Typ.
—
Max.
Unit
V
3.3V ± 5%
3.3V ± 5%
VDD + 0.3
VIL
Input LOW Voltage
VSS - 0.3
0.7
VSS - 0.3
–5
—
0.8
V
VIH_FS
VIL_FS
IIH
LOW Voltage, HIGH Threshold
LOW Voltage, LOW Threshold
Input HIGH Current
For FSA.B.C test_mode
For FSA.B.C test_mode
VIN = VDD
—
VDD + 0.3
V
—
0.35
5
V
—
µ A
µ A
µ A
mA
mA
IIL1
Input LOW Current
VIN = 0V, inputs with no pull-up resistors
VIN = 0V, inputs with pull-up resistors
Full active, CL = full load
All differential pairs driven
All differential pairs tri-stated
VDD = 3.3V
–5
—
—
—
400
70
12
—
7
IIL2
Input LOW Current
–200
—
—
IDD3.3OP
IDD3.3PD
Operating Supply Current
Powerdown Current
—
—
—
—
—
(1)
FI
Input Frequency
—
14.31818
—
MHz
nH
LPIN
Pin Inductance(2)
—
CIN
Logic inputs
—
—
5
COUT
CINX
TSTAB
Input Capacitance(2)
Clock Stabilization(2,3)
Output pin capacitance
—
—
6
pF
XTAL_IN and TXAL OUT pins
From VDD power-up or de-assertion of PD to first clock
Triangular modulation
—
—
5
—
—
1.8
33
60
60
300
5
ms
KHz
ns
(2)
Modulation Frequency
30
—
TSU_SRC
SRC STOP response to OE#
SRC START response to OE#
CPU output enable after PD de-assertion
Fall time of PD
—
—
TDRIVE_SRC
—
—
ns
(2)
TDRIVE_PD
—
—
us
(2)
TFALL_PD
—
—
ns
(2)
TRISE_PD
Rise time of PD
—
—
5
ns
TDRIVE_CPU_STOP#(2)
TFALL_CPU_STOP#(2)
TRISE_CPU_STOP#(2)
CPU output enable after CPU_STOP# de-assertion
Fall time of CPU_STOP#
—
—
10
5
ns
—
—
ns
Rise time of CPU_STOP#
—
—
5
ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
11
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
(2)
VHIGH
VLOW
VOVS
Voltage HIGH
Statistical measurement on single-ended signal using
oscilloscope math function
660
–150
—
—
—
—
—
—
—
850
+150
1150
—
mV
(2)
Voltage LOW
Max Voltage(2)
Min Voltage(2)
Measurement on single-ended signal using absolute value
mV
VUDS
–300
250
—
VCROSS(ABS) Crossing Voltage (abs)(2)
550
mV
mV
ppm
d - VCROSS
ppm
Crossing Voltage (var)(2)
Variation of crossing over all edges
140
(2,3)
Static Error
See TPERIOD Min. - Max. values
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
—
—
—
—
—
0
2.4993
2.9991
3.7489
2.5133
3.016
3.77
TPERIOD
Average Period(3)
200MHz nominal / -0.5% spread
4.9985
—
5.0266
ns
166.66MHz nominal / -0.5% spread
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
5.9982
7.4978
9.997
—
—
—
6.032
7.54
10.0533
96MHz nominal
10.4135
2.4143
2.9141
3.6639
—
—
—
—
10.4198
—
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
—
—
200MHz nominal / -0.5% spread
166.66MHz nominal / -0.5% spread
4.9135
5.9132
—
—
—
—
TABSMIN
Absolute Min Period(2,3)
ns
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
96MHz nominal
7.4128
9.912
10.1635
175
—
—
—
—
—
—
—
—
—
tR
tF
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
VOL = 0.175V, VOH = 0.525V
700
700
125
ps
ps
ps
Fall Time(2)
175
d-tR
Rise Time Variation(2)
—
d-tF
dT3
Fall Time Variation(2)
Duty Cycle(2)
—
45
—
—
125
55
ps
%
Measurement from differential waveform
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
12
IDTCV169
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR,CONTINUED(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
Max.
100
Unit
(2)
Skew, CPU[1:0]
tSK3
Skew, CPU2(2)
VT = 50%
—
—
250
ps
Skew, SRC(2)
—
—
—
—
—
—
250
85
(2)
Jitter, Cycle to Cycle, CPU[1:0]
Jitter, Cycle to Cycle, CPU2(2)
tJCYC-CYC
Measurement from differential waveform
100
ps
Jitter, Cycle to Cycle, SRC(2)
Jitter, Cycle to Cycle, DOT96(2)
—
—
—
—
125
250
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
Max.
Unit
ppm
ns
ppm
StaticError(1,2)
ClockPeriod(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
30.009
30.1598
—
TPERIOD
29.991
29.991
2.4
—
VOH
VOL
IOH
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
IOL
OutputLOWCurrent
30
—
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
1
4
V/ns
V/ns
ns
Fallingedgerate
1
4
tR1
tF1
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
ns
dT1
Duty Cycle(1)
55
%
(1)
tSK1
Skew
VT = 1.5V
—
500
500
ps
tJCYC-CYC
Jitter, Cycle to Cycle(1)
VT = 1.5V
—
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
13
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICALCHARACTERISTICS,48MHZ,USB
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
ppm
StaticError(1,2)
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
TPERIOD
VOH
ClockPeriod(2)
20.8257
2.4
—
20.834
—
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-29
—
mA
-23
—
IOL
OutputLOWCurrent
29
mA
—
27
EdgeRate(1)
1
2
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
2
tR1
tF1
RiseTime(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.5
0.5
45
1.2
1.2
55
FallTime(1)
ns
dT1
Duty Cycle(1)
%
tJCYC-CYC
Jitter, Cycle to Cycle
—
350
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS-REF-14.318MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
14.318MHzoutputnominal
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
(1)
ppm
LongAccuracy
TPERIOD
VOH
Clock Period
69.827
2.4
—
69.855
—
OutputHIGHVoltage(1)
OutputLOWVoltage(1)
Output HIGH Current
V
VOL
IOL = 1mA
0.4
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
1
4
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
4
tR1
tF1
Rise Time(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
55
Fall Time(1)
ns
dT1
Duty Cycle(1)
Jitter, Cycle to Cycle(1)
%
tJCYC-CYC
VT = 1.5V
—
1000
ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
14
IDTCV169
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
OE#DE-ASSERTION
TheclocksamplestheOE#signalonarisingedgeofSRCclock.AfterdetectingtheOE#de-assertion,allcontrolledSRCclockswillbetristateontheirnext
hightolowtransition.
tSU_SRC
OE[9:1]#
SRC
SRC#
OE#ASSERTION
TheassertionoftheOE#signalistobesampledontherisingedgeoftheSRCfreerunningclockdomain.AfterdetectingOE#assertion,allcontrolledSRC
clocks willresumeinaglitchfreemanner.
tDRIVE_SRC
OE[9:1]#
SRC
SRC#
15
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PCISTOPFUNCTIONALITY
ThePCI_STOP#signalisonanactivelowinputcontrollingPCIandSRCoutputs.IfPCIF0andSRCclockscanbesettobefree-runningthroughSMBus
programming, theywillignore boththe PCI_STOP#pinandthe PCI_STOPregisterbit.
PCI_STOP#
CPU
CPU#
Normal
Normal
SRC
Normal
SRC#
Normal
Low
PCIF/PCI
33MHz
Low
USB
DOT96
Normal
Normal
DOT96#
Normal
Normal
REF
1
0
Normal
Normal
48MHz
48MHz
14.318MHz
14.318MHz
IREF * 6 or float
PCI_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
TheclocksamplesthePCI_STOP#signalonarisingedgeofPCIFclock.AfterdetectingthePCI_STOP#assertionlow,allPCI[3:0]andstoppablePCIF0
clocks willlatchlowontheirnexthightolowtransition. Afterthe PCIclocks are latchedlow, the SRCclock, (ifsettostoppable)willlatchhighatIREF *6(or
tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below.
tSU
PCI_STOP#
PCIF0 33MHz
PCI[3:0] 33MHz
PCI_STOP#-DE-ASSERTION
Thede-assertionofthePCI_STOP#signalistobesampledontherisingedgeofthePCIFfreerunningclockdomain.AfterdetectingPCI_STOP#de-assertion,
allPCIF[3:0], stoppable PCIF0andstoppable SRCclocks willresume ina glitchfree manner.
tSU
tDRIVE_SRC
PCI_STOP#
PCIF0 33MHz
PCI[3:0] 33MHz
16
IDTCV169
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
CPUSTOPFUNCTIONALITY
The CPU_STOP#signalis anactive lowinputcontrollingthe CPUoutputs. This signalcanbe assertedasynchronously.
CPU_STOP#
CPU
Normal
CPU#
Normal
Low
SRC
SRC#
Normal
Normal
PCIF/PCI
33MHz
USB
DOT96
Normal
Normal
DOT96#
Normal
Normal
REF
1
0
Normal
Normal
48MHz
48MHz
14.318MHz
14.318MHz
IREF * 6 or float
33MHz
CPU_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
AssertingCPU_STOP#pinstopsallCPUoutputsthataresettobestoppableaftertheirnexttransition.WhentheSMBusCPU_STOPtri-statebitcorresponding
totheCPUoutputofinterestisprogrammedtoa‘0’,CPUoutputwillstopCPU_True=HighandCPU_Complement=Low.WhentheSMBusCPU_STOP#
tri-statebitcorrespondingtotheCPUoutputofinterestisprogrammedtoa‘1’,CPUoutputswillbetri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - DE-ASSERTION (TRANSITION FROM ‘0’ TO ‘1’)
Withthede-assertionofCPU_STOP#allstoppedCPUoutputswillresumewithoutaglitch.Themaximumlatencyfromthede-assertiontoactiveoutputs
istwotosixCPUclockperiods.Ifthecontrolregistertristatebitcorrespondingtotheoutputofinterestisprogrammedto‘1’,thenthestoppedCPUoutputswill
be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.
CPU_STOP#
CPU
CPU#
CPU Internal
tDRIVE_CPU_Stop
10nS > 200mV
17
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PD, POWER DOWN
PDisanasynchronousactivehighinputusedtoshutoffallclockscleanlypriortoclockpower. WhenPDisassertedhigh,allsingle-endedclockswillbe
drivenlow, andCPU#andSRC#willbe leftfloating, before turningoffthe VCO. InPDde-assertionallclocks willstartwithoutglitches.
PD
0
CPU
Normal
CPU#
Normal
Float
SRC
Normal
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
USB
48MHz
Low
DOT96
Normal
DOT96#
Normal
Float
REF
14.318MHz
Low
1
IREF * 2 or float
IREF * 2 or float
IREF * 2 or float
PDASSERTION
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
18
IDTCV169
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PDDE-ASSERTION
tSTAB <1.8mS
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PD
<300μS, <200mV
19
IDTCV169
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
IDTCV
XXX
XX
X
Device Type
Package
Grade
Commercial Temperature Range
Blank
(0°C to +70°C)
Very Fine Pitch Quad Flat Pack
VFQFPN - Green
NL
NLG
Programmable FlexPC Clock for P4 Processor
169
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
logichelp@idt.com
20
相关型号：
©2020 ICPDF网 联系我们和版权申明