IDTCV174CPVG [IDT]
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR; 可编程FLEXPC时钟P4处理器
| 型号： | IDTCV174CPVG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| 文件： | 总21页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE FLEXPC
IDTCV174C
CLOCK FOR P4 PROCESSOR
DESCRIPTION:
FEATURES:
IDTCV174Cisa56pinclockdevice,incorporatingIntelCK505requirements
for the Intel advance P4 processor. The CPU output buffer is designed to
supportupto400MHzreferenceclockfortheCPU. ThischiphasthreePLLs
inside for CPU, SRC/PCI and 48MHz/DOT96 IO clocks.
• Compliant with Intel CK505
• Power management control suitable for low power applications
• One high precision PLL for CPU/SRC/PCI, SSC and N program-
ming
• One high precision PLL for SRC/PCI, SSC and N programming
• One high precision PLL for 96MHz/48MHz
• Push-pull IOs for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength
• Smooth transition for N programming
• Available in SSOP and TSSOP packages
OUTPUTS:
• 2*0.7V differential CPU CLK pair
• 7*0.7V differential SRC CLK pair
• One CPU_ITP/SRC differential clock pair
• One SRC0/DOT96 differential clock pair
• 6*PCI, 33.3MHz
KEYSPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 500ps
• 1*48MHz
• 1*REF
• 1*SATA
FUNCTIONALBLOCKDIAGRAM
REF
XTAL_IN
XTAL
CPU[1:0]
PLL1
SSC
N Programmable
CPU, SRC, PCI
Output Buffer
Stop Logic
Osc Amp
XTAL_OUT
CPU_ITP/SRC8
SDATA
SCLK
SM Bus
Controller
SRC[7:1]
SRC CLK
Output Buffer
Stop Logic
PLL3
SSC
N Programmable
PCI[4:0], PCIF5
SATA
CKPRWGD/PD#
CPU_STOP#
PCI_STOP#
Control
Logic
48MHz
Fixed PLL
PLL2
SRC5_EN, LTE
48MHz/96MHz
Output BUffer
ITP_EN
DOT96/SRC0
CR#_[F:A]
FSC,B,A
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 2006
1
© 2005 Integrated Device Technology, Inc.
DSC 6898/8
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
PCI0/CR#_A
VDD_PCI
1
SCL
SDA
56
55
2
PCI1/CR#_B
PCI2//LTE
3
REF/FSC/TEST_SEL
VDD_REF
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
4
5
PCI3
XTAL_IN
6
PCI4/SRC5_EN
PCIF5/ITP_EN
VSS_PCI
XTAL_OUT
VSS_REF
7
8
FSB/TEST_MODE
CKPWRGD/PD#
VDD_CPU
9
VDD_48MHz
USB_48/FSA
VSS_48MHz
VDD_IO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CPUT0
CPUC0
VSS_CPU
SRCT0/DOT96T
SRCC0/DOT96C
VSS_IO
CPUT1
CPUC1
VDD_CPU_IO
IO_VOUT
VDD_PLL3
SRCT1/SE1
SRCC1/SE2
VSS_PLL3
SRCT8/CPU_ITPT
SRCC8/CPU_ITPC
VDD_SRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
VSS_SRC
VDD_PLL3_IO
SATAT/SRCT2
SATAC/SRCC2
VSS_SRC
SRCT3/CR#_C
SRCC3/CR#_D
VDD_SRC_IO
SRCT4
SRCT6
SRCC6
VDD_SRC
PCI_STOP#/SRCT5
CPU_STOP#/SRCC5
SRCC4
TSSOP
TOP VIEW
2
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PINDESCRIPTION
Pin #
Name
Type
Description
1
PCI0/CR#_A
I/O
33.33MHz/SRC0,2 Differentialclockoutputenable,controlSRC0andSRC2,0=enable.Modeisselected
by SMBus control register. Default is PCI clock mode
2
3
VDD_PCI
PWR
I/O
3.3V
PCI1/CR#_B
33.33MHz/SRC1,2 Differentialclockoutputenable,controlSRC1andSRC4,0=enable.Modeisselected
by SMBus control register. Default is PCI clock mode
4
PCI2/LTE
PCI3
I/O
OUT
I/O
33.33MHz. High = overclocking disabled. Power-on latch.
5
33.33MHz
6
PCI4/SRC5_EN
PCIF5/ITP_EN
VSS_PCI
33.33MHz. Pin 29, 30 mode selection. Power on latch, high = SRC5, low = CPU and PCI Stop#
7
I/O
33.33MHz. Pin 38, 39 mode selection. Power on latch, high = CPU_ITP, low = SRC8
8
GND
PWR
I/O
GND
9
VDD_48
3.3V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
USB 48/FS_A
VSS_48
48MHz/ Frequency select, power on latch
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
I/O
GND
VDD_IO
0.8V
SRCT0/DOT96T
SRCC0/DOT96C
VSS_IO
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0
GND
VDD_PLL3
3.3V
SRCT1/SE1
SRCC1/SE2
VSS_PLL3
Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1.
Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1
GND
VDD_PLL3_IO
SRCT2/SATAT
SRCC2/SATAC
VSS_SRC
0.8V
Differentialoutputclock
Differentialoutputclock
GND
SRCT3/CR#_C
SRC clock/ SRC differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode selected by
SMBus control register. Default is SRC3.
25
SRCC3/CR#_D
I/O
SRC clock/ SRC differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode selected by
SMBus control register. Default is SRC3..
26
27
28
29
30
31
32
33
34
35
VDD_SRC_IO
SRCT4
PWR
OUT
OUT
I/O
0.8V
Differentialoutputclock
SRCC4
Differentialoutputclock
CPU_Stop#/SRCC5
PCI_Stop#/SRCT5
VDD_SRC
CPU stop, low = stop/ SRC clock. Mode selected by pin6, SRC5_EN.
I/O
PCI stop, low = stop/ SRC clock. Mode selected by pin6, SRC5_EN.
PWR
OUT
OUT
GND
I/O
3.3V
SRCC6
Differentialoutputclock
Differentialoutputclock
GND
SRCT6
VSS_SRC
SRCC7/CR#_E
SRCclock/SRCdifferentialclockoutputenable,controlSRC6,0=enable.ModeselectedbySMBuscontrol
register. DefaultisSRC7.
36
SRCT7/CR#_F
I/O
SRCclock/SRCdifferentialclockoutputenable,controlSRC8,0=enable.ModeselectedbySMBuscontrol
register. DefaultisSRC7.
37
38
39
VDD_SRC_IO
PWR
OUT
OUT
0.8V
SRCC8/CPU_ ITPC
SRCT8/CPU_ ITPT
SRC clock/CPU clock. Mode selected by pin7.
SRC clock/CPU clock. Mode selected by pin7.
40
IO_VOUT
OUT
V_IOadjustment
3
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION,CONTINUED
Pin #
41
Name
VDD_CPU_IO
CPUC1
Type
PWR
OUT
OUT
GND
OUT
OUT
PWR
IN
Description
0.8V
42
Differentialoutputclock
Differentialoutputclock
GND
43
CPUT1
44
VSS_CPU
CPUC0
45
Differentialoutputclock
Differentialoutputclock
3.3V
46
CPUT0
47
VDD_CPU
CKPWRGD/PD#
48
CKPWRGDpowergood,activeLOW,usedtolatchFSA,B,C,ITP_EN,TME,andSRC5_EN,activeHIGH.
After, becomes power down, LOW active.
49
50
51
52
53
54
FS_B/TestMode
VSS_REF
IN
GND
OUT
IN
Frequency Select at CKPWRGD assertion. Test Mode selection, see TEST_MODE selection table
GND
XTAL_OUT
XTALout
XTALin
3.3V
XTAL_IN
VDD_REF
PWR
I/O
REF/FS_C/TestSel
14.318MHz.FrequencySelectatCKPWRGDassertion.Selectstestmodeifpulledabove2VatCKPWRGD
assertion.
55
56
SDA
SCL
I/O
IN
SMBus clock
SMBus data
TESTMODESELECTION(1)
IfTEST_SELsampledabove2VatCKPWRGDactiveLOW
Test_Mode
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
PCI/F
REF/N
Hi-Z
REF
REF
Hi-Z
DOT_96/DOT_SSC
USB
REF/N
Hi-Z
1
0
REF/N
Hi-Z
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N, with VIH_FS and VIL_FS threshoulds.
FREQUENCYSELECTION
FSC, B, A
101
CPU
100
SRC[7:0]
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
DOT
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
001
133
100
48
96
011
166
100
48
96
010
200
100
48
96
000
266
100
48
96
100
333
100
48
96
110
400
100
48
96
111
Reserve
100
48
96
4
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ABSOLUTEMAXIMUMRATINGS(1)
RESOLUTION
Symbol
VDDA
Description
Min
Max
4.6
Unit
V
N Resolution (MHz)
0.500000
%
N =
200
200
250
200
200
250
200
200
3.3V Core Supply Voltage
CPU = 100MHz
CPU = 133MHz
CPU = 166MHz
CPU = 200MHz
CPU = 266MHz
CPU = 333MHz
CPU = 400MHz
SRC = 100MHz
0.5%
0.5%
0.4%
0.5%
0.5%
0.4%
0.5%
0.5%
0.666667
VDD
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
0.666667
TSTG
Storage Temperature
–65
0
+150
+70
+115
°C
°C
°C
V
1.000000
TAMBIENT
TCASE
Ambient Operating Temperature
Case Temperature
1.333333
1.333333
ESD Prot Input ESD Protection
Human Body Model
NOTE:
2000
2.000000
0.500000
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
SMPROTOCOL
INDEXBLOCKWRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
until Nth byte (byte count bit 30-37).
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
D2h
11-18
19
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
11-18
19
29-36
37
20
21-28
29
D3h
38-45
46
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Byte count, N (block read back of N
bytes)
38
39-46
47
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
5
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PLL3CONFIGTABLE(1)
PLL#_CFB[3,2,1,0]
Comments
PLL3 off, SRC1 = SRC_Main
PLL3 on, SRC1 = SRC_Main
only SRC1 sourced from PLL3
only SRC1 sourced from PLL3
only SRC1 sourced from PLL3
only SRC1 sourced from PLL3
only SRC1 sourced from PLL3
Reserved
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL3 Disabled
100MHz 0.5% SSC Stby
100MHz 0.5% SSC
100MHz 1.0% SSC
100MHz 1.5% SSC
100MHz 2.0% SSC
100MHz 2.5% SSC
Reserved
1394A 3.3V
only 1394A on SE1 and SE2
only 1394A on SE1, 1394B on SE2
only 1394B on SE1 and SE2
only 27MHz on SE1 and SE2
only 25MHz on SE1 and SE2
Reserved
1394A&B 3.3V
1394B 3.3V
27MHz, 3.3V
25MHz 3.3V
Reserved
Reserved
Reserved
Reserved
Reserved
NOTE:
1. PLL3 spread depend on byte4 bit0 and byte1 bit5, default -0.5%.
IO_VOUT [2:0] TABLE
DEVICE ID TABLE
000
001
010
011
100
101
110
111
0.3V
0.4V
0.5V
0.6V
0.7V
0.8V
0.9V
1V
ID3,ID2,ID1,ID0
Comments
0000
CK505 56 pin TSSOP
CK505 64 pin TSSOP
48 pin QFN
56 pin QFN
64 pin QFN
72 pin QFN
48 pin SSOP
56 pin SSOP
Reserved
CK505 YC
CK505 YC
0001
0010
CK505 YC
0011
CK505 YC
0100
CK505 YC
0101
CK505 YC
0110
CK505 YC
0111
CK505 YC
1000
CK505 Derivative (non YC)
1001
Reserved
1010
Reserved
IB TABLE
1011
Reserved
IB1, IB0
CPU Frequency
(N + 0.3333) * resolution
(N + 0.6666) * resolution
N * resolution
1100
Reserved
01
1101
Reserved
10
1110
Reserved
00, 11
1111
Reserved
6
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
N-PROGRAMMINGPROCEDURE
CPU
SRC
1. Power on CPU frequency = 200MHz. Resolution corresponding to
200MHz is 1.0
2. To change CPU frequency from 200MHz to 100MHz, divide 100 by 1.0-
(100 / 1.0 = 100 [decimal] = 64 [hex]).
3. Program Byte 17 with 64h. CPU frequency changes from 200MHz to
100MHz.
1. Power on SRC frequency = 100MHz.
2. To change SRC frequency from 100MHz to 50MHz, divide 50 by 0.5 (50
/ 0.5 = 100 [decimal] = 64 [hex]).
3. Program Byte 18 with 64h. SRC frequency changes from 100MHz to
50MHz.
CONTROLREGISTERS
BYTE 0
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
FSC
FSB
LatchedFSC
LatchedFSB
LatchedFSA
iAMT Mode
R
R
LatchedValue
LatchedValue
LatchedValue
HW M1 setting(1)
0
FSA
R
iAMT_EN
Reserved
SRC_SEL
Legacy Mode
Enabled
RW
SRC clock source
SATA source
PLL1, PLL3_CFG
tableapplies
PLL3, PLL3_CFG
tablenotapplicable
RW
0
1
0
SATA_SEL
PD_Restore
SRC_main
PLL2(2)
RW
RW
0
1
SMBUScontrolregisterssetting
afterthepowerdown
Powerondefault
Saveregistercontents
NOTES:
1. Sticky 1, can only be reset by power off.
2. 100MHz, no SSC.
BYTE 1
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC0_sel
PLL1_SSC_DC
PLL3_SSC_DC
PLL3_CFB3
PLL3_CFB2
PLL3_CFB1
PLL3_CFB0
PCI
Pin13/14modeselect
SSC mode selection
SSC mode selection
SRC0
DOT96
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
1
1
Downspread
Downspread
Centerspread
Centerspread
Only valid if Byte0 bit2 = 0
See PLL3_CFB table,
configurepin17,18outputmode
PCI select
PLL1
SRC, as byte0 bit2
BYTE 2
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
REF
USB_48
PCIF5
PCI4
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
PCI3
PCI2
PCI1
PCI0
7
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 3
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
SRC8/ITP
SRC7
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Tristate
Enabled
Enabled
Enabled
Enabled
Enabled
SRC6
SRC5
SRC4
BYTE 4
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC3
SATA/SRC2
SRC1
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
SSC Enable
SSC Enable
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
SRC0/DOT96
CPU1
CPU0
PLL1_SSC_ON
PLL3_SSC_ON
BYTE 5
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CR#_A
CR#_A control
CR#_B
Pin1modeselection
CR#_Acontrolselection
Pin3modeselection
PCI0 mode
SRC0
CR#_A mode
SRC2
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
PCI1mode
SRC1(1)
CR#_B mode
SRC4
CR#_B control
CR#_C
CR#_Bcontrolselection
Pin24 modeselection
CR#_Ccontrolselection
Pin25modeselection
CR#_Dcontrolselection
SRCT3mode
SRC0
CR#_C mode
SRC2
CR#_C control
CR#_D
SRCC3 mode
SRC1
CR#_D mode
SRC4
CR#_D control
NOTE:
1. Only when SRC1 is SRC Clock.
BYTE 6(1)
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CR#_E
CR#_F
Pin 35 mode selection, control SRC6
Pin 36 mode selection, control SRC8
SRCC7 mode
CR#_E mode
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
SRCT7mode
CR#_F mode
Reserved
Reserved
Reserved
Reserved
SSCD_STP_CRTL
SRC_STP_CRTL
If set, SSCD stop with PCI_STOP#
If set, SRCs stop with PCI_STOP#
Freerunning
Freerunning
Stoppable
Stoppable
NOTE:
1. STOP - CPUT and SRCT stay high, CPUC and SRCC stay low.
8
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 7
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Revision ID
Revision ID
Revision ID
Revision ID
VendorID
VendorID
VendorID
VendorID
0
0
0
0
0
1
0
1
BYTE 8
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Device_ID3
Device_ID2
Device_ID1
Device_ID0
R
R
See device ID table
R
R
RW
RW
RW
RW
0
0
0
0
SE1_OE
SE2_OE
OutputEnable
OutputEnable
Disabled
Disabled
Enabled
Enabled
BYTE 9
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
PCIF5 with PCI_STOP#
LTE_STRAP
Freerunning
Over-clockingEnable(Nprogramming)
Strengthcontrol
Freerunning
normal
stoppable
No overclocking
2x
RW
R
0
0
1
0
0
REFDriveStrength
1x
RW
RW
RW
Only valid when Byte9 bit3 is 1
Test Modeentrycontrol
Hi-Z
REF/N mode
Testmode,controlled
by byte9 bit 4
Normaloperation
2
1
0
IO_VOUT2
IO_VOUT1
IO_VOUT0
RW
RW
RW
1
0
1
ProgrammableIO_VOUT voltage
BYTES 10 + 11 - RESERVED
BYTE 12 - BYTE COUNT - DEFAULT 0x0D
BYTE13
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
48M
REF
Strengthcontrol
Strengthcontrol
Strengthcontrol
Strengthcontrol
Strengthcontrol
Strengthcontrol
Strengthcontrol
Strengthcontrol
1
1
1
1
1
1
1
1
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
PCIF5
PCI4
PCI3
PCI2
PCI1
PCI0
9
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE14
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
SRC skew selection
Reserved
250ps
400ps
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Reserved
SRC3, 4, 5, 6
Strength(outputimpedance)
Strength
17Ω
17Ω
17Ω
17Ω
17Ω
25Ω
25Ω
25Ω
25Ω
25Ω
SRC2, 7, 8
CPU strength
Strength
SRC0/ DOT strength
SRC1/ PLL3CLK Strength
Strength
Strength
BYTE 15, WATCH DOG(1)
Bit
7
Output(s)Affected
WatchDogEnable
Description / Function
WatchDogAlarmEnable
0
1
Type
RW
RW
R
Power On
Disabled
Enabled
0
0
6
WatchDogSelect
WatchDogHard/SoftAlarmSelect Hard Alarm Only Hard and Soft Alarm
5
WatchDogHardAlarmStatus
WatchDogSoftAlarmStatus
WatchDogcontrol
WatchDogHardAlarmStatus
WatchDogSoftAlarmStatus
WatchDogTimeBaseControl
WatchDog_1_AlarmTimer
Defaultis7*290ms
Normal
Normal
Alarm
Alarm
4
R
3
290msbase
1160msbase
RW
RW
RW
RW
0
1
1
1
2
WD_1_Timer2
1
WD_1_Timer1
0
WD_1_Timer0
NOTE:
1. Hard Alarm switch to HW FS frequency.
BYTE16
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
WDEAPD
Set Byte15 bit7 = 1 after Power Down
Disabled
Enabled
RW
0
to enable the watch dog after the power down
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
IB1
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
Incrementbit1, finetuneCPUfrequnecy
Incrementbit0
See IB table
See IB table
0
0
IB0
CPUN8
FS latch
BYTE 17 (PLL1)
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
CPUN7
CPUN6
CPUN5
CPUN4
CPUN3
CPUN2
CPUN1
CPUN0
RW
RW
RW
RW
RW
RW
RW
RW
CPU frequency = N*Resolution
(seeResolutiontable,
FS latch
N-ProgrammingProcedure)
10
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 18 (PLL3)
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PN 7
PN 6
PN 5
PN 4
PN 3
PN 2
PN 1
PN 0
RW
RW
RW
RW
RW
RW
RW
RW
SRC frequency = N*Resolution
(seeResolutiontable,
100MHz
N-ProgrammingProcedure)
BYTE 19, CLOCK SOURCE SELECTION, WRITEN AFTER STOP BIT
Bit
Output(s) affected
Description/ Function
0
1
Type
Power On
Will be reset to O
CPU Mode is
CPU Mode is
based on SFS
7
CPU MODE Control
RW
0
during the Hard Alarm
based on Hardware SFS
6
5
4
SFSC
SFSB
SFSA
RW
RW
RW
LATCH
Latch
Latch
Power
3
N programming enable
enable
disable
PLL2
RW
on LTE latch
controlled by
PLL3_CFB[3:0]
and byte0 bit2
Follow by te1 bit0
-
2
SRC1 source
RW
0
1
0
PCI source
Reserv ed
PLL2
-
RW
-
0
0
-
11
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
DCOPERATINGCHARACTERISTICS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VDD_3.3
Supply VoltageOperating Supply Current
5 %
3.125
3.465
V
VIH
VIL
Input HIGH Voltage (SE)(1)
Input LOW Voltage (SE)(1)
2
VDD + 0.3
0.8
V
V
VSS - 0.3
VIH_FS_Test
Input HIGH Voltage (SE)(2)
2
VDD + 0.3
V
VIH_FS_Normal
VIL_FS_Normal
IIL
Input HIGH Voltage (FS)(2)
0.7
VSS - 0.3
–5
1.5
0.35
+5
—
V
Input LOW Voltage (FS)(2)
V
Input LeakageCurrent(3)
0 < VIN < VDD
IOH = –1 mA
IOL = 1 mA
µA
V
VOH
Output HIGH Voltage (SE)(4)
Output LOW Voltage (SE)(4)
2.4
—
VOL
.4
V
VDD_IO
LOW Voltage Differential
0.72
1.5
—
0.88
5
V
CIN
Input Pin Capacitance
pF
pF
mA
mA
mA
mA
mA
mA
mA
mA
COUT
Output Pin Capacitance
6
IDD_CFG1_3.3V
IDD_CFG2_3.3V
IDD_CFG3_3.3V
IDD_IO_O.8V
IDD_PWRDWN_3.3V
IDD_PWRDWN_0.8V
IDD_M1_3.3V
IDD_M1_0/8V
Operating Supply Current, default configuration
Operating Supply Current, PLL3 differential out
Operating Supply Current, PLL3 single-ended out
Differential IO Current, all outputs enabled
Power Down Supply Current
Power Down Supply Current
MT Mode Supply Current
—
250
250
250
80
—
—
25
—
1
—
0.1
25
—
MT Mode Supply Current
—
0.8
NOTES:
1. All inputs referenced to 3.3V power suppply.
2. Frequency select inputs which have tri-level input.
3. Input leakage current does not include inputs with pull-up or pull-down resistors.
4. Signal edge is required to be monotonic when transitioning through this region.
12
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 DIFFERENTIAL
PAIR(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
Parameter
Voltage HIGH(2)
Voltage LOW(2)
Max Voltage(2)
Min Voltage(2)
Test Conditions
Min.
Typ.
Max.
Unit
VHIGH
VLOW
VOVS
Statistical measurement on single-ended signal using
oscilloscope math function
660
–150
—
—
—
—
—
—
—
850
+150
1150
—
mV
Measurement on single-ended signal using absolute value
mV
VUDS
–300
250
—
VCROSS(ABS) Crossing Voltage (abs)(2)
550
140
mV
mV
ppm
d - VCROSS
ppm
Crossing Voltage (var)(2)
Static Error(2,3)
Variation of crossing over all edges
See TPERIOD Min. - Max. values
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
—
—
—
—
—
0
2.4993
2.9991
3.7489
2.5133
3.016
3.77
TPERIOD
Average Period(3)
200MHz nominal / -0.5% spread
4.9985
—
5.0266
ns
166.66MHz nominal / -0.5% spread
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
5.9982
7.4978
9.997
—
—
—
6.032
7.54
10.0533
96MHz nominal
10.4135
2.4143
2.9141
3.6639
—
—
—
—
10.4198
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
—
—
—
200MHz nominal / -0.5% spread
166.66MHz nominal / -0.5% spread
4.9135
5.9132
—
—
—
—
TABSMIN
Absolute Min Period(2,3)
ns
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
96MHz nominal
7.4128
9.912
10.1635
175
—
—
—
—
—
—
—
—
—
tR
tF
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
VOL = 0.175V, VOH = 0.525V
700
700
125
ps
ps
ps
Fall Time(2)
175
d-tR
Rise Time Variation(2)
—
d-tF
dT3
Fall Time Variation(2)
Duty Cycle(2)
—
45
—
—
125
55
ps
%
Measurement from differential waveform
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
13
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR,CONTINUED(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
Parameter
Skew, CPU[1:0](2)
Test Conditions
Min.
—
Typ.
—
Max.
100
Unit
tSK3
Skew, CPU2(2)
VT = 50%
—
—
250
ps
Skew, SRC(2)
—
—
—
—
—
—
250
85
Jitter, Cycle to Cycle, CPU[1:0](2)
Jitter, Cycle to Cycle, CPU2(2)
tJCYC-CYC
Measurement from differential waveform
100
ps
Jitter, Cycle to Cycle, SRC(2)
Jitter, Cycle to Cycle, DOT96(2)
—
—
—
—
125
250
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
Max.
Unit
ppm
ns
ppm
StaticError(1,2)
ClockPeriod(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
30.009
30.1598
—
TPERIOD
29.991
29.991
2.4
—
VOH
VOL
IOH
Output HIGH Voltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
1
4
V/ns
V/ns
ns
Fallingedgerate
1
4
tR1
tF1
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
55
FallTime(1)
ns
dT1
Duty Cycle(1)
Skew(1)
%
tSK1
VT = 1.5V
—
250
500
ps
tJCYC-CYC
Jitter, Cycle to Cycle(1)
VT = 1.5V
—
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
14
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICALCHARACTERISTICS,48MHZ,USB
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
ppm
StaticError(1,2)
TPERIOD
VOH
ClockPeriod(2)
20.8257
2.4
—
20.834
—
Output HIGH Voltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-29
—
mA
-23
—
IOL
OutputLOWCurrent
29
mA
—
27
EdgeRate(1)
1
2
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
2
tR1
tF1
RiseTime(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.5
0.5
45
1.2
1.2
55
FallTime(1)
ns
dT1
Duty Cycle(1)
%
tJCYC-CYC
Jitter, Cycle to Cycle
—
350
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS-REF-14.318MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
14.318MHzoutputnominal
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
ppm
LongAccuracy(1)
TPERIOD
VOH
Clock Period
69.827
2.4
—
69.855
—
OutputHIGHVoltage(1)
OutputLOWVoltage(1)
Output HIGH Current
V
VOL
IOL = 1mA
0.4
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
1
4
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
4
tR1
tF1
Rise Time(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
55
Fall Time(1)
Duty Cycle(1)
Jitter, Cycle to Cycle(1)
ns
dT1
%
tJCYC-CYC
VT = 1.5V
—
1000
ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
15
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
MISC. AC TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Unit
TSTABLE
All Clock Stabilization from Power-Up
—
<1.8
ns
TDRIVE_SRC
TDRIVE_PCI
SRC Output Driven After PCI_STOP# De-assertion
PCI Output Driven After PCI_STOP# De-assertion
SRC Output Driven After CR# De-assertion
—
—
—
—
—
—
15
15
ns
us
ns
ns
us
ns
TDRIVE_CR#
15
TDRIVE_PWRDWN
TRISE_Control_Sig
TFALL_Control_Sig
Differential Output Enable after PWRDWN De-assertion
Rise Time for All Control Inputs (LVTTL 20-80%)
Fall time for All Control Inputs (LVTTL 20-80%)
300
10
10
16
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PCISTOPFUNCTIONALITY
PCI_STOP#
SRC
Normal
High
SRC#
Normal
Low
PCI
33MHz
Low
1
0
PCI_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
tSU
PCI_STOP#
PCIF5 33MHz
PCI[4:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - DE-ASSERTION (TRANSITION FROM '0' TO '1')
tSU
tDRIVE_SRC
PCI_STOP#
PCIF5 33MHz
PCI[4:0] 33MHz
SRC 100MHz
SRC# 100MHz
17
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
CPUSTOPFUNCTIONALITY
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU_STOP#
CPU
Normal
High
CPU#
Normal
Low
1
0
CPU_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
AssertingCPU_STOP#pinstopsallCPUoutputsthataresettobestoppableaftertheirnexttransition.WhentheSMBusCPU_STOPtri-statebitcorresponding
totheCPUoutputofinterestisprogrammedtoa‘0’,CPUoutputwillstopCPU_True=HighandCPU_Complement=Low.WhentheSMBusCPU_STOP#
tri-statebitcorrespondingtotheCPUoutputofinterestisprogrammedtoa‘1’,CPUoutputswillbetri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - DE-ASSERTION (TRANSITION FROM ‘0’ TO ‘1’)
Withthede-assertionofCPU_STOP#allstoppedCPUoutputswillresumewithoutaglitch.Themaximumlatencyfromthede-assertiontoactiveoutputs
istwotosixCPUclockperiods.Ifthecontrolregistertristatebitcorrespondingtotheoutputofinterestisprogrammedto‘1’,thenthestoppedCPUoutputswill
be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.
CPU_STOP#
CPU
CPU#
CPU Internal
tDRIVE_CPU_Stop
10nS > 200mV
18
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PD#ASSERTION
PD#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
PD#DE-ASSERTION
tSTABLE <1.8mS
PD#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
19
IDTCV174C
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
IDTCV
XXX
XX
X
Device Type
Package
Grade
CommercialTemperatureRange
Blank
(0°Cto+70°C)
PVG
PAG
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
Programmable FlexPC Clock for P4 Processor
174C
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
logichelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
20
IDTCV174C
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
May 22, 2006
Final Release.
21
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