MPC949FAR2 [IDT]

Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52;


型号：	MPC949FAR2
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 PC 驱动逻辑集成电路
文件：	总4页 (文件大小：272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

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See Upgrade Product – MPC9449

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The MPC949 is a low voltage CMOS, 15 output clock buffer. The 15

outputs can be configured into a standard fanout buffer or into 1X and

1/2X combinations. The device features a low voltage PECL input, in

addition to its LVCMOS/LVTTL inputs, to allow it to be incorporated into

larger clock trees which utilize low skew PECL devices (see the

MC100EP111 data sheet) in the lower branches of the tree. The fifteen

outputs were designed and optimized to drive 50Ω series or parallel ter-

minated transmission lines. With output to output skews of 350ps the

MPC949 is an ideal clock distribution chip for synchronous systems

which need a tight level of skew from a large number of outputs. For a

similar product with a smaller fanout and package consult the MPC946

data sheet.

LOW VOLTAGE

1:15 PECL TO

LVCMOS CLOCK DRIVER

• Low Voltage PECL Clock Input

• 2 Selectable LVCMOS/LVTTL Clock Inputs

• 350ps Maximum Output to Output Skew

• Drives up to 30 Independent Clock Lines

• Maximum Output Frequency of 160MHz

• High Impedance Output Enable

• 52–Lead LQFP Packaging

FA SUFFIX

52–LEAD LQFP PACKAGE

CASE 848D

• 3.3V V_CCSupply

With an output impedance of approximately 7Ω, in both the HIGH and

the LOW logic states, the output buffers of the MPC949 are ideal for driv-

ing series terminated transmission lines. More specifically each of the 15

MPC949 outputs can drive two series terminated transmission lines. With

this capability, the MPC949 has an effective fanout of 1:30 in applications

using point–to–point distribution schemes.

The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are

generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability

to allow the user to select the ratio of 1X outputs to 1/2X outputs.

Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to

provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the

TCLK1 input is selected. The PCLK_Sel input will select the PECL input clock when driven HIGH.

All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the

Dsel pins will select the 1X output. The MR/OE input will reset the internal flip flops and tristate the outputs when it is forced HIGH.

The MPC949 is fully 3.3V compatible. The 52 lead LQFP package was chosen to optimize performance, board space and cost

of the device. The 52–lead LQFP has a 10x10mm body size with a 0.65mm pin spacing.

Rev 3

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

619

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC949

Figure 1. Logic Diagram

Figure 2. 52–Lead Pinout (Top View)

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MPC949

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FUNCTION TABLE

Input

PIN DESCRIPTION

Pin Name

Function

TCLK_Sel

PCLK_Sel

Dseln

TCLK0

TCLKn

÷1

TCLK1

PCLK

÷2

TCLK_Sel

Select pin to choose TCKL0 or TCLK1

LVCMOS/LVTTL clock inputs

(Int Pulldown)

TCLK0:1

MR/OE

Enabled

Hi–Z

(Int Pullup)

PCLK

(Int Pulldown)

True PECL clock input

PCLK

(Int Pullup)

Complement PECL clock input

1x or 1/2x input divide select pins

Internal reset and output tristate control pin

Select Pin to choose TCLK or PCLK

Dseln

(Int Pulldown)

MR/OE

(Int Pulldown)

PCLK_Sel

(Int Pulldown)

620

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC949

ABSOLUTE MAXIMUM RATINGS*

Symbol

Parameter

Min

–0.3

TBD

–40

Max

Unit

Supply Voltage

Input Voltage

Input Current

4.6

+ 0.3

TBD

125

°C

Stor

Storage Temperature Range

Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those

indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.

DC CHARACTERISTICS (T_A= 0° to 70°C, V_CC= 3.3V 5%)

Symbol

Characteristic

Min

Typ

Max

3.60

0.8

Unit

Condition

Input HIGH Voltage

Input LOW Voltage

(Except PECL_CLK)

2.0

Peak–to–Peak Input Voltage

Common Mode Range

Output HIGH Voltage

Output LOW Voltage

Input Current

PECL_CLK

300

1000

CMR

– 2.0

– 0.6

Note 1.

2.5

= –20mA (Note 2.)

= 20mA (Note 2.)

0.4

120

µA

Note 3.

Input Capacitance

Power Dissipation Capacitance

Per Output

Maximum Quiescent Supply Current

1. V

is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within

CMR

the V

range and the input swing lies within the V specification.

CMR

2. The MPC949 can drive 50Ω transmission lines on the incident edge. Each output can drive one 50Ω parallel terminated transmission line to

the termination voltage of V = V /2. Alternately, the device drives up to two 50Ω series terminated transmission lines.

3. Inputs have pull–up/pull–down resistors which affect input current.

AC CHARACTERISTICS (T_A= 0° to 70°C, V_CC= 3.3V 5%)

Symbol

Characteristic

Maximum Input Frequency

Propagation Delay

Min

Typ

Max

Unit

MHz

Condition

Note 4.

160

max

PLH

PECL_CLK to Q

TTL_CLK to Q

4.0

4.2

6.5

7.5

9.0

10.6

Note 4.

Propagation Delay

PECL_CLK to Q

TTL_CLK to Q

3.8

4.0

6.2

7.2

8.6

10.5

Note 4.

PHL

Output–to–Output Skew

Part–to–Part Skew

300

350

Note 4.

Note 5.

sk(o)

PECL_CLK to Q

TTL_CLK to Q

1.5

2.0

2.75

4.0

sk(pp)

Output Enable Time

Output Disable Time

Output Rise/Fall Time

Note 4.

PZL PZH

Note 4.

PLZ PHZ

t , t

0.10

1.0

0.8V to 2.0V

4. Driving 50Ω transmission lines terminated to V /2.

5. Part–to–part skew at a given temperature and voltage.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

621

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC949

APPLICATIONS INFORMATION

Driving Transmission Lines

VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V

The MPC949 clock driver was designed to drive high speed

signals in a terminated transmission line environment. To pro-

vide the optimum flexibility to the user, the output drivers were

designed to exhibit the lowest impedance possible. With an

output impedance of approximately 10Ω the drivers can drive

either parallel or series terminated transmission lines. For

more information on transmission lines the reader is referred to

application note AN1091 in the Timing Solutions data book

(DL207/D).

At the load end the voltage will double, due to the near unity

reflection coefficient, to 2.8V. It will then increment towards the

quiescent 3.0V in steps separated by one round trip delay (in

this case 4.0ns).

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In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a point–to–

point scheme either series terminated or parallel terminated

transmission lines can be used. The parallel technique termi-

nates the signal at the end of the line with a 50Ω resistance to

VCC/2. This technique draws a fairly high level of DC current

and thus only a single terminated line can be driven by each

output of the MPC949 clock driver. For the series terminated

case however there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 3 illustrates

an output driving a single series terminated line vs two series

terminated lines in parallel. When taken to its extreme the fan-

out of the MPC949 clock driver is effectively doubled due to its

capability to drive multiple lines.

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Figure 4. Single versus Dual Waveforms

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Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 5 should be used. In this case the series terminating

resistors are reduced such that when the parallel combination

is added to the output buffer impedance the line impedance is

perfectly matched.

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Figure 3. Single versus Dual Transmission Lines

The waveform plots of Figure 4 show the simulation results

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of an output driving a single line vs two lines. In both cases the

drive capability of the MPC949 output buffers is more than suf-

ficient to drive 50Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta

of only 43ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used exclu-

sively to maintain the tight output–to–output skew of the

MPC949. The output waveform in Figure 4 shows a step in the

waveform, this step is caused by the impedance mismatch

7Ω + 36Ω ꢀ 36Ω = 50Ω ꢀ 50Ω

25Ω = 25Ω

Figure 5. Optimized Dual Line Termination

SPICE level output buffer models are available for engi-

seen looking into the driver. The parallel combination of the neers who want to simulate their specific interconnect

43Ω series resistor plus the output impedance does not match schemes. In addition IV characteristics are in the process of

the parallel combination of the line impedances. The voltage being generated to support the other board level simulators in

wave launched down the two lines will equal:

general use.

622

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

MPC949FAR2 [IDT]

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