QS5V991-5JRI [IDT]
PLL Based Clock Driver, QS5 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | QS5V991-5JRI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, QS5 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQCC32, PLASTIC, LCC-32 驱动 逻辑集成电路 |
| 文件： | 总7页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION
NOTE
PROGRAMMING TURBOCLOCK™
QS5991, QS5992, QS5993,
QS5V991, AND QS5V993
AN-226
INTRODUCTION
PROGRAMMING THE OUTPUT SKEW
Asnewtechnologydemandshigh-performancedesign,thedistribution
The outputs of TurboClock™ are organized in four banks of 2 outputs
ofhigh-speedclockhas become a difficulttaskforthe systemdesigners. each(nQ1,nQ0).Eachoutputpairis programmedwiththe corresponding
TurboClock™ provides the design engineers with the opportunities to Function/SkewSelect(nF1,nF0)inputs.Theinputs canbetiedHigh,Low,
overcome the manychallengingissues ofclockskew,andclockmultipli- or left unconnected to Mid level (an internal resistor network will bias the
cationanddivision.Thefamilyoffers5Vand3.3Vproductsin32-pinPLCC signallevelto0.5VCC).These 3-levelinputs allowa totalofnine different
and28-pinQSOP packages:
outputselections.Inthedatasheet,theSkewSelectionTableforOutputPairs
(reproducedinthe ControlSummaryTable)shows the listofoutputs from
eachpairwhenanyzeroskewoutputisusedasfeedback.Notethatoutput
pair#1and#2sharethesameoutputcharacteristics,andskewadjustment
for pair #4 is not available for QS5993 and QS5V993.
– QS5991 (5V, TTL outputs in PLCC)
– QS5992 (5V, CMOS outputs in PLCC)
– QS5993 (5V, TTL outputs in QSOP)
– QS5V991 (3.3V, LVTTL outputs in PLCC)
– QS5V993 (3.3V, LVTTL outputs in QSOP)
ThefirststepinprogrammingistodeterminetheVCOfrequency(FNOM)
basedonthe REFinputfrequency,andthe designedoutputfrequencies.
The outputpair1Qand2Qwillalways be equaltoVCOfrequency.When
anundividedoutputis usedas feedback, the VCOoperates atthe same
BothQS5991andQS5992arepin-compatibletoCypressCY7B991and
CY7B992,respectively.Figure 1shows the TurboClockblockdiagrams
fordifferentproductvariants.
FIGURE1:TURBOCLOCKBLOCKDIAGRAMS
sOE
sOE
QS5991
QS5992
QS5V991
QS5993
QS5V993
1Q0
1Q1
1Q0
1Q1
SKEW
SKEW
SELECT
SELECT
3
3
3
3
1F
1F
0:1
0:1
2Q0
2Q1
2Q
2Q
0
1
SKEW
SELECT
SKEW
SELECT
3
3
3
3
REF
FB
REF
FB
PLL
3
PLL
3
2F0:1
2F0:1
3Q
0
3Q0
3Q1
SKEW
SELECT
SKEW
SELECT
FS
FS
3
3
3
3
3Q1
3F0:1
3F0:1
4Q0
4Q1
4Q
4Q
0
1
SKEW
SELECT
3
3
4F
0:1
1
c /-
1999 Integrated Device Technology, Inc.
DSC-5838/-
PROGRAMMINGTURBOCLOCKQS5991,QS5992,QS5993,QS5V991,ANDQS5V993
APPLICATIONNOTEAN-226
TheflexibilityofTurboClockisfurtherenhancedbyusingaskewedoutput
as feedback.Forinstance,iffeedbackis 3Qand3F1:0=ML(–2tU),the 2Q
outputwillhave zeroskewwhen2F1:0 =LH(–2tU)since the actualoutput
skewat2Qiscalculatedfromtheprogrammed2Qoutputskew(–2tU)minus
the feedbackskew(–2tU).If2F1:0 =LL,thenthe actualoutputskewat2Q
is–2tU[–4tU–(–2tU)].TheOutputConfigurationtablesshowallthepossible
outputconfigurations(skewadjustment,frequencymultiplication/division)
with different feedbacks. Tables 1 through 3 hold true for 1Q output
configurations ifFBis 2Q.Thefirstcolumninthetables settheskewofthe
feedback.Eachoutputpairhasninepossibleoutputcombinationsforagiven
FB(listed immediately on the right-hand side of the FB skew) by setting
differentlevels toFunctionSelectpairs (nF1:0).
frequency as REF (or FB). If a divide-by-2 or divide-by-4 output is used
as feedback,the VCOwilloperate attwoorfourtimes the REFfrequency
since the PLL will always try to align the frequency and phase of FB with
REF.(Whenthedivide-by-2ordivide-by-4outputis usedas feedback,the
FB is running at one-half or one-fourth the frequency of other outputs.
Therefore, the other outputs are actually two or four times the REF
frequency.)
The secondstepis todecide the settingforFSandnF1:0 controlinputs
basedontheVCOfrequencyanddesiredoutputskew.Thedesiredoutput
skew will be a multiple of the Time Unit (tU) calculated from the PLL
Programmable SkewRange andResolutionTable.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
Skew (Pair #1, #2)
Skew (Pair #3)
Divide by 2
–6tU
Skew (Pair #4) (1)
Divide by 2
–6tU
LL
–4tU
–3tU
LM
LH
–2tU
–4tU
–4tU
ML
MM
MH
HL
–1tU
–2tU
–2tU
Zero Skew
1tU
Zero Skew
2tU
Zero Skew
2tU
2tU
4tU
4tU
HM
HH
3tU
6tU
6tU
4tU
Divide by 4
Inverted
NOTE:
1. Skew (pair #4) is not applicable for QS5993 and QS5V993.
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW
1/(44 x FNOM)
25 to 35MHz
25 to 35MHz
FS = MID
1/(26 x FNOM)
35 to 60MHz
35 to 60MHz
FS = HIGH
1/(16 x FNOM)
60 to 100 MHz
60 to 85 MHz
Time Unit (tU)
VCO Frequency (FNOM)
QS5991, QS5992, and QS5993
QS5V991 and QS5V993
2
PROGRAMMINGTURBOCLOCKQS5991,QS5992,QS5993,QS5V991,ANDQS5V993
APPLICATIONNOTEAN-226
OBTAININGMAXIMUMVCOFREQUENCYOPERATION
FORQS5991,QS5992,ANDQS5993
REF
REF
50 MHz
25 MHz
FB
FB
50 MHz
25 MHz
REF
REF
4Q0
4Q1
4Q0
4Q1
100 MHz
50 MHz
100 MHz
25 MHz
FS
FS
4F0
4F1
3F0
3F1
4F0
4F1
3F0
3F1
3Q0
3Q1
QS5991 3Q0
QS5991
QS5992
QS5993
3Q1
QS5992
QS5993
2Q0
2Q1
2Q0
2Q1
100 MHz
100 MHz
100 MHz
100 MHz
2F0
2F1
1F0
2F0
2F1
1F0
1Q0
1Q1
1Q0
1Q1
1F1
1F1
TEST
TEST
Figure 2. Wiring Diagram and Frequency Multiply by two with
3F[1:0] = LL.
Figure 3. Wiring Diagram and Frequency Multiply by four with
3F[1:0] = HH.
Figure2demonstratestheQS5991,QS5992,andQS5993configuredfor
Figure3showstheQS5991,QS5992andQS5993configuredforgettingmax
gettingmaxoutputat100MHz. The 3Q0outputis programmedtodivide by outputat100MHz. The3Q0outputisprogrammedtodividebyfourandisfed
twoandisfedbacktoFB. ThiscausesthePLLtoincreaseitsfrequencyuntil backtoFB. ThiscausesthePLLtoincreaseitsfrequencyuntil3Q0and3Q1
3Q0and3Q1outputsarelockedat50MHzwhile1Qx,2Qxand3Qxoutputs outputsarelockedat25MHzwhile1Qx,2Qxand4Qxoutputsrunat100MHz.
runat100MHz.The1Qx,2Qxand4Qxoutputsareskewedbyprogramming The1Qx,2Qxand3Qxoutputsareskewedbyprogrammingtheirselectinputs
theirselectinputsaccordingly(RefertoTable4formoredetails.)NotethatFS accordingly(RefertoTable5formoredetails.)NotethatFSpinisconnected
pinisconnectedtoHighforfastestfrequencyoutputrange.
toHighforfastestfrequencyoutputrange.
REF
50 MHz
FB
50 MHz
REF
FS
4Q0
4Q1
50 MHz
4F0
4F1
100 MHz
3Q0
3Q1
QS5991
QS5992
3F0
3F1
2Q0
2Q1
100 MHz
100 MHz
2F0
2F1
1F0
1Q0
1Q1
1F1
TEST
Figure 4. Wiring Diagram and Frequency Multiply by two with
4F[1:0] = LL.
Figure4illustratestheQS5991andQS5992configuredforgettingmaxoutput
at100MHz. The 4Q0outputis programmedtodivide bytwoandis fedback
toFB. ThiscausesthePLLtoincreaseitsfrequencyuntil4Q0and4Q1outputs
are locked at 50 MHz while 1Qx, 2Qx and 3Qx outputs run at 100 MHz. The
1Qx, 2Qx and 3Qx outputs are skewed by programming their select inputs
accordingly(RefertoTable6formoredetails.)NotethatFSpinisconnected
toHighforfastestfrequencyoutputrange.
3
PROGRAMMINGTURBOCLOCKQS5991,QS5992,QS5993,QS5V991,ANDQS5V993
APPLICATIONNOTEAN-226
OBTAININGMAXIMUMVCOFREQUENCYOPERATION
FORQS5V991ANDQS5V993
REF
REF
42.5 MHz
21.25 MHz
FB
FB
42.5 MHz
21.25 MHz
REF
REF
4Q0
4Q1
4Q0
4Q1
85 MHz
85 MHz
FS
FS
4F0
4F1
3F0
3F1
4F0
4F1
3F0
3F1
42.5 MHz
3Q0
QS5V991 3Q1
QS5V993
21.25 MHz
3Q0
3Q1
QS5V991
QS5V993
2Q0
2Q1
2Q0
2Q1
85 MHz
85 MHz
85 MHz
85 MHz
2F0
2F1
1F0
2F0
2F1
1F0
1Q0
1Q1
1Q0
1Q1
1F1
1F1
TEST
TEST
Figure 5. Wiring Diagram and Frequency Multiply by two with
3F[1:0] = LL.
Figure 6. Wiring Diagram and Frequency Multiply by four with
3F[1:0] = HH.
Figure6showstheQS5V991andQS5V993configuredforgettingmaxoutput
at 85 MHz. The 3Q0 output is programmed to divide by four and is fed back
toFB. ThiscausesthePLLtoincreaseitsfrequencyuntil3Q0and3Q1outputs
arelockedat21.25MHzwhile1Qx,2Qxand4Qxoutputsrunat85MHz.The
1Qx, 2Qx and 3Qx outputs are skewed by programming their select inputs
accordingly(RefertoTable5formoredetails.)NotethatFSpinisconnected
toHighforfastestfrequencyoutputrange.
Figure5demonstratestheQS5V991andQS5V993configuredforgetting
max output at 85 MHz. The 3Q0 output is programmed to divide by two and
isfedbacktoFB. ThiscausesthePLLtoincreaseitsfrequencyuntil3Q0and
3Q1 outputs are locked at 42.5 MHz while 1Qx, 2Qx and 3Qx outputs run at
85MHz. The 1Qx, 2Qx and 4Qx outputs are skewed by programming their
selectinputsaccordingly(RefertoTable4formoredetails.)NotethatFSpin
isconnectedtoHighforfastestfrequencyoutputrange.
REF
42.5 MHz
FB
42.5 MHz
REF
42.5 MHz
85 MHz
4Q0
FS
4Q1
4F0
4F1
3Q0
3Q1
QS5V991
3F0
3F1
2Q0
85 MHz
85 MHz
2F0
2Q1
2F1
1Q0
1Q1
1F0
1F1
TEST
Figure 7. Wiring Diagram and Frequency Multiply by two with
4F[1:0] = LL.
Figure7illustratestheQS5V991configuredforgettingmaxoutputat85MHz.
The 4Q0 output is programmed to divide by two and is fed back to FB. This
causesthePLLtoincreaseitsfrequencyuntil4Q0and4Q1outputsarelocked
at 42.5 MHz while 1Qx, 2Qx and 3Qx outputs run at 85 MHz. The 1Qx, 2Qx
and3Qxoutputsareskewedbyprogrammingtheirselectinputsaccordingly
(RefertoTable8formoredetails.)NotethatFSpinisconnectedtoHighforfastest
frequencyoutputrange.
4
PROGRAMMINGTURBOCLOCKQS5991,QS5992,QS5993,QS5V991,ANDQS5V993
APPLICATIONNOTEAN-226
OBTAINING MINIMUM VCO FREQUENCY OPERATION FOR QS5991, QS5992,
QS5993, QS5V991, AND QS5V993
25MHz with 25MHz REF input if there is no divider in the feedback loop.
However,ifthe divided-by-fouris usedas a feedback,the inputfrequency
is limitedbythe minimumREFinputat10MHzandthe VCOwilloperate at
fourtimes the frequency(40MHz).
The VCO can operate at 25MHz minimum frequency with less than a
25MHzREFinputwithdivided-by-twomode. Ifthedivided-by-twois used
as a feedback,the REFinputcanbe as lowas 12.5MHZandthe VCOwill
operate at twice the REF frequency (25MHz). The VCO will operate at
OUTPUT CONFIGURATION TABLES
TABLE 1. FB = 1Q. 2Q OUTPUT CONFIGURATIONS WITH DIFFERENT 2F(1:0)
FB
1F(1:0)
LL
Output at 2F(1:0)
LL
LM
1tU
LH
2tU
ML
3tU
MM
4tU
MH
5tU
HL
6tU
5tU
4tU
3tU
2tU
1tU
0tU
–1tU
–2tU
HM
7tU
6tU
5tU
4tU
3tU
2tU
1tU
0tU
–1tU
HH
8tU
7tU
6tU
5tU
4tU
3tU
2tU
1tU
0tU
0tU
LM
LH
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
0tU
1tU
2tU
3tU
4tU
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
0tU
1tU
2tU
3tU
ML
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
0tU
1tU
2tU
MM
MH
HL
–1tU
–2tU
–3tU
–4tU
–5tU
0tU
1tU
–1tU
–2tU
–3tU
–4tU
0tU
–1tU
–2tU
–3tU
HM
HH
TABLE 2. FB = 1Q. 3Q OUTPUT CONFIGURATIONS WITH DIFFERENT 3F(1:0)
FB
1F(1:0)
LL
Output at 3F(1:0)
LL
LM
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
–9tU
–10tU
LH
0tU
ML
2tU
MM
4tU
MH
6tU
5tU
4tU
3tU
2tU
1tU
0tU
–1tU
–2tU
HL
8tU
7tU
6tU
5tU
4tU
3tU
2tU
1tU
0tU
HM
10tU
9tU
8tU
7tU
6tU
5tU
4tU
3tU
2tU
HH
f/2+4tU
f/2+3tU
f/2+2tU
f/2+1tU
f/2+0tU
f/2–1tU
f/2–2tU
f/2–3tU
f/2–4tU
f/4+4tU
f/4+3tU
f/4+2tU
f/4+1tU
f/4+0tU
f/4–1tU
f/4–2tU
f/4–3tU
f/4–4tU
LM
LH
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
1tU
3tU
0tU
2tU
ML
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
1tU
MM
MH
HL
0tU
–1tU
–2tU
–3tU
–4tU
HM
HH
5
PROGRAMMINGTURBOCLOCKQS5991,QS5992,QS5993,QS5V991,ANDQS5V993
APPLICATIONNOTEAN-226
TABLE 3. FB = 1Q. 4Q OUTPUT CONFIGURATIONS WITH DIFFERENT 4F(1:0)
FB
1F(1:0)
LL
Output at 4F(1:0)
LL
LM
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
–9tU
–10tU
LH
0tU
ML
2tU
MM
4tU
MH
6tU
5tU
4tU
3tU
2tU
1tU
0tU
–1tU
–2tU
HL
8tU
7tU
6tU
5tU
4tU
3tU
2tU
1tU
0tU
HM
10tU
9tU
8tU
7tU
6tU
5tU
4tU
3tU
2tU
HH
f/2+4tU
f/2+3tU
f/2+2tU
f/2+1tU
f/2+0tU
f/2–1tU
f/2–2tU
f/2–3tU
f/2–4tU
–f+4tU
–f+3tU
–f+2tU
–f+1tU
–f+0tU
–f–1tU
–f–2tU
–f–3tU
–f–4tU
LM
LH
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
–7tU
–8tU
1tU
3tU
0tU
2tU
ML
–1tU
–2tU
–3tU
–4tU
–5tU
–6tU
1tU
MM
MH
HL
0tU
–1tU
–2tU
–3tU
–4tU
HM
HH
TABLE 4. FB = 3Q. 1Q/2Q OUTPUT CONFIGURATIONS WITH DIFFERENT 1F(1:0)/2F(1:0)
FB
3F(1:0)
LL
Output at 1F(1:0)/2F(1:0)
LL
2*f–4tU
2tU
LM
2*f–3tU
3tU
LH
2*f–2tU
4tU
ML
2*f–1tU
5tU
MM
2*f+0tU
6tU
MH
HL
2*f+2tU
8tU
HM
2*f+3tU
9tU
HH
2*f+4tU
10tU
8tU
2*f+1tU
7tU
LM
LH
0tU
1tU
2tU
3tU
4tU
5tU
6tU
7tU
ML
–2tU
–1tU
–3tU
–5tU
–7tU
–9tU
4*f–3tU
0tU
1tU
2tU
3tU
4tU
5tU
6tU
MM
MH
HL
–4tU
–2tU
–4tU
–6tU
–8tU
4*f–2tU
–1tU
–3tU
–5tU
–7tU
4*f–1tU
0tU
1tU
2tU
3tU
4tU
–6tU
–2tU
–4tU
–6tU
4*f+0tU
–1tU
–3tU
–5tU
4*f+1tU
0tU
1tU
2tU
–8tU
–2tU
–4tU
4*f+2tU
–1tU
–3tU
4*f+3tU
0tU
HM
HH
–10tU
4*f–4tU
–2tU
4*f+4tU
TABLE 5. FB = 3Q. 4Q OUTPUT CONFIGURATIONS WITH DIFFERENT 4F(1:0)
FB
3F(1:0)
LL
Output at 4F(1:0)
LL
LM
2*f–6tU
0tU
LH
2*f–4tU
2tU
ML
2*f–2tU
4tU
MM
2*f+0tU
6tU
MH
2*f+2tU
8tU
HL
2*f+4tU
10tU
8tU
HM
2*f+6tU
12tU
10tU
8tU
HH
0tU
–2*f
LM
LH
f/2+6tU
f/2+4tU
f/2+2tU
f/2+0tU
f/2–2tU
f/2–4tU
f/2–6tU
2*f
–f+6tU
–f+4tU
–f+2tU
–f+0tU
–f–2tU
–f–4tU
–f–6tU
–4*f
–2tU
0tU
2tU
4tU
6tU
ML
–4tU
–2tU
0tU
2tU
4tU
6tU
MM
MH
HL
–6tU
–4tU
–2tU
–4tU
–6tU
–8tU
4*f–2tU
0tU
2tU
4tU
6tU
–8tU
–6tU
–2tU
–4tU
–6tU
4*f+0tU
0tU
2tU
4tU
–10tU
–12tU
4*f–6tU
–8tU
–2tU
–4tU
4*f+2tU
0tU
2tU
HM
HH
–10tU
4*f–4tU
–2tU
4*f+4tU
0tU
4*f+6tU
6
PROGRAMMINGTURBOCLOCKQS5991,QS5992,QS5993,QS5V991,ANDQS5V993
APPLICATIONNOTEAN-226
TABLE 6. FB = 4Q. 1Q/2Q OUTPUT CONFIGURATIONS WITH DIFFERENT 1F(1:0)/2F(1:0)(1)
FB
4F(1:0)
LL
Output at 1F(1:0)/2F(1:0)
LL
–2*f–4tU
2tU
LM
2*f–3tU
3tU
LH
2*f–2tU
4tU
ML
2*f–1tU
5tU
MM
2*f+0tU
6tU
MH
HL
2*f+2tU
8tU
HM
2*f+3tU
9tU
HH
2*f+4tU
10tU
8tU
2*f+1tU
7tU
LM
LH
0tU
1tU
2tU
3tU
4tU
5tU
6tU
7tU
ML
–2tU
–1tU
–3tU
–5tU
–7tU
–9tU
–f–3tU
0tU
1tU
2tU
3tU
4tU
5tU
6tU
MM
MH
HL
–4tU
–2tU
–4tU
–6tU
–8tU
–f–2tU
–1tU
–3tU
–5tU
–7tU
–f–1tU
0tU
1tU
2tU
3tU
4tU
–6tU
–2tU
–4tU
–6tU
–f+0tU
–1tU
–3tU
–5tU
–f+1tU
0tU
1tU
2tU
–8tU
–2tU
–4tU
–f+2tU
–1tU
–3tU
–f+3tU
0tU
HM
HH
–10tU
–f–4tU
–2tU
–f+4tU
NOTE:
1. Table 6 is not applicable for QS5993 and QS5V993.
TABLE 7. FB = 4Q. 3Q OUTPUT CONFIGURATIONS WITH DIFFERENT 3F(1:0) (1)
FB
4F(1:0)
LL
Output at 3F(1:0)
LL
LM
2*f–6tU
0tU
LH
2*f–4tU
2tU
ML
2*f–2tU
4tU
MM
2*f+0tU
6tU
MH
2*f+2tU
8tU
HL
2*f+4tU
10tU
8tU
HM
2*f+6tU
12tU
10tU
8tU
HH
0tU
f/2+0tU
f/4+6tU
f/4+4tU
f/4+2tU
f/4+0tU
f/4–2tU
f/4–4tU
f/4–6tU
–f/4
LM
LH
f/2+6tU
f/2+4tU
f/2+2tU
f/2+0tU
f/2–2tU
f/2–4tU
f/2–6tU
–f/2
–2tU
0tU
2tU
4tU
6tU
ML
–4tU
–2tU
–4tU
–6tU
–8tU
–10tU
–f–4tU
0tU
2tU
4tU
6tU
MM
MH
HL
–6tU
–2tU
–4tU
–6tU
–8tU
–f–2tU
0tU
2tU
4tU
6tU
–8tU
–2tU
–4tU
–6tU
–f+0tU
0tU
2tU
4tU
–10tU
–12tU
–f–6tU
–2tU
–4tU
–f+2tU
0tU
2tU
HM
HH
–2tU
–f+4tU
0tU
–f+6tU
NOTE:
1. Table 7 is not applicable for QS5993 and QS5V993.
CONCLUSION
Withits flexible,programmable skewcapability,TurboClockis ideally possible solutions for a given set of inputs at the press of a key. The
suited for a variety of applications. IDT offers several tools to assist the designers canthenselectthesolutionthatbestmeets theirrequirements.
designers with designs incorporating TurboClock. One of these tools is In addition, IBIS models are available at no cost for system simulation
TurboKit, a powerful software tool that provides the designers with all purposes.
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7
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