SSTUA32864BHLF [IDT]
CABGA-96, Tray;
| 型号： | SSTUA32864BHLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CABGA-96, Tray 逻辑集成电路 |
| 文件： | 总11页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICSSSTUA32864B
Integrated
Circuit
Systems,Inc.
25-Bit Configurable Registered Buffer for DDR2
Pin Configuration
Recommended Application:
•
DDR2 Memory Modules
1
2
3
4
5
6
•
Provides complete DDR DIMM solution with
ICS97U877
Ideal for DDR2 400, 533 and 667
A
B
C
D
E
F
•
Product Features:
•
•
25-bit 1:1 or 14-bit 1:2 configurable registered buffer
Supports SSTL_18 JEDEC specification on data
inputs and outputs
Supports LVCMOS switching levels on C0, C1 and
RESET# inputs
Low voltage operation
VDD = 1.7V to 1.9V
G
H
J
•
•
K
L
M
N
P
R
T
•
•
•
Available in 96 BGA package
Drop-in replacement for ICSSSTUA32866
Green packages available
96 Ball BGA
(Top View)
Truth Table
Inputs
Outputs
QCS#
Dn,
DODT,
DCKE
QODT,
QCKE
RST#
DCS#
CSR#
CK
CK#
Qn
Ball Assignments
H
H
H
H
H
H
H
H
H
H
H
H
L
H
X
L
L
L
L
L
L
L
L
L
L
DCKE
D2
NC
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
QCKE
NC
H
H
A
B
C
D
E
F
Q
0
Q
0
Q
0
L or H
L or H
L or H
L or H
L or H
L or H
D15
D16
NC
Q2
Q15
Q16
NC
L
L
L
L
L
L
H
H
H
L
L
D3
Q3
H
X
H
H
DODT
D5
QODT
Q5
Q
0
Q
0
Q
0
D17
D18
RST#
DCS#
CSR#
D19
D20
D21
D22
D23
D24
D25
Q17
Q18
C0
L
L
L
H
H
H
L
L
L
H
H
H
X
H
H
D6
Q6
Q
0
Q
0
Q
0
NC
C1
G
H
J
Q
0
H
H
L
L
H
H
H
H
CK
QCS#
ZOH
Q8
NC
Q
0
H
X
H
CK#
D8
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
Q25
Q
0
Q
0
Q
0
H
H
L or H
X or
L or H
X or
X or
X or
X or
K
L
L
L
L
L
Floating Floating Floating Floating Floating
D9
Q9
D10
D11
D12
D13
D14
Q10
Q11
Q12
Q13
Q14
M
N
P
R
T
1
2
3
4
5
6
1:1 Register (C0 = 0, C1 = 0)
1055A—01/28/05
ICSSSTUA32864B
Ball Assignments
Ball Assignments
D1
NC
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
DCKE
D2
NC
VREF
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
QCKEA QCKEB
A
B
C
D
E
F
A
B
C
D
E
F
D2
NC
NC
Q2A
Q3A
Q2B
Q3B
D3
NC
D3
NC
D4
NC
DODT
D5
NC
QODTA QODTB
D5
NC
NC
Q5A
Q6A
C1
Q5B
Q6B
C0
D6
NC
D6
NC
NC
RST#
DCS#
CSR#
NC
NC
RST#
DCS#
CSR#
NC
G
H
J
G
H
J
CK
QCSA# QCSB#
CK
QCSA# QCSB#
CK#
D8
ZOH
Q8A
Q9A
Q10A
ZOL
Q8B
Q9B
Q10B
CK#
D8
ZOH
Q8A
ZOL
Q8B
K
L
K
L
D9
NC
D9
NC
Q9A
Q9B
D10
DODT
D12
D13
DCKE
NC
D10
D11
D12
D13
D14
NC
Q10A
Q11A
Q12A
Q13A
Q14A
Q10B
Q11B
Q12B
Q13B
Q14B
M
N
P
R
T
M
N
P
R
T
NC
QODTA QODTB
NC
NC
Q12A
Q13A
Q12B
Q13B
NC
NC
NC
NC
QCKEA QCKEB
NC
1
2
3
4
5
6
1
2
3
4
5
6
1:2 Register A (C0 = 0, C1 = 1)
1:2 Register B (C0 = 1, C1 = 1)
General Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUA32864B operates
from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when
high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers
are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when
RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be
held at a valid logic high or low level.To ensure defined outputs from the register before a stable clock has been supplied,
RST# must be held in the low state during power up.
In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared
and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until
the input receivers are fully enabled, the design of the ICSSSTUA32864B must ensure that the outputs will remain
low, thus ensuring no glitches on the output.
The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS#
and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input
has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not
desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would
be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
1055A—01/28/05
2
ICSSSTUA32864B
Ball Assignment
Electrical
Characteristics
Terminal Name
Description
GND
VDD
Ground
Ground input
1.8V nominal
0.9V nominal
Input
Power supply voltage
VREF
ZOH
Input reference voltage
Reserved for future use
Reserved for future use
Positive master clock input
Negative master clock input
Configuration control inputs
ZOL
Input
CK
Differential input
Differential input
LVCMOS inputs
CK#
C0, C1
Asynchronous reset input - resets registers and disables VREF data and
clock differential-input receivers
RST#
CSR#, DCS#
D1 - D25
DODT
LVCMOS input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
Chip select inputs - disables D1 - D24 outputs switching when both inputs
are high
Data input - clock in on the crossing of the rising edge of CK and the
falling edge of CK#
The outputs of this register bit will not be suspended by the DCS# and
CSR# control
The outputs of this register bit will now be suspended by the DCS# and
CSR# control
DCKE
Q1 - Q25
QCS#
Data ouputs that are suspended by the DCS# and CSR# control
Data output that will not be suspended by the DCS# and CSR# control
Data output that will not be suspended by the DCS# and CSR# control
Data output that will not be suspended by the DCS# and CSR# control
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
QODT
QCKE
1055A—01/28/05
3
ICSSSTUA32864B
Block Diagram for 1:1 mode (positive logic)
RST#
CK
CK#
VREF
DCKE
D
C1
C1
QCKEA
QODTA
R
D
DODT
DCS#
CSR#
R
1D
C1
QCSA#
R
D1
0
1
1D
Q1A
C1
Q1B*
R
To 21 Other Channels
*Note: Disabled in 1:1 configuration
1055A—01/28/05
4
ICSSSTUA32864B
Block Diagram for 1:2 mode (positive logic)
RST#
CK
CK#
VREF
DCKE
1D
C1
QCKEA
QCKEB*
R
DODT
DCS#
CSR#
1D
QODTA
C1
QODTB*
R
1D
QCSA#
C1
QCSB#*
R
D1
0
1
1D
Q1A
C1
Q1B*
R
To 10 Other Channels
*Note: Disabled in 1:1 configuration
1055A—01/28/05
5
ICSSSTUA32864B
Absolute Maximum Ratings
Notes:
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V
Input Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +2.5V
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V
Input Clamp Current . . . . . . . . . . . . . . . . . . . . 50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . 50mA
Continuous Output Current. . . . . . . . . . . . . . . 50mA
VDD or GND Current/Pin . . . . . . . . . . . . . . . . 100mA
1. The input and output negative voltage
ratings may be excluded if the input
andoutputclampratingsareobserved.
2. This value is limited to 2.5V maximum.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Package Thermal Impedance3 . . . . . . . . . . . . . . . 36°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Recommended Operating Conditions
DESCRIPTION
PARAMETER
MIN
1.7
TYP
1.8
MAX
1.9
UNITS
I/O Supply Voltage
VDD
Reference Voltage
VREF
VTT
0.49 x VDD
VREF - 0.04
0
0.5 x VDD
VREF
0.51 x VDD
VREF + 0.04
VDD
Termination Voltage
VI
Input Voltage
VIH (DC)
VIH (AC)
VIL (DC)
VIL (AC)
VIH
DC Input High Voltage
AC Input High Voltage
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
Input Low Voltage Level
Common mode Input Range
Differential Input Voltage
High-Level Output Current
Low-Level Output Current
VREF + 0.125
VREF + 0.250
Data Inputs
V
VREF - 0.125
VREF - 0.250
RESET#,
C0, C1
0.65 x VDD
VIL
0.35 x VDD
1.125
VICR
0.675
0.600
CLK, CLK#
VID
IOH
-8
8
mA
°C
IOL
Operating Free-Air Temperature
TA
0
70
1Guaranteed by design, not 100% tested in production.
Note: Reset# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation.
The differential inputs must not be floating unless Reset# is low.
1055A—01/28/05
6
ICSSSTUA32864B
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 1.8 +/-0.1V (unless otherwise stated)
CONDITIONS
SYMBOL
PARAMETERS
VDD
MIN
1.2
-5
TYP MAX
-1.2
UNITS
V
VIK
VOH
VOL
II
II = -18mA
IOH = -6mA
IOL = 6mA
1.7V
1.7V
1.9V
0.5
5
100
All Inputs
Standby (Static)
VI = VDD or GND
RESET# = GND
VI = VIH(AC) or VIL(AC)
RESET# = VDD
µA
µA
IDD
,
1.9V
1.8V
Operating (Static)
40
39
mA
RESET# = VDD
,
Dynamic operating
(clock only)
µ/clock
MHz
VI = VIH(AC) or VIL(AC)
,
CLK and CLK# switching
50% duty cycle.
IO = 0
RESET# = VDD
,
Dynamic Operating
(per each data input)
1:1 mode
IDDD
VI = VIH(AC) or VIL (AC)
,
19
35
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
µA/ clock
MHz/data
Dynamic Operating
(per each data input)
1:2 mode
Data Inputs
CLK and CLK#
RESET#
VI = VREF 350mV
VICR = 1.25V, VI(PP) = 360mV
VI = VDD or GND
2.5
2
3.5
3
pF
Ci
2.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
1055A—01/28/05
7
ICSSSTUA32864B
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
410
SYMBOL
fclock
PARAMETERS
Clock frequency
Pulse duration, CK, CK High or Low
UNITS
MHz
ns
tW
1
Differential inputs active time (See notes 1 and 2)
Differential inputs inactive time (See notes 1 and 3)
DCS before CK, CK↓,
tACT
10
15
ns
tINACT
ns
Setup time
Setup time
Hold time
CSR high; CSR before
CK, CK↓, DCS high
DCS before CK, CK↓,
CSR Low
DODT, DCKE and data
before CK, CK↓
DCS, DODT, DCKE and
data after CK, CK↓
PAR_IN after CK, CK↓
0.7
ns
0.5
0.5
ns
ns
tSU
0.50
0.50
ns
ns
th
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
Notes:
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
From
(Input)
To
(Output)
VDD = 1.8V 0.1V
MIN TYP MAX
SYMBOL
UNITS
fmax
410
1.1
MHz
ns
1
CLK, CLK#
CLK, CLK#
RESET#
Q
Q
Q
1.9
2
tPDM
2
tPDMSS
tphl
3
ns
Notes: 1. Includes 350ps test-load transmission-line delay
2. Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
V
MIN
1
DD = 1.8V 0.1V
PARAMETER
UNIT
MAX
dV/dt_r
4
4
1
V/ns
V/ns
V/ns
dV/dt_f
1
1
∆
dV/dt_
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
1055A—01/28/05
8
ICSSSTUA32864B
V
DD
DUT
RL = 1000Ω
TL=350ps, 50Ω
TL=50Ω
CK#
CK
Out
Test Point
CK Inputs
CL = 30 pF
(see Note 1)
RL = 1000Ω
Test Point
RL = 100Ω
LOAD CIRCUIT
Test Point
VCMOS
RST#
Input
VDD
0 V
tact
90%
VID
VDD/2
VDD/2
CK
CK
VICR
VICR
tinact
tPLH
tPHL
IDD
(see
Note 2)
10%
VOH
VOL
Output
VTT
VTT
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
VID
tw
Inpu t
VICR
VICR
VOLTAGE WAVEFORMS – PULSE DURATION
VID
LVCMOS
RST#
Input
VIH
VIL
VDD/2
CK
VICR
tRPHL
CK
VOH
VOL
th
tsu
Output
VTT
VIH
VIL
Inpu t
VREF
VREF
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
Figure 6 — Parameter
(V
= 1.8 V 0.1 V)
DD
Measurement Information
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,
Zo=50Ω, input slew rate = 1 V/ns 20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. tPLH and tPHL are the same as tPDM
.
1055A—01/28/05
9
ICSSSTUA32864B
VDD
DUT
RL = 50Ω
Test Point
Out
CL = 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Output
VOH
80%
20%
dt_f
VOL
dv_f
VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out
Test Point
C
L = 10 pF
RL = 50Ω
(see Note 1)
LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT
dt_r
dv_r
VOH
80%
20%
Output
VOL
VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT
Figure 7 — Output Slew-Rate
(V
= 1.8V 0.1V)
DD
Measurement Information
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO
50Ω, input slew rate = 1 V/ns 20% (unless otherwise specified).
=
1055A—01/28/05
10
ICSSSTUA32864B
C
Seating
Plane
Numeric Designations
for Horizontal Grid
A1
b
REF
T
3 2 1
4
A
B
C
D
Alpha Designations
for Vertical Grid
(Letters I, O, Q & S
not used)
D
d TYP
D1
- e - TYP
TOP VIEW
E
c
REF
TYP
- e -
h
TYP
E1
0.12
C
ALL DIMENSIONS IN MILLIMETERS
----- BALL GRID -----
Max.
REF. DIMENSIONS
D
E
T
e
HORIZ
VERT
TOTAL
d
h
Min/Max
b
c
Min/Max
Min/Max
13.50 Bsc
11.50 Bsc
5.50 Bsc
5.00 Bsc
1.30/1.50
/1.2
0.80 Bsc
0.65 Bsc
6
6
16
16
96
96
0.40/0.50
0.38/0.48
0.25/0.41
0.27/0.37
0.75
0.875
0.75
0.875
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
* Source Ref.: JEDEC Publication 95,
MO-205
10-0055C
Ordering Information
ICSSSTUA32864Bz(LF)T
Example:
ICS XXXX y z (LF) - T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
H = LFBGA (standard size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
1055A—01/28/05
11
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