SSTUA32864EG_技术文档

SSTUA32864

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM

applications

Rev. 01 — 12 May 2005

Product data sheet

1. General description

The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer designed

for 1.7 V to 2.0 V V_DDoperation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTUA32864 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout conﬁguration of the 1 : 2 pinout from A conﬁguration

(when LOW) to B conﬁguration (when HIGH). The C1 input controls the pinout

conﬁguration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).

The device supports low-power standby operation. When the reset input (RESET) is LOW,

the differential input receivers are disabled, and un-driven (ﬂoating) data, clock and

reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all

registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs

must always be held at a valid logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the data outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUA32864 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from

changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is

LOW, the Qn outputs will function normally. The RESET input has priority over the DCS

and CSR control and will force the outputs LOW. If the DCS-control functionality is not

desired, then the CSR input can be hardwired to ground, in which case the setup time

requirement for DCS would be the same as for the other Dn data inputs.

The SSTUA32864 is available in a 96-ball, low proﬁle ﬁne-pitch ball grid array (LFBGA96)

package.

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

2. Features

■ Conﬁgurable register supporting DDR2 Registered DIMM applications

■ Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

■ Controlled output impedance drivers enable optimal signal integrity and speed

■ Exceeds SSTUA32864 JEDEC speciﬁcation speed performance (1.8 ns max.

single-bit switching propagation delay; 2.0 ns max. mass-switching)

■ Supports up to 450 MHz clock frequency of operation

■ Optimized pinout for high-density DDR2 module design

■ Chip-selects minimize power consumption by gating data outputs from changing state

■ Supports SSTL_18 data inputs

■ Differential clock (CK and CK) inputs

■ Supports LVCMOS switching levels on the control and RESET inputs

■ Single 1.8 V supply operation (1.7 V to 2.0 V)

■ Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package

3. Applications

■ 400 MT/s to 667 MT/s DDR2 registered DIMMs without parity

4. Ordering information

Table 1:

Ordering information

T_amb= 0 °C to +70 °C.

Type number

Solder process

Package

Name

Description

Version

SSTUA32864EC/G Pb-free (SnAgCu

solder ball compound)

LFBGA96 plastic low proﬁle ﬁne-pitch ball grid array package; SOT536-1

96 balls; body 13.5 × 5.5 × 1.05 mm

SSTUA32864EC

SnPb solder ball

compound

LFBGA96 plastic low proﬁle ﬁne-pitch ball grid array package; SOT536-1

96 balls; body 13.5 × 5.5 × 1.05 mm

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

2 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

5. Functional diagram

RESET

CK

SSTUA32864

VREF

DCKE

1D

C1

R

QCKEA

QCKEB

(1)

DODT

DCS

CSR

D1

1D

C1

R

QODTA

QODTB

1D

C1

R

QCSA

(1)

QCSB

0

1

1D

C1

R

Q1A

(1)

Q1B

002aab383

to other channels

(1) Disabled in 1 : 1 conﬁguration.

Fig 1. Functional diagram of SSTUA32864; 1 : 2 mode (positive logic)

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

3 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

6. Pinning information

6.1 Pinning

SSTUA32864EC/G

ball A1

SSTUA32864EC

index area

1 2 3 4 5 6

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

002aab384

Transparent top view

Fig 2. Pin conﬁguration for LFBGA96

1

DCKE

D2

2

n.c.

3

4

5

QCKE

Q2

6

A

B

C

D

E

F

VREF

GND

V

DNU

Q15

Q16

DNU

Q17

Q18

C0

DD

D15

D16

n.c.

GND

D3

V

Q3

DD

DODT

D5

GND

QODT

Q5

D17

D18

RESET

DCS

CSR

D19

D20

D21

D22

D23

D24

D25

V

DD

D6

GND

Q6

G

H

J

n.c.

CK

V

C1

DD

GND

QCS

ZOH

Q8

DNU

ZOL

Q19

Q20

Q21

Q22

Q23

Q24

CK

V

DD

K

L

D8

GND

D9

V

Q9

DD

M

N

P

R

T

D10

D11

D12

D13

D14

GND

Q10

Q11

Q12

Q13

Q14

V

DD

GND

V

DD

VREF

Q25

002aaa955

Fig 3. Ball mapping; 1 : 1 register (C0 = 0, C1 = 0); top view

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

4 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

1

DCKE

D2

2

3

4

5

6

A

B

C

D

E

F

n.c.

VREF

GND

V

QCKEA QCKEB

DD

DNU

n.c.

GND

Q2A

Q3A

Q2B

Q3B

D3

V

DD

DODT

D5

GND

QODTA QODTB

DNU

RESET

DCS

CSR

DNU

V

Q5A

Q6A

Q5B

Q6B

DD

D6

GND

G

H

J

n.c.

CK

V

C1

C0

DD

GND

QCSA

ZOH

Q8A

QCSB

ZOL

CK

V

DD

K

L

D8

GND

Q8B

D9

V

Q9A

Q9B

DD

M

N

P

R

T

D10

D11

D12

D13

D14

GND

Q10A

Q11A

Q12A

Q13A

Q14A

Q10B

Q11B

Q12B

Q13B

V

DD

GND

V

DD

VREF

Q14B

002aaa956

Fig 4. Ball mapping; 1 : 2 register A (C0 = 0, C1 = 1); top view

1

D1

2

3

4

5

6

A

B

C

D

E

F

n.c.

VREF

GND

V

Q1A

Q2A

Q3A

Q4A

Q5A

Q6A

C1

Q1B

Q2B

Q3B

Q4B

Q5B

Q6B

C0

DD

D2

DNU

n.c.

GND

D3

V

DD

D4

GND

D5

DNU

RESET

DCS

CSR

DNU

V

DD

D6

GND

G

H

J

n.c.

CK

V

DD

GND

QCSA

ZOH

Q8A

Q9A

Q10A

QCSB

ZOL

Q8B

Q9B

Q10B

CK

V

DD

K

L

D8

GND

D9

V

DD

M

N

P

R

T

D10

DODT

D12

D13

DCKE

GND

V

QODTA QODTB

DD

GND

Q12A

Q13A

Q12B

Q13B

V

DD

VREF

QCKEA QCKEB

002aaa957

Fig 5. Ball mapping; 1 : 2 register B (C0 = 1, C1 = 1); top view

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

5 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

6.2 Pin description

Table 2:

Symbol

GND

Pin description

Type

Description

B3, B4, D3, D4, F3, F4, ground input

H3, H4, K3, K4, M3,

ground

M4, P3, P4

V_DD

A4, C3, C4, E3, E4,

G3, G4, J3, J4, L3, L4,

N3, N4, R3, R4, T4

1.8 V nominal

power supply voltage

VREF

ZOH

ZOL

A3, T3

J5

0.9 V nominal

input

input reference voltage

reserved for future use

J6

input

CK

H1

differential input positive master clock input

differential input negative master clock input

LVCMOS inputs conﬁguration control inputs

CK

J1

C0, C1

RESET

G6, G5

G2

LVCMOS input Asynchronous reset input (active LOW). Resets registers and

disables VREF data and clock differential-input receivers.

CSR, DCS

D1 to D25

DODT

J2, H2

SSTL_18 input Chip select inputs (active LOW). Disables data outputs

switching when both inputs are HIGH. ^[2]

[1]

SSTL_18 input Data inputs. Clocked in on the crossing of the rising edge of

CK and the falling edge of CK.

[1]

SSTL_18 input The outputs of this register will not be suspended by DCS and

CSR control.

DCKE

SSTL_18 input The outputs of this register will not be suspended by DCS and

CSR control.

Q1 to Q25,

1.8 V CMOS

The outputs that are suspended by DCS and CSR control^[3]

.

Q1A to Q14A,

Q1B to Q14B

[1]

QCS, QCSA,

QCSB

1.8 V CMOS

Data outputs that will not be suspended by DCS and CSR

control.

QODT, QODTA,

QODTB

1.8 V CMOS

Data outputs that will not be suspended by DCS and CSR

control.

QCKE, QCKEA,

QCKEB

1.8 V CMOS

Data outputs that will not be suspended by DCS and CSR

control.

n.c.

A2, D2, G1

-

Not connected. Ball present but no internal connection to the

die.

[1]

DNU

Do-not-use. Ball internally connected to the die which should

be left open-circuit.

[1] Depends on conﬁguration. See Figure 3, Figure 4, and Figure 5 for ball number.

[2] Conﬁgurations:

Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.

Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.

Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.

[3] Conﬁgurations:

Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.

Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.

Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

6 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

7. Functional description

7.1 Function table

Table 3:

Function table (each ﬂip-ﬂop)

L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition;

↓ = HIGH-to-LOW transition

Inputs

CSR

Outputs ^[1]

RESET

DCS

CK

Dn,

DODT,

DCKE

Qn

QCS

QODT,

QCKE

H

L

↑

↓

L

H

X

L

H

L

H

↑

↓

L

L or H

Q₀

L

Q₀

L

Q₀

L

H

L

↑

↓

L

↑

↓

H

X

L

H

L

H

L

L or H

Q₀

L

Q₀

H

Q₀

L

H

↑

↓

L

↑

L or H

↑

↓

L or H

↓

H

X

L

H

L

Q₀

L

Q₀

H

Q₀

L

H

↑

↓

H

X

H

L or H

Q₀

L

Q₀

L

X or

ﬂoating

[1] Q₀is the previous state of the associated output.

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

7 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

8. Limiting values

Table 4:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_I

Parameter

Conditions

Min

Max

Unit

V

supply voltage

−0.5

−0.5^[1]

+2.5

receiver input voltage

driver output voltage

input clamp current

output clamp current

continuous output current

continuous current through each

+2.5^[2]

V_DD+ 0.5^[2]

±50

V

V_O

V

I_IK

V_I< 0 V or V_I> V_DD

V_O< 0 V or V_O> V_DD

0 V < V_O< V_DD

-

mA

I_OK

±50

I_O

±50

I_CCC

±100

V_DDor GND pin

T_stg

storage temperature

−65

+150

°C

[1] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

[2] This value is limited to 2.5 V maximum.

9. Recommended operating conditions

Table 5:

Symbol

V_DD

Operating conditions

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

1.7

-

2.0

V

V_ref

reference voltage

termination voltage

input voltage

0.49 × V_DD

0.50 × V_DD0.51 × V_DD

V_TT

V

0

_ref− 0.040

V_ref

V_ref+ 0.040

V_I

-

V_DD

-

V_IH(AC)

V_IL(AC)

V_IH(DC)

V_IL(DC)

V_IH

AC HIGH-level input voltage data inputs (Dn), CSR

AC LOW-level input voltage data inputs (Dn), CSR

DC HIGH-level input voltage data inputs (Dn), CSR

DC LOW-level input voltage data inputs (Dn), CSR

V_ref+ 0.250

-

V

-

_ref− 0.250

V_ref+ 0.125

-

V

_ref− 0.125

[1]

[2]

HIGH-level input voltage

LOW-level input voltage

RESET, Cn

0.65 × V_DD

V_DD

V_IL

-

0.35 × V_DD

1.125

V_ICR

common mode input voltage CK, CK

range

0.675

[2]

V_ID

I_OH

I_OL

differential input voltage

HIGH-level output current

LOW-level output current

ambient temperature

CK, CK

600

-

mV

mA

°C

-

−8

8

-

T_amb

operating in free air

0

+70

[1] The RESET and Cn inputs of the device must be held at valid logic levels (not ﬂoating) to ensure proper device operation.

[2] The differential inputs must not be ﬂoating, unless RESET is LOW.

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

8 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

10. Characteristics

Table 6:

Characteristics

Recommended operating conditions; T_amb= 0 °C to +70 °C; all voltages are referenced to GND (ground = 0 V);

unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

1.2

-

Typ

Max

-

Unit

V

V_OH

V_OL

I_I

HIGH-level output voltage

I_OH= −6 mA; V_DD= 1.7 V

I_OL= 6 mA; V_DD= 1.7 V

all inputs; V_I= V_DDor GND;

-

LOW-level output voltage

input current

0.5

+5

V

−5

µA

V

_DD= 2.0 V

RESET = GND; I_O= 0 mA;

_DD= 2.0 V

RESET = V_DD; I_O= 0 mA;

_DD= 2.0 V;

V_I= V_IH(AC)or V_IL(AC)

RESET = V_DD

I_DD

static standby current

static operating current

-

100

40

µA

V

mA

V

I_DDD

dynamic operating current per

MHz, clock only

;

-

16

11

-

µA

V_I= V_IH(AC)or V_IL(AC); CK and

CK switching at 50 % duty cycle.

I_O= 0 mA; V_DD= 2.0 V

dynamic operating current per

MHz, per each data input,

1 : 1 mode

RESET = V_DD;

V_I= V_IH(AC)or V_IL(AC); CK and

CK switching at 50 % duty cycle.

One data input switching at half

clock frequency, 50 % duty

cycle. I_O= 0 mA; V_DD= 2.0 V

dynamic operating current per

MHz, per each data input,

1 : 2 mode

RESET = V_DD

;

-

19

-

µA

V_I= V_IH(AC)or V_IL(AC); CK and

CK switching at 50 % duty cycle.

One data input switching at half

clock frequency, 50 % duty

cycle. I_O= 0 mA; V_DD= 2.0 V

C_i

input capacitance, data inputs,

CSR

V_I= V_ref± 250 mV; V_DD= 1.8 V

2.5

2

-

3.5

3

pF

input capacitance, CK and CK

V_ICR= 0.9 V; V_ID= 600 mV;

V_DD= 1.8 V

input capacitance, RESET

V_I= V_DDor GND; V_DD= 1.8 V

2

4

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

9 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

Table 7:

Timing requirements

Recommended operating conditions; T_amb= 0 °C to +70 °C; V_DD= 1.8 V ± 0.1 V; unless otherwise speciﬁed.

See Figure 6 through Figure 11.

Symbol

f_clock

Parameter

Conditions

Min

Typ

Max

450

-

Unit

MHz

ns

clock frequency

-

t_W

pulse duration, CK, CK HIGH or

LOW

1

[1] [2]

[1] [3]

t_ACT

t_INACT

t_su

differential inputs active time

differential inputs inactive time

setup time

-

10

15

-

ns

-

DCS before CK ↑, CK ↓,

0.7

CSR HIGH

DCS before CK ↑, CK ↓,

CSR LOW

0.5

-

ns

CSR, ODT, CKE, and data

before CK ↑, CK ↓

t_h

hold time

DCS, CSR, ODT, CKE,

and data after CK ↑, CK ↓

[1] This parameter is not necessarily production tested.

[2] Data inputs must be active below a minimum time of t_ACT(max)after RESET is taken HIGH.

[3] Data and clock inputs must be held at valid levels (not ﬂoating) a minimum time of t_INACT(max)after RESET is taken LOW.

Table 8:

Switching characteristics

Recommended operating conditions; T_amb= 0 °C to +70 °C; V_DD= 1.8 V ± 0.1 V;

Class I, V_ref= V_TT= V_DD× 0.5 and C_L= 10 pF; unless otherwise speciﬁed. See Figure 6 through Figure 11.

Symbol

f_MAX

Parameter

Conditions

Min

450

1.2

-

Typ

Max

-

Unit

MHz

ns

maximum input clock frequency

propagation delay

-

[1]

t_PDM

CK and CK to output

1.8

2.0

[1] [2]

t_PDMSS

propagation delay, simultaneous

switching

ns

t_PHL

propagation delay

RESET to output

-

3

ns

[1] Includes 350 ps of test-load transmission line delay.

[2] This parameter is not necessarily production tested.

Table 9:

Output edge rates

Recommended operating conditions; V_DD= 1.8 V ± 0.1 V; unless otherwise speciﬁed.

Symbol

dV/dt_r

dV/dt_f

dV/dt_∆

Parameter

Conditions

Min

Typ

Max

Unit

V/ns

rising edge slew rate

falling edge slew rate

1

-

4

1

absolute difference between dV/dt_r

and dV/dt_f

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

10 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

11. Test information

11.1 Test circuit

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z₀= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

The outputs are measured one at a time with one transition per measurement.

V

DD

DUT

R

= 1000 Ω

L

T

= 50 Ω

T

= 350 ps, 50 Ω

L

CK

CK inputs

OUT

(1)

= 30 pF

C

L

R

L

test point

R

L

= 100 Ω

002aaa371

test point

(1) C_Lincludes probe and jig capacitance.

Fig 6. Load circuit

LVCMOS

V

DD

RESET

V

/2

DD

V

/2

DD

0 V

t

ACT

INACT

90 %

(1)

DD

I

10 %

002aaa372

(1) I_DDtested with clock and data inputs held at V_DDor GND, and I_O= 0 mA.

Fig 7. Voltage and current waveforms; inputs active and inactive times

t

W

V

IH

IL

V

input

V

ICR

ID

ICR

002aaa373

V_ID= 600 mV

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 8. Voltage waveforms; pulse duration

9397 750 14757

Product data sheet

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11 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

CK

V

ICR

ID

CK

t

h

su

V

IH

IL

input

V

ref

V

ref

002aaa374

V_ID= 600 mV

V_ref= V_DD/2

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 9. Voltage waveforms; setup and hold times

CK

V

ICR

i(p-p)

CK

t

PHL

PLH

V

OH

OL

V

output

TT

002aaa375

t_PLHand t_PHLare the same as t_PD

.

Fig 10. Voltage waveforms; propagation delay times (clock to output)

LVCMOS

V

IH

RESET

V

/2

DD

IL

t

PHL

OH

OL

output

V

TT

002aaa376

t_PLHand t_PHLare the same as t_PD

.

V_IH= V_ref+ 250 mV (AC voltage levels) for differential inputs. V_IH= V_DDfor LVCMOS inputs.

V_IL= V_ref− 250 mV (AC voltage levels) for differential inputs. V_IL= GND for LVCMOS inputs.

Fig 11. Voltage waveforms; propagation delay times (reset to output)

9397 750 14757

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11.2 Output slew rate measurement

V_DD= 1.8 V ± 0.1 V.

All input pulses are supplied by generators having the following characteristics:

PRR ≤ 10 MHz; Z₀= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise speciﬁed.

V

DD

R

DUT

= 50 Ω

L

OUT

test point

002aaa377

(1)

= 10 pF

C

L

(1) C_Lincludes probe and jig capacitance.

Fig 12. Load circuit, HIGH-to-LOW slew measurement

output

V

OH

80 %

dv_f

20 %

V

OL

dt_f

002aaa378

Fig 13. Voltage waveforms, HIGH-to-LOW slew rate measurement

DUT

OUT

test point

(1)

= 10 pF

C

L

R

L

= 50 Ω

002aaa379

(1) C_Lincludes probe and jig capacitance.

Fig 14. Load circuit, LOW-to-HIGH slew measurement

dt_r

V

OH

80 %

dv_r

20 %

output

OL

002aaa380

Fig 15. Voltage waveforms, LOW-to-HIGH slew rate measurement

9397 750 14757

Product data sheet

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12. Package outline

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

e

1

C

1/2 e

y

v M

w M

C

A B

C

1

e

b

T

R

P

N

e

M

L

K

J

H

G

F

e

2

1/2 e

E

D

C

B

A

ball A1

index area

1

2

3

4

5

6

X

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

v

w

y

1

D

E

1

2

1

2

max.

0.41

0.31

1.2

0.9

0.51

0.41

5.6

5.4

13.6

13.4

mm

1.5

4

12

0.1

0.2

0.8

0.15

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

00-03-04

03-02-05

SOT536-1

Fig 16. Package outline SOT536-1 (LFBGA96)

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

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SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of

soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch

SMDs. In these situations reﬂow soldering is recommended.

13.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)

vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °C to 270 °C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

9397 750 14757

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– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C

or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most

applications.

13.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage

(24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be

limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 seconds to 5 seconds between 270 °C and 320 °C.

13.5 Package related soldering information

Table 10: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package ^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^{[5] [6]}

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or

external package cracks may occur due to vaporization of the moisture in them (the so called popcorn

effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with

peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package

body peak temperature must be kept as low as possible.

9397 750 14757

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[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink

on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by

using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

14. Abbreviations

Table 11: Abbreviations

Acronym

CMOS

DDR

Description

Complementary Metal Oxide Silicon

Double Data Rate

DIMM

Dual In-line Memory Module

LVCMOS

PRR

Low Voltage Complementary Metal Oxide Silicon

Pulse Repetition Rate

RDIMM

SSTL

Registered Dual In-line Memory Module

Stub Series Terminated Logic

15. Revision history

Table 12: Revision history

Document ID

Release date Data sheet status

20050512 Product data sheet

Change notice Doc. number

Supersedes

SSTUA32864_1

-

9397 750 14757

-

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

17 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

16. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

17. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

19. Trademarks

Notice — All referenced brands, product names, service names and

18. Disclaimers

trademarks are the property of their respective owners.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

20. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

9397 750 14757

Product data sheet

Rev. 01 — 12 May 2005

18 of 19

SSTUA32864

Philips Semiconductors

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications

21. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

7.1

8

Functional description . . . . . . . . . . . . . . . . . . . 7

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended operating conditions. . . . . . . . 8

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 9

9

10

11

11.1

11.2

Test information. . . . . . . . . . . . . . . . . . . . . . . . 11

Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output slew rate measurement. . . . . . . . . . . . 13

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

13

13.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 15

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 16

Package related soldering information . . . . . . 16

13.2

13.3

13.4

13.5

14

15

16

17

18

19

20

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 18

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Contact information . . . . . . . . . . . . . . . . . . . . 18

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 12 May 2005

Document number: 9397 750 14757

Published in The Netherlands


型号：	SSTUA32864EG
厂家：	NXP
描述：	1.8 V configurable registered buffer for DDR2-667 RDIMM applications 1.8 V CON连接的可配置注册DDR2-667 RDIMM应用程序的缓冲区双倍数据速率
文件：	总19页 (文件大小：109K)
中文：	中文翻译
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