SSTUA32864EC,518 [NXP]
SSTUA32864 - 1.8 V configurable registered buffer for DDR2-667 RDIMM applications;型号: | SSTUA32864EC,518 |
厂家: | NXP |
描述: | SSTUA32864 - 1.8 V configurable registered buffer for DDR2-667 RDIMM applications 双倍数据速率 逻辑集成电路 触发器 |
文件: | 总20页 (文件大小:105K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SSTUA32864
1.8 V configurable registered buffer for DDR2-667 RDIMM
applications
Rev. 02 — 9 March 2007
Product data sheet
1. General description
The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed
for 1.7 V to 2.0 V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.
The SSTUA32864 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration of the 1 : 2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).
The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and un-driven (floating) data, clock and
reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all
registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs
must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUA32864 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from
changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS
and CSR control and will force the outputs LOW. If the DCS-control functionality is not
desired, then the CSR input can be hardwired to ground, in which case the setup time
requirement for DCS would be the same as for the other Dn data inputs.
The SSTUA32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96)
package.
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
2. Features
I Configurable register supporting DDR2 Registered DIMM applications
I Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
I Controlled output impedance drivers enable optimal signal integrity and speed
I Exceeds SSTUA32864 JEDEC specification speed performance (1.8 ns max.
single-bit switching propagation delay; 2.0 ns max. mass-switching)
I Supports up to 450 MHz clock frequency of operation
I Optimized pinout for high-density DDR2 module design
I Chip-selects minimize power consumption by gating data outputs from changing state
I Supports SSTL_18 data inputs
I Differential clock (CK and CK) inputs
I Supports LVCMOS switching levels on the control and RESET inputs
I Single 1.8 V supply operation (1.7 V to 2.0 V)
I Available in 96-ball, 13.5 mm × 5.5 mm, 0.8 mm ball pitch LFBGA package
3. Applications
I 400 MT/s to 667 MT/s DDR2 registered DIMMs without parity
4. Ordering information
Table 1.
Ordering information
Tamb = 0 °C to +70 °C.
Type number
Solder process
Package
Name
Description
Version
SSTUA32864EC/G Pb-free (SnAgCu
solder ball compound)
LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
SSTUA32864EC
SnPb solder ball
compound
LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
SSTUA32864_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
2 of 20
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
5. Functional diagram
RESET
CK
CK
SSTUA32864
VREF
DCKE
1D
C1
R
QCKEA
QCKEB
(1)
(1)
DODT
DCS
CSR
D1
1D
C1
R
QODTA
QODTB
1D
C1
R
QCSA
(1)
QCSB
0
1
1D
C1
R
Q1A
(1)
Q1B
002aab383
to other channels
(1) Disabled in 1 : 1 configuration.
Fig 1. Functional diagram of SSTUA32864; 1 : 2 mode (positive logic)
SSTUA32864_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
3 of 20
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
6. Pinning information
6.1 Pinning
SSTUA32864EC/G
ball A1
SSTUA32864EC
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aab384
Transparent top view
Fig 2. Pin configuration for LFBGA96
1
DCKE
D2
2
n.c.
3
4
5
QCKE
Q2
6
A
B
C
D
E
F
VREF
GND
V
DNU
Q15
Q16
DNU
Q17
Q18
C0
DD
D15
D16
n.c.
GND
D3
V
V
Q3
DD
DD
DODT
D5
GND
GND
QODT
Q5
D17
D18
RESET
DCS
CSR
D19
D20
D21
D22
D23
D24
D25
V
V
DD
DD
D6
GND
GND
Q6
G
H
J
n.c.
CK
V
V
C1
DD
DD
GND
GND
QCS
ZOH
Q8
DNU
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
CK
V
V
DD
DD
K
L
D8
GND
GND
D9
V
V
Q9
DD
DD
M
N
P
R
T
D10
D11
D12
D13
D14
GND
GND
Q10
Q11
Q12
Q13
Q14
V
V
DD
DD
GND
GND
V
V
V
DD
DD
DD
VREF
Q25
002aaa955
Fig 3. Ball mapping; 1 : 1 register (C0 = 0, C1 = 0); top view
SSTUA32864_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
4 of 20
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
1
DCKE
D2
2
3
4
5
6
A
B
C
D
E
F
n.c.
VREF
GND
V
QCKEA QCKEB
DD
DNU
DNU
n.c.
GND
Q2A
Q3A
Q2B
Q3B
D3
V
V
DD
DD
DODT
D5
GND
GND
QODTA QODTB
DNU
DNU
RESET
DCS
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
V
V
Q5A
Q6A
Q5B
Q6B
DD
DD
D6
GND
GND
G
H
J
n.c.
CK
V
V
C1
C0
DD
DD
GND
GND
QCSA
ZOH
Q8A
QCSB
ZOL
CK
V
V
DD
DD
K
L
D8
GND
GND
Q8B
D9
V
V
Q9A
Q9B
DD
DD
M
N
P
R
T
D10
D11
D12
D13
D14
GND
GND
Q10A
Q11A
Q12A
Q13A
Q14A
Q10B
Q11B
Q12B
Q13B
V
V
DD
DD
GND
GND
V
V
V
DD
DD
DD
VREF
Q14B
002aaa956
Fig 4. Ball mapping; 1 : 2 register A (C0 = 0, C1 = 1); top view
1
D1
2
3
4
5
6
A
B
C
D
E
F
n.c.
VREF
GND
V
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
DD
D2
DNU
DNU
n.c.
GND
D3
V
V
DD
DD
D4
GND
GND
D5
DNU
DNU
RESET
DCS
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
V
V
DD
DD
D6
GND
GND
G
H
J
n.c.
CK
V
V
DD
DD
GND
GND
QCSA
ZOH
Q8A
Q9A
Q10A
QCSB
ZOL
Q8B
Q9B
Q10B
CK
V
V
DD
DD
K
L
D8
GND
GND
D9
V
V
DD
DD
M
N
P
R
T
D10
DODT
D12
D13
DCKE
GND
GND
V
V
QODTA QODTB
DD
DD
GND
GND
Q12A
Q13A
Q12B
Q13B
V
V
V
DD
DD
DD
VREF
QCKEA QCKEB
002aaa957
Fig 5. Ball mapping; 1 : 2 register B (C0 = 1, C1 = 1); top view
Rev. 02 — 9 March 2007
SSTUA32864_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
5 of 20
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
6.2 Pin description
Table 2.
Symbol
GND
Pin description
Pin
Type
Description
B3, B4, D3, D4, F3, F4, ground input
H3, H4, K3, K4, M3,
ground
M4, P3, P4
VDD
A4, C3, C4, E3, E4,
G3, G4, J3, J4, L3, L4,
N3, N4, R3, R4, T4
1.8 V nominal
power supply voltage
VREF
ZOH
ZOL
A3, T3
J5
0.9 V nominal
input
input reference voltage
reserved for future use
reserved for future use
J6
input
CK
H1
differential input positive master clock input
differential input negative master clock input
LVCMOS inputs configuration control inputs
CK
J1
C0, C1
RESET
G6, G5
G2
LVCMOS input Asynchronous reset input (active LOW). Resets registers and
disables VREF data and clock differential-input receivers.
CSR, DCS
D1 to D25
DODT
J2, H2
SSTL_18 input Chip select inputs (active LOW). Disables data outputs
switching when both inputs are HIGH.[2]
[1]
SSTL_18 input Data inputs. Clocked in on the crossing of the rising edge of
CK and the falling edge of CK.
[1]
[1]
[1]
SSTL_18 input The outputs of this register will not be suspended by DCS and
CSR control.
DCKE
SSTL_18 input The outputs of this register will not be suspended by DCS and
CSR control.
Q1 to Q25,
1.8 V CMOS
The outputs that are suspended by DCS and CSR control[3].
Q1A to Q14A,
Q1B to Q14B
[1]
[1]
[1]
QCS, QCSA,
QCSB
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
QODT, QODTA,
QODTB
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
QCKE, QCKEA,
QCKEB
1.8 V CMOS
Data outputs that will not be suspended by DCS and CSR
control.
n.c.
A2, D2, G1
-
-
Not connected. Ball present but no internal connection to the
die.
[1]
DNU
Do-not-use. Ball internally connected to the die which should
be left open-circuit.
[1] Depends on configuration. See Figure 3, Figure 4, and Figure 5 for ball number.
[2] Configurations:
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
[3] Configurations:
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
SSTUA32864_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
6 of 20
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
7. Functional description
7.1 Function table
Table 3.
Function table (each flip-flop)
L = LOW voltage level; H = HIGH voltage level; X = don’t care; ↑ = LOW-to-HIGH transition;
↓ = HIGH-to-LOW transition
Inputs
CSR
Outputs[1]
RESET
DCS
CK
CK
Dn,
DODT,
DCKE
Qn
QCS
QODT,
QCKE
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
↑
↓
L
H
X
L
L
H
L
L
L
H
↑
↓
L
L
L or H
L or H
Q0
L
Q0
L
Q0
L
L
H
H
H
L
↑
↓
L
↑
↓
H
X
L
H
L
H
L
L or H
L or H
Q0
L
Q0
H
Q0
L
H
H
H
H
H
H
↑
↓
L
↑
L or H
↑
↓
L or H
↓
H
X
L
H
H
H
L
Q0
Q0
Q0
Q0
L
Q0
H
Q0
L
H
H
H
↑
↓
H
X
H
H
L or H
L or H
Q0
L
Q0
L
X or
X or
X or
X or
X or
floating
floating
floating
floating
floating
[1] Q0 is the previous state of the associated output.
SSTUA32864_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
7 of 20
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
V
VDD
VI
supply voltage
−0.5
−0.5[1]
−0.5[1]
+2.5
input voltage
receiver
+2.5[2]
VDD + 0.5[2]
±50
V
VO
IIK
output voltage
driver
V
input clamping current
output clamping current
output current
VI < 0 V or VI > VDD
VO < 0 V or VO > VDD
continuous; 0 V < VO < VDD
-
-
-
-
mA
mA
mA
mA
IOK
IO
±50
±50
ICCC
continuous current through
each VDD or GND pin
±100
Tstg
storage temperature
−65
2
+150
°C
kV
V
Vesd
electrostatic discharge
voltage
Human Body Model (HBM); 1.5 kΩ; 100 pF
Machine Model (MM); 0 Ω; 200 pF
-
-
200
[1] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
[2] This value is limited to 2.5 V maximum.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Operating conditions
Parameter
Conditions
Min
Typ
Max
Unit
V
supply voltage
1.7
-
2.0
Vref
reference voltage
termination voltage
input voltage
0.49 × VDD
0.50 × VDD 0.51 × VDD
V
VT
V
0
ref − 0.040
Vref
Vref + 0.040
V
VI
-
-
-
-
-
-
-
-
VDD
-
V
VIH(AC)
VIL(AC)
VIH(DC)
VIL(DC)
VIH
AC HIGH-level input voltage data inputs (Dn), CSR
AC LOW-level input voltage data inputs (Dn), CSR
DC HIGH-level input voltage data inputs (Dn), CSR
DC LOW-level input voltage data inputs (Dn), CSR
Vref + 0.250
V
-
V
-
ref − 0.250
V
Vref + 0.125
V
-
V
ref − 0.125
V
[1]
[1]
[2]
HIGH-level input voltage
LOW-level input voltage
RESET, Cn
RESET, Cn
0.65 × VDD
VDD
V
VIL
-
0.35 × VDD
1.125
V
VICR
common mode input voltage CK, CK
range
0.675
V
[2]
VID
IOH
IOL
differential input voltage
HIGH-level output current
LOW-level output current
ambient temperature
CK, CK
600
-
-
-
-
-
mV
mA
mA
°C
-
−8
8
-
Tamb
operating in free air
0
+70
[1] The RESET and Cn inputs of the device must be held at valid logic levels (not floating) to ensure proper device operation.
[2] The differential inputs must not be floating, unless RESET is LOW.
SSTUA32864_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
8 of 20
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
10. Characteristics
Table 6.
Characteristics
Recommended operating conditions; Tamb = 0 °C to +70 °C; all voltages are referenced to GND (ground = 0 V);
unless otherwise specified.
Symbol Parameter
Conditions
Min
1.2
-
Typ
Max
-
Unit
V
VOH
VOL
II
HIGH-level output voltage IOH = −6 mA; VDD = 1.7 V
-
-
-
-
LOW-level output voltage
input current
IOL = 6 mA; VDD = 1.7 V
0.5
+5
2
V
all inputs; VI = VDD or GND; VDD = 2.0 V
−5
-
µA
mA
IDD
supply current
static standby; RESET = GND; IO = 0 mA;
V
DD = 2.0 V
static operating; RESET = VDD; IO = 0 mA;
DD = 2.0 V; VI = VIH(AC) or VIL(AC)
dynamic operating current clock only; RESET = VDD
-
-
-
40
-
mA
V
IDDD
;
16
µA
per MHz
VI = VIH(AC) or VIL(AC); CK and CK switching
at 50 % duty cycle. IO = 0 mA; VDD = 2.0 V
per each data input, 1 : 1 mode;
RESET = VDD; VI = VIH(AC) or VIL(AC)
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
-
11
19
-
µA
µA
;
VDD = 2.0 V
per each data input, 1 : 2 mode;
-
-
RESET = VDD; VI = VIH(AC) or VIL(AC)
;
CK and CK switching at 50 % duty cycle.
One data input switching at half clock
frequency, 50 % duty cycle. IO = 0 mA;
V
DD = 2.0 V
data inputs, CSR; VI = Vref ± 250 mV;
DD = 1.8 V
CK and CK; VICR = 0.9 V; VID = 600 mV;
DD = 1.8 V
Ci
input capacitance
2.5
2
-
-
-
3.5
3
pF
pF
pF
V
V
RESET; VI = VDD or GND; VDD = 1.8 V
2
4
SSTUA32864_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
9 of 20
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
Table 7.
Timing requirements
Recommended operating conditions; Tamb = 0 °C to +70 °C; VDD = 1.8 V ± 0.1 V; unless otherwise specified.
See Figure 6 through Figure 11.
Symbol
fclock
tW
Parameter
Conditions
Min
-
Typ
Max
Unit
MHz
ns
clock frequency
-
-
-
-
-
-
-
450
pulse width
CK, CK HIGH or LOW
1
-
[1][2]
[1][3]
tACT
differential inputs active time
differential inputs inactive time
set-up time
-
10
15
-
ns
tINACT
tsu
-
ns
DCS before CK ↑, CK ↓, CSR HIGH
DCS before CK ↑, CK ↓, CSR LOW
0.7
0.5
0.5
ns
-
ns
CSR, ODT, CKE, and data before
-
ns
CK ↑, CK ↓
th
hold time
DCS, CSR, ODT, CKE, and data
0.5
-
-
ns
after CK ↑, CK ↓
[1] This parameter is not necessarily production tested.
[2] Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH.
[3] Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 8.
Switching characteristics
Recommended operating conditions; Tamb = 0 °C to +70 °C; VDD = 1.8 V ± 0.1 V;
Class I, Vref = VT = VDD × 0.5 and CL = 10 pF; unless otherwise specified. See Figure 6 through Figure 11.
Symbol
fmax
Parameter
Conditions
Min
450
1.2
-
Typ
Max
-
Unit
MHz
ns
maximum input clock frequency
peak propagation delay
-
-
-
[1]
tPDM
CK and CK to output
CK and CK to output
1.8
2.0
[1][2]
tPDMSS
simultaneous switching peak
propagation delay
ns
tPHL
HIGH-to-LOW propagation delay
RESET to output
-
-
3
ns
[1] Includes 350 ps of test-load transmission line delay.
[2] This parameter is not necessarily production tested.
Table 9.
Output edge rates
Recommended operating conditions; VDD = 1.8 V ± 0.1 V; unless otherwise specified.
Symbol
dV/dt_r
dV/dt_f
dV/dt_∆
Parameter
Conditions
Min
Typ
Max
Unit
V/ns
V/ns
V/ns
rising edge slew rate
falling edge slew rate
1
1
-
-
-
-
4
4
1
absolute difference between dV/dt_r
and dV/dt_f
SSTUA32864_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2007
10 of 20
SSTUA32864
NXP Semiconductors
1.8 V configurable registered buffer for DDR2-667 RDIMM applications
11. Test information
11.1 Test circuit
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
The outputs are measured one at a time with one transition per measurement.
V
DD
DUT
delay = 350 ps
= 50 Ω
R
= 1000 Ω
= 1000 Ω
L
50 Ω
Z
o
CK
CK
CK inputs
OUT
(1)
= 30 pF
C
L
R
L
test point
R
L
= 100 Ω
test point
002aaa371
(1) CL includes probe and jig capacitance.
Fig 6. Load circuit
LVCMOS
V
DD
0.5V
0.5V
RESET
DD
DD
0 V
t
t
ACT
INACT
90 %
(1)
DD
I
10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 7. Voltage and current waveforms; inputs active and inactive times
t
W
V
V
IH
IL
V
input
V
V
ICR
ID
ICR
002aaa373
VID = 600 mV
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 8. Voltage waveforms; pulse duration
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CK
V
V
ICR
ID
CK
t
t
h
su
V
V
IH
IL
input
V
ref
V
ref
002aaa374
VID = 600 mV
Vref = 0.5VDD
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 9. Voltage waveforms; setup and hold times
CK
V
V
V
i(p-p)
ICR
ICR
CK
t
t
PHL
PLH
V
V
OH
OL
V
output
T
002aaa375
tPLH and tPHL are the same as tPD
.
Fig 10. Voltage waveforms; propagation delay times (clock to output)
LVCMOS
V
V
V
V
IH
RESET
0.5V
DD
IL
t
PHL
OH
OL
output
V
T
002aaa376
tPLH and tPHL are the same as tPD
.
VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs.
VIL = Vref − 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 11. Voltage waveforms; propagation delay times (reset to output)
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11.2 Output slew rate measurement
VDD = 1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z0 = 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
V
DD
R
DUT
= 50 Ω
L
OUT
test point
002aaa377
(1)
= 10 pF
C
L
(1) CL includes probe and jig capacitance.
Fig 12. Load circuit, HIGH-to-LOW slew measurement
output
V
OH
80 %
dv_f
20 %
V
OL
dt_f
002aaa378
Fig 13. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
test point
(1)
= 10 pF
C
L
R
L
= 50 Ω
002aaa379
(1) CL includes probe and jig capacitance.
Fig 14. Load circuit, LOW-to-HIGH slew measurement
dt_r
V
V
OH
80 %
dv_r
20 %
output
OL
002aaa380
Fig 15. Voltage waveforms, LOW-to-HIGH slew rate measurement
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12. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
B
A
D
ball A1
index area
A
2
A
E
A
1
detail X
e
1
C
1/2 e
y
y
v M
w M
C
C
A B
C
1
e
b
T
R
P
N
e
M
L
K
J
H
G
F
e
2
1/2 e
E
D
C
B
A
ball A1
index area
1
2
3
4
5
6
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
b
e
e
e
v
w
y
y
1
D
E
1
2
1
2
max.
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
13.6
13.4
mm
1.5
4
12
0.1
0.2
0.8
0.15
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
00-03-04
03-02-05
SOT536-1
Fig 16. Package outline SOT536-1 (LFBGA96)
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13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 11. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 17.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 12. Abbreviations
Acronym
CMOS
DDR
Description
Complementary Metal Oxide Semiconductor
Double Data Rate
DIMM
Dual In-line Memory Module
LVCMOS
PRR
Low Voltage Complementary Metal Oxide Semiconductor
Pulse Repetition Rate
RDIMM
SSTL
Registered Dual In-line Memory Module
Stub Series Terminated Logic
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15. Revision history
Table 13. Revision history
Document ID
SSTUA32864_2
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20070309
Product data sheet
SSTUA32864_1
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Table 4 “Limiting values”:
–
–
–
–
changed Parameter for VI to “input voltage”; moved “receiver” to Conditions
changed Parameter for VO to “output voltage”; moved “driver” to Conditions
changed Parameter for IO to “output current”; moved “continuous” to Conditions
added Vesd specifications
• Table 5 “Operating conditions”:
changed symbol “VTT” to “VT”
• Table 6 “Characteristics”:
–
–
Symbol IDD: changed Parameter to “supply current”; moved “static standby” and “static
operating” to Conditions
–
–
IDD, supply current, static standby: changed Max value from “100 µA” to “2 mA”
Symbol IDDD: changed Parameter to “dynamic operating current per MHz”; moved “clock
only”, “per each data input, 1 ; 1 mode”, and “per each data input, 1 : 2 mode” to Conditions
–
Symbol Ci: changed Parameter to “input capacitance”; moved “data inputs, CSR”,
“CK and CK”, and “RESET” to Conditions
• Table 7 “Timing requirements”, Symbol tW: changed Parameter to “pulse width”; moved “CK, CK
HIGH or LOW” to Conditions
• Table 8 “Switching characteristics”:
–
–
–
–
changed Symbol “fMAX” to “fmax”
changed Parameter for tPDM to “peak propagation delay”
changed Parameter for tPDMSS to “simultaneous switching peak propagation delay”
changed Parameter for tPHL to “HIGH-to-LOW propagation delay”
SSTUA32864_1
(9397 750 14757)
20050512
Product data sheet
-
-
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
16.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
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Product data sheet
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18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
7.1
8
Functional description . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 9
9
10
11
11.1
11.2
Test information. . . . . . . . . . . . . . . . . . . . . . . . 11
Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output slew rate measurement. . . . . . . . . . . . 13
12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Introduction to soldering . . . . . . . . . . . . . . . . . 15
Wave and reflow soldering . . . . . . . . . . . . . . . 15
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16
13.1
13.2
13.3
13.4
14
15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 March 2007
Document identifier: SSTUA32864_2
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