ZSSC1751 [IDT]
Data Acquisition System Basis Chip;
| 型号： | ZSSC1751 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Data Acquisition System Basis Chip |
| 文件： | 总116页 (文件大小：1405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZSSC1750 / ZSSC1751
Data Acquisition
Datasheet
System Basis Chip
Brief Description
Benefits
The ZSSC1750 and ZSSC1751 are System Basis
Chips (SBCs) with a dual-channel ADC for battery
sensing/management in automotive, industrial, and
medical systems. The ZSSC1750 and ZSSC1751
feature an SPI interface; in addition, the ZSSC1750
has an integrated LIN 2.1 transceiver.
•
Integrated, precision measurement solution for
accurate prediction of battery state of health
(SOH), state of charge (SOC), or state of
function (SOF)
•
Robust power-on-reset (POR) concept for harsh
automotive environments
One of the two input channels measures the battery
current IBAT via the voltage drop at the external shunt
resistor. The second channel measures the battery
voltage VBAT and the temperature.
•
•
•
•
•
On-chip precision oscillator accuracy: ±1%
On-chip low-power oscillator
Only a few external components needed
Easy communication via SPI interface
By simultaneously measuring VBAT and IBAT, it is
possible to determine dynamically the internal
resistance of the battery, Rdi, which is correlated
with the state-of-health (SOH) of the battery. By
integrating IBAT, it is possible to determine the state-
of-charge (SOC) and the state-of-function (SOF) of
the battery.
Power supply, interrupt, and reset signals for
external microcontroller
•
•
Watchdog timer with dedicated oscillator
Industry’s smallest footprint allows minimal
module size and cost
•
AEC-Q100 qualified solution
During Sleep Mode, the system makes periodic
measurements to monitor the discharge of the
battery. Measurement cycles are controlled by user
software and include various wake-up conditions.
The ZSSC1750/51 is optimized for ultra-low power
consumption drawing only 60µA or less in this mode.
Available Support
•
•
Evaluation Kit
Application Notes
Physical Characteristics
Features
•
•
•
Operation temperature up to -40°C to +125°C
Supply voltage: 4.2 to 18V
•
Two high-precision 24-bit sigma-delta ADCs
(18-bit with no missing codes);
Small footprint package: PQFN36 6x6 mm
sample rate: 1Hz to 16kHz
* FSR = full-scale range.
•
•
On-chip voltage reference (5ppm/K typical)
Current channel
Basic ZSSC1750/51 Application Circuit
.
.
.
.
IBAT offset error: ≤ 10mA
To Harness
IBAT resolution: ≤ 1mA
-
+
Car Chassis Ground
Programmable gain: 4 to 512
Max. differential input stage input range: ±300mV
3.3V, <30mA
LIN-I/F
(ZSSC1750 )
VDDP
LIN
VBAT
VDDE
•
•
Voltage channel
INP
INN
VDDA
.
.
Input range: 4 to 28.8V
RX
TX
VDD
Voltage accuracy: ±60ppm FSR* = 1.73mV
Rshunt
IRQN
MCU_RSTN
MCU_CLK
IRQ
RST
CLK (opt.)
Interface
to Host
(e.g. CAN)
Temperature channel
.
.
External temperature sensor (NTC)
NTH
I/F
ZSSC1750/51
SPI
VSSE
µC
Factory-calibrated internal temp. sensor: ±2°C
NTC
+
-
SPI
NTL
VSSA
Battery
•
•
LIN 2.1/SAE J2602-1 transceiver (ZSSC1750 only)
Typical current consumption
VSS
.
.
Normal Mode: 12mA
Sleep Mode: ≤ 60µA
© 2016 Integrated Device Technology, Inc.
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April 20, 2016
ZSSC1750 / ZSSC1751
Data Acquisition
System Basis Chip
Datasheet
Common
Ground
Analog
Block
VBAT
Digital
Block
ZSSC1750/51 Block Diagram
ZSSC1750/51 Analog Front End SBC
VDDP
WD_TIMER
IRQ_CTRL
OSC
LP_REG
VDDP_REG
VDDC_REG
SD_ADC
BG_REF
VDDE
VDDA
VDDC
SBC_PMU
GP_TIMER
SLEEPN
WDT_DIS
MCU_CLK
MCU_RSTN
IRQN
VDDA_REG
INP
DIGITAL
FILTER
CONFIG
REGISTER
RESULT
REGISTER
Applications
SHUNT
INN
PGA
• Intelligent battery monitoring in
automotive applications; start/stop
systems, e-bikes, scooters, and e-carts
VBAT
RREF
CSN
DIGITAL
FILTER
CALIBRATION
DATA PATH
SPI
SCLK
MISO
MOSI
SD_ADC
NTH
NTC
• Battery monitoring in Industrial, medical
and photovoltaic applications;
+
–
MUX
BATTERY
NTL
• High precision data acquisition
RXD
TXD
LIN_PHYS (1)
LIN
LIN
1) Available in ZSSC1750 only
ZSSC1751 Typical Application Circuit
ZSSC1750 Typical Application Circuit
Cddl
10nF
Cddl
10nF
Cddc
2.2µF
Cddc
2.2µF
Rbat
Rbat
LIN
BAT+
BAT+
Clin
220pF
Cbat
100nF
Cbat
100nF
Cddp
2.2µF
Cddp
2.2µF
100Ω
100Ω
VBAT
VDDE
VBAT
VDDE
NC
VSS
LIN
Ddde
1
1
Ddde
Rdde Cdde1
Cdde2
Rdde Cdde1
Cdde2
VSSLIN
TESTH
TESTL
BAS21 2.2Ω
BAS21 2.2Ω
10µF 100nF
10µF 100nF
VSSE
VSSA
INP
TESTH
TESTL
n.c
.
VSSE
VSSA
INP
.
n.c
n.c
.
n.c
.
Cinp
10nF
Cinp
10nF
Chassis
GND
Rinp
Chassis
GND
Rinp
wdt_dis
mcu_clk
WDT_DIS
MCU_CLK
wdt_dis
mcu_clk
WDT_DIS
MCU_CLK
220Ω
220Ω
Rshunt
Cin
100nF
Rshunt
Cin
100nF
100µΩ
ZSSC1751
Rinn
100µΩ
ZSSC1750
Rinn
INN
INN
BAT-
BAT-
220Ω
Cinn
10nF
220Ω
Cinn
10nF
VSSA
VDDA
STO
TCK
TMS
sto
tck
VSSA
VDDA
STO
TCK
TMS
sto
tck
Cdda
Cdda
Rref
75kΩ
Rref
75kΩ
470nF
470nF
NTH
NTL
tms
NTH
NTL
tms
TRSTN
VSSN
Rntc
10kΩ
Cntc
470pF
trstn
TRSTN
VSSN
Rntc
10kΩ
Cntc
470pF
trstn
NC
NC
RXD
VDDP
open
mcu_rstn irqn csn
sclk mosi miso
rxd
txd mcu_rstn irqn csn
sclk mosi miso
Ordering Information
Product Sales Code Description
Package
ZSSC1750EA3R
ZSSC1751EA3R
ZSSC1750KIT V1.1
ZSSC1750 Battery Sensing SBC—Temperature Range: -40°C to 125°C
ZSSC1751 Battery Sensing SBC—Temperature Range: -40°C to 125°C
PQFN36 6x6 mm, reel
PQFN36 6x6 mm, reel
ZSSC1750/51 Evaluation Kit: modular evaluation and development board for ZSSC1750/51, 3 IC samples, and
USB cable (software and documentation can be downloaded from www.IDT.com)
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance
specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an
implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property
rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated
Device Technology, Inc. All rights reserved.
© 2016 Integrated Device Technology, Inc.
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April 20, 2016
ZSSC1750 / ZSSC1751 Datasheet
Contents
1
IC Characteristics ............................................................................................................................................. 8
1.1 Absolute Maximum Ratings....................................................................................................................... 8
1.2 Recommended Operating Conditions ....................................................................................................... 9
1.3 Electrical Parameters .............................................................................................................................. 10
1.4 Timing Parameters .................................................................................................................................. 18
Circuit Description .......................................................................................................................................... 21
2.1 Overview.................................................................................................................................................. 21
2.2 SBC-to-MCU Interface Pins..................................................................................................................... 22
2.2.1 Digital I/Os........................................................................................................................................ 23
2.2.2 External Microcontroller (MCU) Supply Pins.................................................................................... 23
2.2.3 SLEEPN Power State Indicator Pin.................................................................................................. 23
2.3 System Power States .............................................................................................................................. 24
2.3.1 Full Power State (FP) ....................................................................................................................... 24
2.3.2 Low Power State (LP) ...................................................................................................................... 24
2.3.3 Ultra Low Power State (ULP) ........................................................................................................... 25
2.3.4 OFF Power State.............................................................................................................................. 25
ZSSC1750/51 Functional Block Descriptions ................................................................................................ 26
3.1 Serial Peripheral Interface (SPI Slave).................................................................................................... 26
3.1.1 SPI Protocol...................................................................................................................................... 26
3.2 SBC Register Map (RESULT REGISTER Block and CONFIG REGISTER Block) ................................28
3.3 ZSSC1750/51 Clock and Reset Logic..................................................................................................... 33
3.3.1 Clock Sources .................................................................................................................................. 33
3.3.2 Trimming the Low-Power Oscillator ................................................................................................. 34
3.3.3 Clock Trimming and Configuration Registers................................................................................... 35
3.3.4 Resets .............................................................................................................................................. 37
3.4 SBC Watchdog Timer (WD_TIMER Block) ............................................................................................. 39
3.4.1 Watchdog Registers ......................................................................................................................... 41
3.5 SBC Sleep Timer (GP_TIMER Block)..................................................................................................... 43
3.5.1 Sleep Timer Registers...................................................................................................................... 44
3.6 SBC Interrupt Controller (IRQ_CTRL Block)........................................................................................... 45
3.7 SBC Power Management Unit (SBC_PMU Block).................................................................................. 49
3.7.1 FP State............................................................................................................................................ 50
3.7.2 LP and ULP States........................................................................................................................... 51
3.7.3 OFF State......................................................................................................................................... 60
3.7.4 Registers for Power Configuration and the Discreet Current Measurement Count.........................61
3.8 ZSSC1750/51 ADC Unit.......................................................................................................................... 63
3.8.1 ADC Clocks ...................................................................................................................................... 64
3.8.2 ADC Data Path................................................................................................................................. 69
3.8.3 ADC Operating Modes and Result Registers................................................................................... 74
3.8.4 ADC Control and Conversion Timing ............................................................................................... 86
2
3
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ZSSC1750 / ZSSC1751 Datasheet
3.8.5 Diagnostic Features.......................................................................................................................... 96
3.8.6 Digital Features ................................................................................................................................ 97
3.9 SBC LIN Support Logic (for ZSSC1750 only) ....................................................................................... 100
3.9.1 LIN Wakeup Detection ................................................................................................................... 100
3.9.2 TXD Timeout Detection .................................................................................................................. 100
3.9.3 LIN Short Detection ........................................................................................................................ 101
3.9.4 LIN Testing ..................................................................................................................................... 102
3.10 ZSSC1750/51 OTP (CONFIG REGISTER)........................................................................................... 104
3.11 Miscellaneous Registers........................................................................................................................ 105
3.12 Voltage Regulators ................................................................................................................................ 108
3.12.1 VDDE.............................................................................................................................................. 108
3.12.2 VBAT .............................................................................................................................................. 108
3.12.3 VDDA.............................................................................................................................................. 108
3.12.4 VDDL .............................................................................................................................................. 109
3.12.5 VDDP.............................................................................................................................................. 109
3.12.6 VDDC ............................................................................................................................................. 109
ESD / EMC ................................................................................................................................................... 110
4.1 Electrostatic Discharge.......................................................................................................................... 110
4.2 Power System Ripple Factor................................................................................................................. 110
4.3 Application Circuit Examples for EMC Conformance............................................................................ 111
Pin Configuration and Package.................................................................................................................... 112
Ordering Information .................................................................................................................................... 115
Related Documents...................................................................................................................................... 115
Glossary ....................................................................................................................................................... 115
Document Revision History.......................................................................................................................... 116
4
5
6
7
8
9
List of Figures
Figure 1.1 Measurement Method for Determining VDDP Pin Current Capability..............................................17
Figure 1.2 SPI Protocol Timing.......................................................................................................................... 19
Figure 1.3 ZSSC1750/51 Power-Up and Power-Down Sequence ....................................................................20
Figure 2.1 Functional Block Diagram................................................................................................................. 21
Figure 2.2 ZSSC1750/51 Digital IO Interface .................................................................................................... 22
Figure 2.3 ZSSC1750/51 Power States............................................................................................................. 24
Figure 3.1 Read and Write Burst Access to the SBC ........................................................................................ 27
Figure 3.2 Structure of the Watchdog Timer...................................................................................................... 39
Figure 3.3 Structure of the Sleep Timer............................................................................................................. 43
Figure 3.4 Generation of Interrupt and Wake-up............................................................................................... 46
Figure 3.5 LP/ULP State without any Measurements........................................................................................ 52
Figure 3.6 LP/ULP State Performing Only Current Measurements...................................................................54
© 2016 Integrated Device Technology, Inc.
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ZSSC1750 / ZSSC1751 Datasheet
Figure 3.7 LP/ULP State Performing Current, Voltage, and Temperature Measurements
with discCvtCnt== 2..................................................................................................................... 56
Figure 3.8 LP/ULP State Performing Current, Voltage, and Temperature Measurements
with discCvtCnt== 5..................................................................................................................... 56
Figure 3.9 LP/ULP State Performing Current, Voltage, and Temperature Measurements
with discCvtCnt== 1..................................................................................................................... 57
Figure 3.10 LP/ULP State Performing Continuous Current-Only Measurements ...............................................58
Figure 3.11 Performing Continuous Current and Voltage Measurements during LP/ULP State.........................60
Figure 3.12 Functional Block Diagram of the Analog Measurement Subsystem ................................................64
Figure 3.13 FP ADC Clocking Scheme for sdmPos= sdmPos2= 2; sdmClkDivFp= 1;
sdmChopClkDiv= 0........................................................................................................................ 66
Figure 3.14 FP ADC Clocking for sdmPos= 1 and sdmPos2= 4; sdmClkDivFp= 1; sdmChopClkDiv= 0...66
Figure 3.15 FP ADC Clocking for sdmPos= 3 and sdmPos2= 0; sdmClkDivFp= 1; sdmChopClkDiv= 0...67
Figure 3.16 FP ADC Clocking for sdmPos= 0 and sdmPos2= 3; sdmClkDivFp= 1; sdmChopClkDiv= 0...67
Figure 3.17 LP/ULP ADC Clocking Scheme; sdmClkDivLp= 5; sdmChopClkDiv= 0 ...................................68
Figure 3.18 Functional Block Diagram of the Digital ADC Data Path..................................................................69
Figure 3.19 Data Post Correction ........................................................................................................................ 70
Figure 3.20 Data Representation through Data Post Correction including Over-Range and Overflow Levels...71
Figure 3.21 Common Enable for the “set overrange” and “set overflow” Interrupt Strobes for Current ..............72
Figure 3.22 Individual SRCS................................................................................................................................ 87
Figure 3.23 Individual MRCS (Example for Result Counter of 3) ........................................................................87
Figure 3.24 Continuous SRCS............................................................................................................................. 88
Figure 3.25 Continuous MRCS (Example for Result Counter of 3) .....................................................................88
Figure 3.26 Stopping Continuous SRCS ............................................................................................................. 89
Figure 3.27 Stopping Continuous MRCS (Example for Result Counter of 3)......................................................89
Figure 3.28 Interrupting a Continuous SRCS ...................................................................................................... 90
Figure 3.29 Interrupting a Continuous MRCS (Example for Result Counter of 3)...............................................90
Figure 3.30 Signal Behavior of adcMode............................................................................................................ 91
Figure 3.31 Timing for Current, Voltage, and Internal Temperature Measurements without Chopping for
Different Configurations of the Average Filter .................................................................................. 93
Figure 3.32 Timing for External Temperature Measurements without Chopping when
No Average Filter is Enabled............................................................................................................ 94
Figure 3.33 Timing for Current, Voltage, and Internal Temperature Measurements using Chopping.................95
Figure 3.34 Timing for External Temperature Measurements using Chopping...................................................96
Figure 3.35 Usage of Register adcCaccThfor the Digital ADC BIST ................................................................98
Figure 3.36 Bit Stream of ADC Interface Test at STO Pad ................................................................................. 99
Figure 3.37 Protection Logic of the LIN TXD Line ............................................................................................. 100
Figure 3.38 Waveform Showing the Gating Principle for Non-zero Values of linShortDelay...................... 101
Figure 4.1 Optional External Components for ZSSC1750............................................................................... 111
Figure 4.2 Optional External Components for ZSSC1751............................................................................... 111
Figure 5.1 ZSSC1750/51 PQFN36 6x6mm Package Pin-out (Top View) .......................................................112
Figure 5.2 Package Drawing of the ZSSC1750/51.......................................................................................... 114
© 2016 Integrated Device Technology, Inc.
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April 20, 2016
ZSSC1750 / ZSSC1751 Datasheet
List of Tables
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Absolute Maximum Ratings (referenced to VSSE)............................................................................. 8
Operating Conditions .......................................................................................................................... 9
Electrical Specifications.................................................................................................................... 10
Timing Parameters ........................................................................................................................... 18
SBC Register Map ............................................................................................................................ 28
Register irefOsc............................................................................................................................ 35
Register irefLpOsc........................................................................................................................ 35
Register lpOscTrim ........................................................................................................................... 36
Register lpOscTrimCnt................................................................................................................. 36
Register swRst................................................................................................................................. 38
Register cmdExe............................................................................................................................... 38
Register funcDis............................................................................................................................ 39
Resolution and Maximum Timeout for Prescaler Configurations .....................................................40
Table 3.10 Register wdogPresetVal............................................................................................................... 41
Table 3.11 Register wdogCnt............................................................................................................................ 41
Table 3.12 Register wdogCfg............................................................................................................................ 42
Table 3.13 Register sleepTAdcCmp................................................................................................................. 44
Table 3.14 Register sleepTCmp........................................................................................................................ 45
Table 3.15 Register sleepTCurCnt................................................................................................................. 45
Table 3.16 Register irqStat............................................................................................................................ 48
Table 3.17 Register irqEna............................................................................................................................... 48
Table 3.18 Register pwrCfgFp.......................................................................................................................... 61
Table 3.19 Register pwrCfgLp.......................................................................................................................... 62
Table 3.20 Register gotoPd............................................................................................................................... 63
Table 3.21 Register discCvtCnt...................................................................................................................... 63
Table 3.22 Value for sdmPos2Depending on sdmPosand Desired Clock Delay from SDM to Chop Clock....65
Table 3.23 Register sdmClkCfgLp.................................................................................................................... 68
Table 3.24 Register sdmClkCfgFp.................................................................................................................... 68
Table 3.25 Register adcCoff............................................................................................................................ 72
Table 3.26 Register adcCgan............................................................................................................................ 72
Table 3.27 Register adcVoff............................................................................................................................ 72
Table 3.28 Register adcVgan............................................................................................................................ 73
Table 3.29 Register adcToff............................................................................................................................ 73
Table 3.30 Register adcTgan............................................................................................................................ 73
Table 3.31 Register adcPoCoGain.................................................................................................................... 74
Table 3.32 Register adcCdat............................................................................................................................ 75
Table 3.33 Register adcVdat............................................................................................................................ 75
Table 3.34 Register adcTdat............................................................................................................................ 75
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ZSSC1750 / ZSSC1751 Datasheet
Table 3.35 Register adcRdat............................................................................................................................ 75
Table 3.36 Register adcGain............................................................................................................................ 76
Table 3.37 Register adcCrcl............................................................................................................................ 77
Table 3.38 Register adcCrcv............................................................................................................................ 77
Table 3.39 Register adcVrcl............................................................................................................................ 77
Table 3.40 Register adcVrcv............................................................................................................................ 77
Table 3.41 Register adcCrth............................................................................................................................ 79
Table 3.42 Register adcCtcl............................................................................................................................ 79
Table 3.43 Register adcCtcv............................................................................................................................ 79
Table 3.44 Register adcCaccTh........................................................................................................................ 80
Table 3.45 Register adcCaccu.......................................................................................................................... 80
Table 3.46 Register adcVTh............................................................................................................................... 81
Table 3.47 Register adcVaccu.......................................................................................................................... 81
Table 3.48 Register adcCmax............................................................................................................................ 82
Table 3.49 Register adcCmin............................................................................................................................ 82
Table 3.50 Register adcVmax............................................................................................................................ 82
Table 3.51 Register adcVmin............................................................................................................................ 82
Table 3.52 Register adcTmax............................................................................................................................ 83
Table 3.53 Register adcTmin............................................................................................................................ 83
Table 3.54 Register adcAcmp............................................................................................................................ 84
Table 3.55 Register adcGomd............................................................................................................................ 85
Table 3.56 Register adcSamp............................................................................................................................ 85
Table 3.57 adcModeSettings............................................................................................................................. 86
Table 3.58 Register adcCtrl............................................................................................................................ 92
Table 3.59 Register adcChan............................................................................................................................ 97
Table 3.60 Example Results of BIST.................................................................................................................. 98
Table 3.61 Register adcDiag............................................................................................................................ 99
Table 3.62 Register currentSrcEna............................................................................................................... 99
Table 3.63 ZSSC1750 Register linCfg.......................................................................................................... 102
Table 3.64 ZSSC1750 Register linShortFilter........................................................................................ 103
Table 3.65 ZSSC1750 Register linShortDelay........................................................................................... 103
Table 3.66 ZSSC1750 Register linWuDelay..................................................................................................... 103
Table 3.67 OTP Memory Map .......................................................................................................................... 104
Table 3.68 Register pullResEna.................................................................................................................... 106
Table 3.69 Register versionCode.................................................................................................................. 106
Table 3.70 Register pwrTrim.......................................................................................................................... 107
Table 3.71 Register ibiasLinTrim............................................................................................................... 107
Table 4.1
Table 5.1
ESD Protection According to AEC-Q100 Rev. G ........................................................................... 110
ZSSC1750/51 Pins Description ...................................................................................................... 112
© 2016 Integrated Device Technology, Inc.
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April 20, 2016
ZSSC1750 / ZSSC1751 Datasheet
1 IC Characteristics
The absolute maximum ratings are stress ratings only. The ZSSC1750/51 might not function or be operable
above the recommended operating conditions. Stresses exceeding the absolute maximum ratings might also
damage the device. In addition, extended exposure to stresses above the recommended operating conditions
might affect device reliability. IDT does not recommend designing to the “Absolute Maximum Ratings.”
1.1 Absolute Maximum Ratings
Table 1.1 Absolute Maximum Ratings (referenced to VSSE)
No
Parameter
External power supply
Symbol
VDDE
Conditions
Min
Max
40
Unit
V
VSSE-0.3
VSSE-0.3
VSSE-0.3
-18
1.1.1.
1.1.2.
1.1.3.
1.1.4.
Current sensing, INP pin
Current sensing, INN pin
Voltage sensing, VBAT pin
VINP
VDDA+0.3
VDDA+0.3
33
V
VINN
V
VVBAT
V
1h over
lifetime
Voltage sensing, VBAT pin
VVBAT
-18
40
V
1.1.5.
Temperature sensing, NTH pin
Temperature sensing, NTL pin
LIN bus interface, LIN pin
VNTH
VNTL
VLIN
VSSE-0.3
VSSE-0.3
-16
VDDA+0.3
VDDA+0.3
33
V
V
V
1.1.6.
1.1.7.
1.1.8.
1h over
lifetime
LIN bus interface, LIN pin
VLIN
-16
40
V
1.1.9.
Digital IO pins
VIO
TAMB
Tj
VSSE-0.3
VDDP+0.3
125
V
1.1.10.
1.1.11.
1.1.12.
1.1.13.
Ambient temperature under bias
Junction temperature
Storage temperature
°C
°C
°C
135
TSTOR
-50
125
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ZSSC1750 / ZSSC1751 Datasheet
1.2 Recommended Operating Conditions
Table 1.2 Operating Conditions
No.
Parameter
Symbol
Conditions
Min
Typ.
Max
Unit
Operating temperature range
TAMB
Ambient temperature;
RTHJA=27K/W
-40
115
°C
1.2.1
TAMB_Ext
Extended temperature range
Ambient temperature;
reduced accuracies
-40
6
125
18
°C
V
1.2.2
1.2.3
Supply voltage at BAT+
VBAT+
13
terminal1) for normal operation
Minimum supply voltage at
VDDE pin:
Normal accuracy for
current and temperature
measurements
4.8
a) When BAT+ < 6V, i.e.
operation with low battery
Reduced accuracy for
voltage measurements
VDDE_low
V
1.2.4
b) When VBAT = VDDE , i.e.
without using Ddde and
Rdde 1)
Reduced accuracy for all
measurements
4.2
0
Digital input voltage LOW
Digital input voltage HIGH
VIL
VIH
0.3 VDDP
*
V
V
1.2.5
1.2.6
0.7 VDDP
*
VDDP
1) See application diagram on page 2.
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ZSSC1750 / ZSSC1751 Datasheet
1.3 Electrical Parameters
Note: See important notes at the end of the following table. See section 3.7 for definitions of the ULP and OFF
power states.
Table 1.3 Electrical Specifications
No.
Parameter
Symbol
Conditions
Min
Typ. Max
Unit
Supply
1.3.1.
Average supply current at VDDE
IDDE_avg
Normal Mode
(FP State,
10
12
14
mA
both ADCs on)
1.3.2.
1.3.3.
Average power dissipation
PDDE_avg
IDDE_slp
Normal Mode,
VDDE=13V
130
156
55
182
mW
µA
Current at VDDE in Sleep Mode
(ULP State with no
measurement)
TAMB =room
temperature
(RT)
TAMB = 115°C
100
160
µA
1.3.4.
Average current at VDDE in
Comparator Mode
IDDE_cmp
TAMB =RT
µA
(ULP State with wake-up interval
= 30s and current ADC only)
1.3.5.
1.3.6.
1.3.7.
Average current at VDDE in OFF
State (no measurements)
IDDE_off
VDDA
VDDL
TAMB =RT
50
µA
V
Internal analog power supply
voltage, VDDA pin
2.4
2.5
2.6
Internal digital power supply
voltage, VDDL pin
1.62
1.8
1.98
V
External Microcontroller (MCU) Supply
1.3.8.
External microcontroller core
power supply voltage, VDDC pin
VDDC
Default
1.62
1.08
1.8
1.2
1.98
1.32
V
V
Configuration
option (see
section 2.2)
1.3.9.
External microcontroller power
supply voltage (periphery), VDDP
pin
VDDP
Default
2.97
2.25
3.3
2.5
3.63
2.75
V
V
Configuration
option (see
section 2.2)
1.3.10. Output current of VDDP regulator
IVDDP_OUT
-
-
40
mA
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ZSSC1750 / ZSSC1751 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ. Max
Unit
1.3.11. Output current capability of VDDP
pin
IVDDP
See Figure 1.1
for test circuit
-
-
30
mA
1.3.12. Output current of VDDC regulator
IVDDC_OUT
IVDDC
40
40
mA
mA
1.3.13. Output current capability of
VDDC pin
Digital IO Pins Parameters (VDDP = 3.3V)
1.3.14. Input low-to-high threshold
voltage
% of
VDDP
VLH_th
VHL_th
55
35
60
40
65
45
1.3.15. Input high-to-low threshold
voltage
% of
VDDP
1.3.16.
Internal pull-down resistor
RPULL_down
ILEAK_I/O
Vpin = VDDP
IOUT = I_I/O
70
-
190
-
310
1
kΩ
1.3.17. Leakage current
µA
1.3.18.
% of
VDDP
Output low level
VOL
VOH
-
-
-
20
-
1.3.19.
% of
VDDP
Output high level
IOUT = I_I/O
80
-
1.3.20. Output low level of SLEEPN pin
1.3.21. Output high level of SLEEPN pin
1.3.22.
VL_SLEEPN
VH_SLEEPN
ISLEEPN = 0.1mA
-
0.40
-
V
ISLEEPN = 0.1mA 1.40
-
-
V
MCU_CLK pin
All other IOs
SLEEPN pin
-
-
3.0
1.5
0.1
6.5
mA
mA
mA
pF
I_I/O
1.3.23. Pin output current 1)
-
1.3.24.
ISLEEPN
C_I/O
-
-
1.3.25. Pin capacitance 1)
Current Channel
4.5
5.5
1.3.26. Input signal range 1)
RangeC
Gain = 4
-300
-150
-75
300
150
75
mV
mV
mV
mV
mV
mV
mV
mV
nA
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 256
Gain = 512
TAMB = 25°C
-38
38
-19
19
-9.5
-4.7
-2.3
-3
9.5
4.7
2.3
+3
1.3.27. Input leakage current 1)
ILEAK_C
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ZSSC1750 / ZSSC1751 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ. Max
Unit
1.3.28. Input offset current 1)
IOFFSET_C
For input signal
< 10mV
0.5
1.5
nA
1.3.29. Conversion rate 1), 2)
RateC
OSRC
Programmable
Programmable
1
16000
256
Hz
1)
1.3.30. Oversampling ratio (OSR)
(Sinc4 decimation filter)
1.3.31. No missing codes 1)
32
18
NMCC
INL
Bits
1.3.32. Integral nonlinearity 1), 3)
Maximum input
range
±10
±3
±60
ppm of
FSR 4)
1)
1.3.33. PGA gain range
APGA
4
512
1
1.3.34. Total gain error 1)
1.3.35. Gain drift 1)
1.3.36. Offset error after calibration 1)
errPGA_C
-1
%
ppm/°C
µV
err_driftPGA_C
VOFFSET_C
Normal Mode
chop on,
-2
2
external short
(VSSA)
Low-Power
State, chop on,
external short
(VSSA)
-0.6
+0.6
µV
1.3.37. Offset error drift 1)
VOFFSET DRIFT C Chop on
±20
±80
1.1
nV/oC
nV/oC
µVRMS
_
_
Chop off
1.3.38. Output noise with chop on 1)
VNOISE_C
Gain = 512,
conversion rate
= 10Hz
Gain = 512,
conversion rate
= 1kHz
1.1
3
µVRMS
µVRMS
µVRMS
Gain = 32,
conversion rate
= 1kHz
Gain = 4,
11
conversion rate
= 1kHz
© 2016 Integrated Device Technology, Inc.
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ZSSC1750 / ZSSC1751 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ. Max
Unit
1.3.39. Current offset 1)
IBAT_offset
Chop on,
gain = 512,
10
mA
Rshunt = 100µΩ
1.3.40. Resolution 1)
Chop on,
gain = 512,
IRES
1
mA
Rshunt = 100µΩ
Voltage Channel
1.3.41. Input signal range (at VBAT pin) 1)
RangeV
Resistive
divider (1:24)
0
28.8
V
V
V
1.3.42. Input measurement range 1)
1.3.43. Input valid range for ADC 1)
1.3.44. Voltage resistive divider ratio 1)
Rangemeas_V Resistive
divider (1:24)
3.6
28.8
RangeADC_V Resistive
divider (1:24)
0.15
1.2
RatioV
24
1.3.45. Resistor divider mismatch drift 1)
1.3.46. Conversion rate 1), 2)
Ratio_misdrift_v
RateV
±3
ppm/ºC
Hz
Programmable
Programmable
1
16000
256
1.3.47. Oversampling ratio
(Sinc4 decimation filter) 1)
OSRV
32
1.3.48. No missing codes 1)
1.3.49. Integral nonlinearity 1), 3)
NMCV
INLV
18
Bits
Maximum input
range
±10
±60
ppm of
FSR 4)
1.3.50. Total gain error 1)
errPGA_V
-0.25
0.25
%
(includes resistor divider
mismatch)
1.3.51. Gain drift 1)
err_driftPGA_V
VOFFSET_V
±3
ppm/°C
µV
1.3.52. Offset error after calibration:
Normal Mode 1)
Chop on
external short
(1.25V)
200
Chop off
1
mV
external short
(1.25V)
1.3.53. Offset error drift 1)
VOFFSET DRIFT V Chop on
±10
±20
µV/°C
µV/°C
_
_
Chop off
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ZSSC1750 / ZSSC1751 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ. Max
Unit
1.3.54. Output noise 1)
VNOISE_V
Chop on
30
50
µVRMS
gain = 1,
conversion rate
=10Hz
Chop on
1
µVRMS
gain = 1,
conversion rate
= 1kHz
Temperature Channel (External NTC/Reference Resistor and Internal Temperature Sensor)
1.3.55. Voltage drop over NTC resistor 1)
VNTC
VREF_Res
RateT
OSRT
INLT
0
0
1.2
1.2
V
V
1.3.56. Voltage drop over reference
resistor 1)
1.3.57. Conversion rate 1)
Programmable
Programmable
1
16000
256
Hz
1.3.58. Oversampling ratio
(Sinc4 decimation filter) 1)
1.3.59. Integral nonlinearity 1), 3)
32
Maximum input
range
±10
±60
ppm
of FSR
1.3.60. No missing codes 1)
NMCT
16
Bit
µV
1.3.61. Offset error after ZSSC1750/51
calibration 1)
VOFFSET_T
Normal Mode,
chop on,
external short
(1.25V)
-100
100
2
Normal Mode,
chop off,
-2
mV
external short
(1.25V)
1.3.62. Offset error drift 1)
1.3.63. Output noise 1)
VOFFSET DRIFT T Chop on
±10
±20
µV/oC
µV/oC
µVRMS
_
_
Chop off
VNOISE_T
Chop on,
50
gain = 1,
conversion
rate =500Hz
1.3.64. Resistor to ground at pin NTL 1)
GNDRES
RESITS
50
kΩ
Internal temperature sensor
1.3.65.
-
-
1/32
-
-
°C/LSB
resolution 1)
Linearity error of internal
1.3.66.
LEITS
±2
°C
temperature sensor 1)
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ZSSC1750 / ZSSC1751 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ. Max
Unit
Power-on Reset (POR)
1.3.67. Power-on reset threshold
1.3.68. Power-on-reset hysteresis
1.3.69. Low-voltage flag
VPORB
At VDDE
At VDDE
2.75
3.0
300
2.0
3.6
V
mV
V
HystPORB
low_voltage At VDDE
1.8
3.9
2.3
4.2
1.3.70. VDDP high 1)
vddp_high
At VDDE
4.05
V
(for VDDP = 3.3V configuration)
1.3.71. VDDP high hysteresis 1)
HystVDDP_high At VDDE
400
mV
Low-Power Voltage Reference
1.3.72. Reference bandgap voltage:
low-power
VBGL
1.16
-3
1.32
3
V
%
1.3.73. Accuracy
(including temperature drift)
1.3.74. Temperature coefficient 1)
Low-Power (LP) Oscillator
1.3.75. Frequency
TCVBGL
50
ppm/K
fLPO
125
kHz
%
1.3.76. Accuracy (including temperature
drift) 1)
-3
3
High-Precision Voltage Reference
1.3.77. Reference bandgap voltage:
high-precision
1.3.78. Temperature coefficient 1)
High-Precision (HP) Oscillator
1.3.79. Frequency
VBGH
Uncalibrated
1.16
-20
1.32
+20
V
TCVBGH
Calibrated
±5
20
ppm/K
fHPO
MHz
%
1.3.80. Accuracy
-1
1
(including temperature drift) 1)
LIN Interface
1.3.81. Current limitation for driver
dominant state 1)
LIN spec 2.1
Param 12
IBUS_LIM
40
-1
200
mA
mA
µA
1.3.82. Input leakage current, dominant
state, driver off 1)
LIN spec 2.1
Param 13
IBUS_PAS_dom
IBUS_PAS_rec
1.3.83. Input leakage current, recessive
state, driver off 1)
LIN spec 2.1
Param 14
20
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ZSSC1750 / ZSSC1751 Datasheet
No.
Parameter
Symbol
Conditions
Min
Typ. Max
Unit
1.3.84. Control unit disconnected from
ground 1)
LIN spec 2.1
Param 15
IBUS_NO_GND
-1
1
mA
1.3.85. VBAT supply disconnected 1)
LIN spec 2.1
Param 16
IBUS_NO_BAT
VBUSdom
VBUSrec
VBUS_CNT
VHYS
100
0.4
µA
VDDE
VDDE
VDDE
VDDE
V
1.3.86. Receiver dominant state,
VDDE > 7V 1)
LIN spec 2.1
Param 17
1.3.87. Receiver recessive state,
VDDE > 7V 1)
LIN spec 2.1
Param 18
0.6
1.3.88. Center of receiver threshold 1)
1.3.89. Receiver hysteresis voltage 1)
1.3.90. Voltage drop at serial diodes 1)
1.3.91. Battery shift 1)
LIN spec 2.1
Param 19
0.475
0.5
0.7
0.525
0.175
1
LIN spec 2.1
Param 20
LIN spec 2.1
Param 21
VSerDiode
VSHIFT_BAT
VBUS_GND
VSHIFT_Difference
RSLAVE
D1
0.4
LIN spec 2.1
Param 22
0.115
0.115
8
VBAT
VBAT
%
1.3.92. Ground shift 1)
LIN spec 2.1
Param 23
1.3.93. Difference between battery shift
and ground shift 1)
1.3.94. LIN pull-up resistor 1)
LIN spec 2.1
Param 24
0
LIN spec 2.1
Param 26
20
30
47
kΩ
1.3.95. Duty cycle 11)
LIN spec 2.1
Param 27
0.396
1.3.96. Duty cycle 2 1)
LIN spec 2.1
Param 28
D2
0.581
1.3.97. Duty cycle 3 1)
LIN spec 2.1
Param 29
D3
0.417
1.3.98. Duty cycle 4 1)
LIN spec 2.1
Param 30
D4
0.590
1.3.99. Receiver propagation delay 1)
LIN spec 2.1
Param 31
TRX_pdr
TRX_sym
6
2
µs
µs
1.3.100. Symmetry receiver propagation
delay, rising/falling edge 1)
LIN spec 2.1
Param 32
-2
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ZSSC1750 / ZSSC1751 Datasheet
No.
Parameter
Symbol
CSLAVE
CLIN
Conditions
Min
Typ. Max
Unit
pF
1.3.101. Capacitance of slave node 1)
LIN spec 2.1
Param 23
250
1.3.102. LIN pin capacitance 1)
-
-
30
pF
1) Not tested in production test; given by design and/or characterization.
2) Depends on chopping and OSR settings.
3) FSR = 1.2V
4) FSR = Full-scale input range of the ADCs. The input range is given in specification 1.3.26 for current, 1.3.41 for voltage, and
1.3.55 and 1.3.56 for external temperature.
Figure 1.1 Measurement Method for Determining VDDP Pin Current Capability
I
VDDP_OUT
I
VDDP
VDDP
I
IO=10mA
VDDP
VDD
ZSSC1750/51
External
MCU
VSS
VSSN
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ZSSC1750 / ZSSC1751 Datasheet
1.4 Timing Parameters
Table 1.4 Timing Parameters
No
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SPI Protocol Timing (See Figure 1.2)
SPI operational frequency 1)
1.4.1.
1.4.2.
-
-
-
8
-
MHz
ns
fSPI
SCLK clock period for registers
read/write 1)
125
tSCLKPreg
1.4.3.
1.4.4.
SCLK clock period for OTP read 1)
200
40
-
-
ns
tSCLKPotp
tSCLKW
SCLK clock pulse width 1)
50
60
%
tSCLKP
1.4.5.
1.4.6.
1.4.7.
1.4.8.
1.4.9.
CSN setup time 1)
CSN hold time 1)
50
50
300
20
10
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
tCSU
tCHD
tCHI
CSN high time 1)
-
MOSI data setup time 1)
MOSI data hold time 1)
-
tDSU
tDHD
tDACC
-
1.4.10. MISO data access time 1)
25
Timer 0 (Sleep Timer)
1.4.11. Time interval 1)
1.4.12. Time interval with post-scaler 1)
SLPTI1
SLPTI2
Programmable 0.1
Programmable
6553.5
466
s
h
1)
1.4.13. Resolution
SLPTI1res
100
ms
Timer 1 (Watchdog Timer WDT)
1.4.14. Time interval 1)
1.4.15. Resolution 1)
WDTI
Programmable
8µ
6553.5
100
s
WDTIres Programmable 0.008
ms
Startup Timing (See Figure 1.3)
1.4.16. PORB delay until analog blocks
settled1)
1
ms
TPORB_dly
1) Not tested in production test; given by design and/or characterization.
© 2016 Integrated Device Technology, Inc.
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ZSSC1750 / ZSSC1751 Datasheet
Figure 1.2 SPI Protocol Timing
tCHI
tSCLKP
CSN
t
CSU
t
SCLKW
t
CHD
SPI_CLK
MOSI
t
DSU DHD
t
7 (MSB)
0 (LSB)
t
DACC
MISO
7 (MSB)
0 (LSB)
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ZSSC1750 / ZSSC1751 Datasheet
Figure 1.3 ZSSC1750/51 Power-Up and Power-Down Sequence
VDDE
TYP
VPORBmax
VPORBmin
t
VDDL
t
t
PORB at STO pin
TPORB_dly
VDDC
t
VDDP
VDDA
t
t
STATE
ADC measurements can run
Supplied
Supplied
OFF
OFF
OFF
OFF
OFF
Running
Settled
SBC Digital
SBC Analog
MCU
Running
OFF
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ZSSC1750 / ZSSC1751 Datasheet
2 Circuit Description
2.1 Overview
The ZSSC1750/51 is a data acquisition System Basis Chip (SBC) assembled in a PQFN36 6x6mm package. It
contains a high voltage circuit, analog input stage including peripheral blocks, sigma-delta (ΣΔ) ADCs
(SD_ADC), digital filtering, and a LIN transceiver (for ZSSC1750 only). Communication between an external
microcontroller and the SBC is handled by a Serial Peripheral Interface (SPI). The functions of the ZSSC1750/51
are controlled by register settings. The circuit starts after power-on with default register and calibration settings
that can be overwritten by the user’s software.
One input channel measures IBAT via the voltage drop at the external shunt resistor. The second channel
measures VBAT and the temperature. By simultaneously measuring VBAT and IBAT, it is possible to dynamically
determine Rdi, which is correlated with the state of health (SOH) of the battery. By integrating IBAT, it is possible
to determine the state of charge (SOC) of the battery. These are the fundamental parameters for an intelligent
battery sensor. The necessary microcontroller and the software for determining these parameters is not part of
the ZSSC1750/51.
Figure 2.1 Functional Block Diagram
Common
Ground
Analog
Block
VBAT
Digital
Block
ZSSC1750/51 Analog Front End SBC
VDDP
WD_TIMER
IRQ_CTRL
OSC
LP_REG
VDDP_REG
VDDC_REG
SD_ADC
BG_REF
VDDE
VDDA
VDDC
SBC_PMU
GP_TIMER
SLEEPN
WDT_DIS
MCU_CLK
MCU_RSTN
IRQN
VDDA_REG
INP
DIGITAL
FILTER
CONFIG
REGISTER
RESULT
REGISTER
SHUNT
INN
PGA
MUX
VBAT
RREF
CSN
DIGITAL
FILTER
CALIBRATION
DATA PATH
SPI
SCLK
MISO
MOSI
SD_ADC
NTH
+
–
NTC
BATTERY
NTL
RXD
TXD
LIN_PHYS (1)
LIN
LIN
1) Available in ZSSC1750 only.
During the Standby Mode and the system’s Sleep Mode (e.g., engine is off), the system periodically measures
the values to monitor the discharge of the battery (see section 3.7 regarding modes). Measurement cycles are
controlled by the user’s software and are dependent on the detected events. The ZSSC1750/51 is designed for
low current consumption during Sleep Mode in the range of less than 60µA.
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ZSSC1750 / ZSSC1751 Datasheet
2.2 SBC-to-MCU Interface Pins
The ZSSC1750/51 connects to the external microcontroller (MCU) using pins shown in Figure 2.2-A.
ZSSC1750/51 pins can be classified in three categories: digital IOs, microcontroller supply pins, and the power
state indicator pin.
Figure 2.2 ZSSC1750/51 Digital IO Interface
ZSSC1750/51
VDDC
VDDC
Core and periphery
supply for extenal MCU
VDDP
VDDP
VDDP
ULP state DIS
OFF state DIS
DigIO
Digital
Input
MCU_CLK
MCU_RSTN
WDT_DIS
IRQN
OSC
20MHz
To
core
Optional MCU clock
External MCU reset:
- Power-on Reset
- Watchdog Timer
(with external disable)
Pull-down
enable
POR
&
WDT
VSSN
ZSSC1750/51 IRQ to
external MCU interrupt pin
IRQ ctrl
B) Structure of ZSSC1750/51 digital input
CSN
SCLK
VDDP
Serial Peripheral Interface
to MCU master SPI pins
SPI
MOSI
MISO
Digital Out
From
core
TXD
LIN PHY
To MCU LIN UART
RXD
VSSN
VSSN
VSSN
C) Structure of ZSSC1750/51 digital output
VDDL
PMU
ZSSC1750/51 digital ground
VSSN
SLEEPN
Power mode indicator pin
or disable signal for ext.
regulators
VSSN
A) ZSSC1750/51 external MCU interface
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ZSSC1750 / ZSSC1751 Datasheet
2.2.1 Digital I/Os
The digital I/O pins include the SPI interface pins, MCU clock, rest and interrupt pins, LIN UART pins (for
ZSSC1750 only), and watchdog timer disable pin.
All digital input pins of the ZSSC1750/51 feature a Schmitt trigger (see Figure 2.2-B), as well as configurable
pull-down resistors and protection diodes. The pull-down resistors have values specified by parameter 1.3.16.
They are enabled after power-on-reset and can be further controlled via the pullResEna register (see section
3.11.1.1).
All digital output pins of the ZSSC1750/51 have a push-pull stage and protection diodes connected as shown in
Figure 2.2-C.
All digital I/Os are supplied by the VDDP voltage, which is switched off when the ZSSC1750/51 is in the ULP or
OFF State (see section 2.3); i.e. the I/Os are also off in this state.
Note: In order to avoid parasitic supply of the digital I/O circuitry when the ZSSC1750/51 is in the ULP or OFF
State, the digital outputs of the external microcontroller should be disabled. This is valid when the external micro-
controller is not supplied by the ZSSC1750/51.
2.2.2 External Microcontroller (MCU) Supply Pins
The ZSSC1750/51 provides two separate regulators for the external microcontroller supply. The VDDP regulator
provides 3.3V, and VDDC provides 1.8V. Both voltages are switched off when the ZSSC1750/51 is in the ULP or
OFF State. For more information regarding the VDDP and VDDC regulators, including trimming options, refer to
sections 3.12.5 and 3.12.6. The current capability of the VDDP and VDDC pins is specified by parameters 1.3.11
and 1.3.13 respectively.
2.2.3 SLEEPN Power State Indicator Pin
The ZSSC1750/51 features a SLEEPN pin that indicates the power state of the ZSSC1750/51 (see section 2.3).
When the ZSSC1750/51 is in the full power (FP) state or low power (LP) state, the SLEEPN pin is HIGH; when
the state is ULP or OFF, SLEEPN is LOW. In order to remain powered in these states, the SLEEPN pin circuitry
is supplied by the VDDL regulator. When HIGH, the SLEEPN pin has a 1.8V output voltage level; the HIGH and
LOW levels are specified with parameters 1.3.20 and 1.3.21.
In the application, the SLEEPN pin can be connected to the external microcontroller (if it remains powered in
system Sleep Mode), or it can be used for disabling an external circuitry when the ZSSC1750/51 goes into one
of the power saving modes. Depending on the application specifics, an external buffer (e.g., a transistor) might
be needed for the SLEEPN pin for a proper level or current conditioning.
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2.3 System Power States
There are four different power states implemented in the ZSSC1750/51 as illustrated in Figure 2.3. Full details
are given in section 3.7.
Figure 2.3 ZSSC1750/51 Power States
FP
LP
ULP
OFF
2.3.1 Full Power State (FP)
The ZSSC1750/51 enters the Full Power (FP) State after power-on reset or after wake-up. In this power state,
the ZSSC1750/51 is fully operational and the external microcontroller is supplied and running (see section 3.7).
In the FP State, the ADCs are fully powered and running on the 4MHz base clock, which is generated from the
20MHz high-precision oscillator.
Of the four power states, the FP State consumes the most power. The MCU software can trigger the power
management unit (PMU) inside the ZSSC1750/51 to enter any other power state (see section 3.7).
2.3.2 Low Power State (LP)
The Low Power (LP) State is intended for scenarios where the ZSSC1750/51 will only perform low-power
measurements without any operation by the external microcontroller (MCU). For its ADC operations, it uses a
125kHz clock from the low-power oscillator as the base clock. The system can wake up from this power state via
any enabled interrupt of the SBC as well as via an MCU reset generated by the watchdog timer.
Note: For any SBC interrupt source that will wake up the system, the corresponding interrupt source must be
enabled in the SBC. Note that the SBC rejects the power-down command when an enabled interrupt source
inside the SBC is already active.
When the system enters the LP State from the FP State, the microcontroller software must first enable the
required interrupt sources for later wake-up in the ZSSC1750/51 SBC and the microcontroller and it must set the
pdState bit in the pwrCfgLp register (see Table 3.19) followed by a gotoPd command (see section 3.7 and
Table 3.20). A rising edge on the CSN line triggers the SBC to enter its LP State.
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When any of the enabled interrupts becomes active, the system returns to the FP State and continues the
software execution.
Note: Do not release the CSN line by software at the end of sending a power-down command to avoid the MCU
clock being stopped by the SBC at an intermediate state.
2.3.3 Ultra Low Power State (ULP)
The Ultra-Low Power (ULP) State is similar to the LP State except that the SBC also disables the power for the
external microcontroller. This power state is intended for scenarios where the SBC will only perform low-power
measurements without any operation running on the microcontroller. For the ZSSC1750/51’s ADC operations in
this state, it uses a 125kHz clock from the low-power oscillator as the base clock. The system can wake up from
this power state by any enabled interrupt of the SBC. The microcontroller is reset upon wake up by the SBC to
guarantee correct start up. This means that the microcontroller software starts again from address 0HEX after
wake up, not at the position where it was stopped.
Note: For any SBC interrupt source that will wake up the system, the corresponding interrupt source must be
enabled in the SBC. Note that the SBC rejects the power-down command when an enabled interrupt source
inside the SBC is already active.
When the system enters the ULP State from the FP State, the microcontroller software must first enable the
required interrupt sources for later wake-up in the SBC and the microcontroller and it must set the pdStatebit
in pwrCfgLpregister (see Table 3.19) followed by a gotoPd command (see section 3.7 and Table 3.20). A rising
edge on the CSN line triggers the SBC to enter its ULP State. When any of the enabled interrupts becomes
active, the system returns to FP State and restarts the microcontroller software execution.
Note: Do not release the CSN line by software at the end of sending a power-down command to avoid the
microcontroller clock being stopped by the SBC at an intermediate state.
2.3.4 OFF Power State
The OFF power state has the lowest power consumption: no measurements can be performed as all oscillators
are stopped. This power state is intended for scenarios where no measurements will be performed and the
system will consume as little power as possible. The system can wake up from this power state only by receiving
a wakeup frame over the LIN interface (only for the ZSSC1750) or after a power-on reset (for ZSSC1750/51).
The external microcontroller is reset at wake up by the SBC to guarantee correct start up. This means that the
microcontroller’s software starts again from address 0HEX after wake up, not at the position where it was stopped.
Note: For any SBC interrupt source that will wake up the system, the corresponding interrupt source, e.g. the
LIN wakeup interrupt (for the ZSSC1750 only), must be enabled inside the SBC. Note that the SBC rejects the
power-down command when an enabled interrupt source in the SBC is already active.
When the system enters the OFF power state from the FP State, the microcontroller software must first enable
the required interrupt source in the SBC, e.g. the LIN interrupt (for the ZSSC1750 only), and the microcontroller
and must set the PdState bit in register pwrCfgLp (see Table 3.19) followed by a gotoPD command (see
Table 3.20). A rising edge on the CSN line triggers the SBC to enter its OFF State. When any of the enabled
interrupts becomes active, the ZSSC1750/51 returns to the FP State and the external microprocessor can restart
its software execution.
Note: Do not release the CSN line by software at the end of sending a power-down command to avoid the MCU
clock being stopped by the SBC at an intermediate state.
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3 ZSSC1750/51 Functional Block Descriptions
3.1 Serial Peripheral Interface (SPI Slave)
The ZSSC1750/51 is fully controllable by an external microcontroller via an integrated four-wire SPI slave. It only
operates in a single mode when both the clock polarity and the clock phase are 1 (the clock is high when
inactive, data is sent on the falling SPI clock edge, and data is sampled on the rising SPI clock edge). The
accessible registers of the SBC as well as the one-time programmable (OTP) memory can be read via the SPI.
The internal status information of the SBC is also shifted-out during the address and length bytes of the
implemented SPI protocol (see Figure 3.1). Read and write burst accesses of up to 128 bytes are supported.
The SPI chip-select line CSN must be low during any transfer until the complete transfer has finished. This is
needed as the CSN input is not only used as an enable signal but also as an asynchronous reset for part of the
SPI front-end. The reason for this is to be able to set the SPI back to a defined state via the microcontroller as
well as to extract status information without needing to access any register. The CSN input can be kept low
between two transfers. The CSN input must only be driven high for execution of the “go-to-power-down”
command after the required register settings have been completed.
Note: A high level at CSN resets the internal SPI state machine.
3.1.1 SPI Protocol
The SPI slave module only operates with a clock polarity of 1 (SCLK is high when no transfer is active) and with
a clock phase of 1 (data is sent on the falling edge; data is sampled on the rising edge). For any access, the
CSN input must be low. At the end of any read access, the CSN input can be kept low. For write accesses that
change the power state, the CSN input must be driven high at the end of the write access; it can be kept low for
write accesses to other registers. During an SPI access, the CSN input must be kept low.
Important: Driving the CSN input high during a read transfer can cause a loss of data.
In each SPI transfer, 1 to 128 bytes can be read or written in one burst access. All bytes are sent and received
with the MSB first. As shown in Figure 3.1, each SPI transfer starts with two bytes sent by the master while the
slave sends back status information in parallel. The first of the two bytes sent by the master is the address byte
containing the first address to be accessed. When multiple bytes are read or written, the received SPI address is
internally incremented for each data byte. The second byte starts with the access type of the transfer (1 = write;
0 = read) followed by the 7-bit length field indicating the number of data bytes that will be read or written. The
exception is the length value of 0, which is interpreted by the slave SPI as 128 bytes.
The status information sent back by the slave during the address and length bytes starts with a fixed value of
A
HEX. This can be used to detect whether the connection is still present. The next bits sent are the slave status
word (SSW), which is 12 bits of actual status information.
The 12 SSW bits have the following definitions:
SSW[11]:
Value of the low-voltage flag
SSW[10:8]: Reset status
SSW[7]:
SSW[6]:
SSW[5]:
Watchdog active flag
Low-power oscillator trimming circuit active
Voltage/temperature ADC active
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SSW[4]:
SSW[3]:
SSW[2]:
SSW[1]:
SSW[0]:
Current ADC active
LIN short protection active (applicable for ZSSC1750 only)
LIN TXD timeout protection active (applicable for ZSSC1750 only)
Readable sleep timer value valid
OTP download procedure active
Note: After the external microcontroller has been reset, the user’s software can read the low-voltage flag and the
reset status by a single-byte transfer (important: send only the address byte) to shorten the initialization phase
(e.g., when a reset was caused by a wake-up event) without needing to read or write further bytes including the
length byte.
After the address byte and length byte are sent by the master, either the master (write transfer) or the slave
(read transfer) is transmitting data. The slave ignores all incoming bits while it is sending the requested number
of data bytes (read), and the data bytes returned during a write transfer have no meaning. Figure 3.1 shows a
read and a write burst access to the SBC.
Figure 3.1 Read and Write Burst Access to the SBC
Read Access
SCLK
CSN
MOSI
A[7:0]
R
L[6:0]
MISO
SSW[11:0]
D0[7:0]
DL-1[7:0]
Write Access
SCLK
CSN
MOSI
A[7:0]
W
L[6:0]
D0[7:0]
DL-1[7:0]
MISO
SSW[11:0]
A:
R:
W:
L:
Start address of SPI access
Read access (MSB of second byte is low)
Write access (MSB of second byte is high)
Number of data bytes (0 = 128 bytes)
SSW: Slave status word
SCLK: SPI clock
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3.2 SBC Register Map (RESULT REGISTER Block and CONFIG REGISTER Block)
Table 3.1 defines the registers in the SBC. In the “Access” column, the following abbreviations indicate the
read/write status of the registers: RC = read-clear; RO = read-only; RW = readable and writable; WO = write-
only; W1C = write-one-to-clear, RWS = read-write-set. For more details, see the subsequent sections for the
individual registers in section 3.
Important: There is a distinction between “unused” and “reserved” addresses. No problem occurs when writing
to unused addresses, but writing 0HEX to unused addresses for future expansions is recommended. Reserved
addresses must always be written with the given default value.
Table 3.1 SBC Register Map
Name
irqStat
Address
00HEX
01HEX
02HEX
03HEX
04HEX
05HEX
06HEX
07HEX
08HEX
09HEX
Order
LSB
MSB
LSB
---
Default
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
Access
RC
Short Description
Interrupt status register
RC
adcCdat
adcVdat
RO
ADC result register of a single current
measurement
RO
MSB
LSB
---
RO
RO
ADC result register of a single voltage
measurement
RO
MSB
LSB
MSB
RO
ADC result register of a single temperature
measurement by reading a voltage across the
reference resistor (external temperature
measurement only)
adcRdat
adcTdat
RO
RO
0AHEX
0BHEX
LSB
00HEX
00HEX
RO
RO
ADC result register of a single temperature
measurement by reading a voltage across the
NTC resistor (external temperature measurement)
or of a differential voltage (VPTAT – VBGH;
internal temperature measurement)
MSB
adcCaccu
adcVaccu
0CHEX
0DHEX
0EHEX
0FHEX
10HEX
11HEX
12HEX
13HEX
14HEX
15HEX
16HEX
LSB
---
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
80HEX
FFHEX
7FHEX
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Accumulator register for current measurements
---
MSB
LSB
---
Accumulator register for voltage measurements
MSB
LSB
MSB
LSB
MSB
adcCmax
adcCmin
Maximum current value measured in configured
measurement sequence
Minimum current value measured in configured
measurement sequence
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Name
adcVmax
Address
17HEX
Order
LSB
MSB
LSB
MSB
LSB
MSB
---
Default
00HEX
80HEX
FFHEX
7FHEX
00HEX
00HEX
00HEX
Access
RO
Short Description
Maximum voltage value measured in configured
measurement sequence
18HEX
RO
adcVmin
adcCrcv
adcCtcv
19HEX
RO
Minimum voltage value measured in configured
measurement sequence
1AHEX
1BHEX
1CHEX
1DHEX
RO
RO
Counter register containing the number of current
measurements
RO
RO
Counter register containing the number of current
measurements greater than or equal to the
threshold
adcVrcv
1EHEX
---
00HEX
RO
Counter register containing the number of voltage
measurements
Unused
1FHEX
20HEX
---
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
80HEX
00HEX
00HEX
00HEX
00HEX
00HEX
80HEX
00HEX
00HEX
00HEX
00HEX
80HEX
00HEX
00HEX
00HEX
00HEX
---
---
sleepTCurCnt
LSB
MSB
---
RO
RO
---
Current sleep timer value
21HEX
Unused
22HEX to 2FHEX
30HEX
---
adcCgan
LSB
---
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Digital gain correction for current channel
31HEX
32HEX
MSB
LSB
---
adcCoff
adcVgan
adcVoff
33HEX
Digital offset correction for current channel
Digital gain correction for voltage channel
Digital offset correction for voltage channel
34HEX
35HEX
MSB
LSB
---
36HEX
37HEX
38HEX
MSB
LSB
---
39HEX
3AHEX
3BHEX
3CHEX
3DHEX
3EHEX
3FHEX
40HEX
MSB
LSB
MSB
LSB
MSB
LSB
MSB
adcTgan
adcToff
adcCrcl
Digital gain correction for temperature channel
Digital offset correction for temperature channel
Number of current measurements before the
ready strobe is generated
41HEX
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Name
adcCrth
Address
42HEX
Order
LSB
MSB
---
Default
00HEX
00HEX
00HEX
Access
RW
Short Description
Absolute current value is compared to this
threshold in Current Threshold Comparator Mode
43HEX
RW
adcCtcl
44HEX
RW
Number of current measurements greater than or
equal to the threshold before the set interrupt
strobe is generated
adcVrcl
adcVth
45HEX
---
00HEX
RW
Number of voltage measurements before ready
strobe is generated
46HEX
47HEX
48HEX
49HEX
4AHEX
4BHEX
4CHEX
4DHEX
4EHEX
4FHEX
50HEX
LSB
MSB
LSB
---
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
30HEX
00HEX
10HEX
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Voltage threshold level for Threshold Comparator
(unsigned) or Accumulator (signed) Modes
adcCaccth
Accumulator threshold for current channel
---
MSB
---
adcTmax
adcTmin
adcAcmp
Upper threshold for temperature measurement
Lower threshold for temperature measurement
ADC function enable register
---
LSB
MSB
---
adcGomd
Reference voltage and sigma-delta modulator
(SDM) configuration (see section 3.8)
adcSamp
adcGain
pwrCfgFp
51HEX
52HEX
53HEX
---
---
---
00HEX
00HEX
00HEX
RW
RW
RW
Oversampling and filter configuration
Gain configuration register for analog amplifiers
Power configuration register for Full Power (FP)
State
irqEna
54HEX
55HEX
LSB
MSB
---
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
RW
RW
RW
RW
---
Interrupt enable register
adcCtrl
56HEX
ADC control register for Full Power State (FP)
adcPoCoGain
Unused
57HEX
---
Post-correction gain configuration
---
58HEX - 5EHEX
5FHEX
---
discCvtCnt
---
RW
Configuration register for some power-down
states
sleepTAdcCmp
sleepTCmp
pwrCfgLp
60HEX
61HEX
62HEX
63HEX
64HEX
LSB
MSB
LSB
MSB
---
00HEX
00HEX
00HEX
00HEX
20HEX
RW
RW
RW
RW
RW
Compare value for ADC trigger timer
Compare value for sleep timer
Power configuration register for power-down states
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Name
gotoPd
Address
65HEX
Order
---
Default
00HEX
00HEX
02HEX
00HEX
FFHEX
FFHEX
FFHEX
FFHEX
09HEX
00HEX
00HEX
00HEX
52HEX
04HEX
00HEX
00HEX
00HEX
18HEX
00HEX
08HEX
90HEX
Access
WO
---
Short Description
Power-down activation register
Unused
cmdExe
Unused
wdogCnt
66HEX to 67HEX
68HEX
---
---
---
WO/RW
---
Command execution register
---
69HEX to 6FHEX
70HEX
---
LSB
MSB
LSB
MSB
---
RO
Current watchdog counter value
71HEX
RO
wdogPresetVal
72HEX
RW
RW
RW
---
Preset value for watchdog counter
73HEX
wdogCfg
74HEX
Configuration register for watchdog counter
Unused
75HEX to 77HEX
78HEX
---
---
lpOscTrimCnt
LSB
MSB
---
RO
Result counter of low-power oscillator trim circuit
79HEX
RO
irefLpOsc
lpOscTrim
Unused
7AHEX
RW
RW
---
Trim value for low-power oscillator
7BHEX
---
Configuration register for trim circuit of LP oscillator
7CHEX to 7FHEX
80HEX
---
---
swRst
---
WO
---
Software reset
---
Unused
81HEX to AFHEX
B0HEX
---
sdmClkCfgLp
LSB
MSB
LSB
MSB
RW
RW
RW
RW
Clock configuration for SDM clock in power-down
state
B1HEX
sdmClkCfgFp
linCfg
B2HEX
Clock configuration for SDM clock in Full-Power
State (FP)
B3HEX
ZSSC1750: Configuration for LIN control logic
B4HEX
---
---
00HEX
RW/W1C
RW
ZSSC1751: Not used
Important: Must remain as default for ZSSC1751
ZSSC1750: Configuration for LIN short de-
bounce filter
linShortFilter
linShortDelay
B5HEX
0FHEX
ZSSC1751: Not used
Important: Must remain as default for ZSSC1751
ZSSC1750: Configuration for LIN short TX-RX
delay
B6HEX
---
4FHEX
RW
ZSSC1751: Not used
Important: Must remain as default for ZSSC1751
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Name
Address
Order
Default
Access
Short Description
ZSSC1750: Configuration for LIN wake-up time
linWuDelay
B7HEX
---
14HEX
RW
ZSSC1751: Not used
Important: Must remain as default for ZSSC1751
pullResEna
funcDis
B8HEX
B9HEX
BAHEX
BBHEX
---
---
FFHEX
00HEX
01HEX
03HEX
00HEX
7CHEX
10HEX
40HEX
RW
RW
RO
RO
---
Configuration register for pull-down resistors
Disable bits for dedicated functions
Version code
versionCode
LSB
MSB
---
Unused
pwrTrim
irefOsc
BCHEX
-
BFHEX
---
C0HEX
C1HEX
C2HEX
C3HEX
---
RW
RW
RW
Trim bits for voltage regulators and bandgap
Trim values for high-precision oscillator
LSB
MSB
---
ibiasLinTrim
ZSSC1750: Bias current trim register for LIN
block
10HEX
RW
ZSSC1751: Not used
Important: Must remain as default for ZSSC1751
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
adcChan
C4HEX
C5HEX
C6HEX
C7HEX
C8HEX
C9HEX
CAHEX
CBHEX
CCHEX
CDHEX
CEHEX
CFHEX
D0HEX
---
---
---
---
---
---
---
---
---
---
---
---
---
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
08HEX
00HEX
00HEX
00HEX
00HEX
00HEX
00HEX
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
---
---
---
---
---
---
---
---
---
---
---
---
Analog multiplexer configuration during test/
diagnosis
adcDiag
D1HEX
D2HEX
D3HEX
D4HEX
D5HEX
---
---
---
---
---
80HEX
00HEX
00HEX
00HEX
00HEX
RW
RW
RW
RW
RW
Enable register for test/diagnosis
currentSrcEna
Reserved
Reserved
Reserved
Enable register for current sources
---
---
---
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Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OTP
Address
D6HEX
Order
---
Default
00HEX
00HEX
00HEX
00HEX
B8HEX
00HEX
00HEX
00HEX
00HEX
00HEX
---
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
Short Description
---
---
---
---
---
---
---
---
---
---
D7HEX
---
D8HEX
---
D9HEX
---
DAHEX
---
DBHEX
---
DCHEX
---
DDHEX
---
DEHEX
---
DFHEX
---
E0HEX to FFHEX
---
OTP raw data (see section 3.10.)
3.3 ZSSC1750/51 Clock and Reset Logic
3.3.1 Clock Sources
The ZSSC1750/51 SBC contains two different oscillators, a low-power oscillator (LP oscillator) providing a clock
of 125kHz (typical) with an accuracy of ±3% and a high-precision oscillator (HP oscillator) providing a clock of
20MHz (typical) with an accuracy of ±1%. The low-power oscillator is always active except in the OFF State
while the high-precision oscillator is only active in Full-Power State (FP). The clock from the high-precision
oscillator is routed to the external microcontroller via the MCU_CLK pin.
There are three different internal clocks generated from the two clocks from the oscillators for the digital core of
the SBC:
•
Low-power clock (lpClk): This clock is directly driven by the low-power oscillator and has a frequency of
125kHz. It is used for the watchdog timer, the sleep timer, and the power management unit.
•
Divided clock (divClk): This clock is derived from the high-precision oscillator and has a frequency of
4MHz. It is used for the register file, the low-power oscillator trimming circuit, the LIN support logic
(ZSSC7150 only), and the OTP controller.
•
Multiplexed clock (muxClk): This clock is identical to the divClk in the Full-Power State (FP) and
identical to lpClk in the LP and ULP States. It is used for the ADC controller unit and the interrupt
controller.
Both oscillators are trimmed during the production test, and the trim values are stored in the OTP memory
(IREF_OSC_0, IREF_OSC_1, IREF_OSC_2, IREF_OSC_3, IREF_LP_OSC; see Table 3.67). The high
precision oscillator is routed to the MCU_CLK pin, which can be used as a clock source for the external
microcontroller or other digital devices, so it is important that the clock from the high-precision oscillator has the
correct frequency. Therefore, the two trimming values for the high-precision oscillator are protected by
redundancy inside the OTP. Software can check the validity of the trim values and the redundancy bits by
reading the OTP raw data directly from the OTP via the SPI.
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Note: The trimming values for both oscillators should also be stored by the user’s external microcontroller so that
the user’s software is able to check the validity of the trimming values. On detection of errors inside the OTP, the
user’s software can write the correct values via SPI.
3.3.2 Trimming the Low-Power Oscillator
Because the clock from the low-power oscillator is less accurate than the clock from the high-precision oscillator,
a trimming circuit is implemented that trims the low-power oscillator using the divided clock divClk. There are two
options for trimming the low-power oscillator. One option is to allow the hardware to update the trim value for the
low-power oscillator automatically so that no user interference is necessary. For this, the user only needs to set
the lpOscTrimEnaand lpOscTrimUpdbits in register lpOscTrimto 1 as well as setting the lpOscTrimCfg
field as needed (see Table 3.4). The latter configuration value defines how many low-power clock periods are
used for frequency calculation. While the trimming circuit is faster when fewer periods are used, the result of the
frequency calculation is more accurate when more periods are used. In the first part of the trimming loop, the
circuit determines the frequency of the low-power oscillator. When the measured frequency is too low, the
hardware increments the trim value by 1; if it is too high, the hardware decrements the trim value by 1.
Otherwise, the trim value remains unchanged. After changing the trim value, the hardware measures the (new)
frequency. This algorithm is only stopped when the user’s software clears the lpOscTrimEnabit (trimming logic
stops after a final update) or when any low-power state is entered.
The second option is to use the trim circuit only to measure the frequency but to update the trim value via the
user’s software. This can be preferable when the target frequency is not equal to 125kHz. For this, the user only
needs to set the lpOscTrimEna bit to 1 and set the lpOscTrimUpd bit to 0 as well as setting the
lpOscTrimCfg field as needed. Next, the user must clear the lpOscTrimEna bit without changing the other
values in the register and must wait until the hardware has finished to calculate the frequency (wait until SSW[6]
is 0). By reading the lpOscTrimCnt register, the user can calculate the actual frequency of the low-power
oscillator using the following formula:
fHP
fLP
=
⋅ 2lpOscTrimCfg+2
fHP = 4MHz
(1)
l pOscTr i mcnt + 1
After determining the actual frequency, the user can change the trim value for the low-power oscillator
lpOscTrimValas required (see Table 3.3) and re-enable the trimming circuit to check the new frequency.
Note: The trimming circuit can be kept active when going to any low-power state. The PMU interrupts the
trimming circuit on transition to the low-power state and restarts it after wakeup. This is needed as divClk is
stopped in any low-power state.
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3.3.3 Clock Trimming and Configuration Registers
3.3.3.1
Register “irefOsc” – Trim Values for the High-Precision Oscillator
Table 3.2 Register irefOsc
Name
Address
Bits
Default
Access
Description
irefTcOscTrim
[4:0] 10000BIN
RW
Trim value to minimize the temperature
coefficient of the high-precision oscillator.
Note: This value is automatically updated by the
OTP controller after an SBC reset.
C1HEX
Unused
irefOscTrim[0]
irefOscTrim[8:1]
[6:5]
[7]
[7:0]
00BIN
0BIN
40HEX
RO
RW
RW
Unused; always write as 0.
Trim value for the high-precision oscillator.
The frequency of the high-precision oscillator
increases (decreases) when this value is
incremented (decremented).
C2HEX
Note: This value is automatically updated by the
OTP controller after an SBC reset.
3.3.3.2
Register “irefLpOsc” – Trim Value for the Low-Power Oscillator
Table 3.3 Register irefLpOsc
Name
Address
Bits
Default
Access
Description
lpOscTrimVal
[6:0]
1010010BIN
RW
Trim value for the low-power oscillator. The
frequency of the low-power oscillator
increases (decreases) when this value is
incremented (decremented).
7AHEX
Note: This value is automatically updated by
the OTP controller after SBC reset.
Unused; always write as 0.
Unused
[7]
0BIN
RO
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3.3.3.3
Register “lpOscTrim” – Configuration Register for the Low-Power Oscillator Trimming Circuit
Table 3.4 Register lpOscTrim
Name
Address
Bits
Default
Access
Description
lpOscTrimEna
[0]
0BIN
RW
If set to 1, enables the low-power oscillator
trimming circuit.
Note: When the user disables the trimming
feature, the trimming logic continues its operation
until it has finished the current calculation and
then stops. The user can check that the trimming
circuit has stopped by evaluating SSW[6], which
is 0 when the trimming circuit is inactive.
Update bit for the low-power oscillator trimming
circuit. When set to 1, the trimming circuit is
allowed to update lpOscTrimVal in register
irefLpOsc. When set to 0, no hardware update
is performed.
lpOscTrimUpd
lpOscTrimCfg
[1]
0BIN
RW
RW
7BHEX
Note: Do not change while trimming circuit is
active.
This value selects the number of clock periods of
the low-power oscillator to be used to determine
the frequency.
[3:2]
01BIN
0
1
2
3
4 clock periods
8 clock periods
16 clock periods
32 clock periods
Note: Do not change while trimming circuit is
active.
Unused
[7:3] 00000BIN
RO
Unused; always write as 0.
3.3.3.4
Register “lpOscTrimCnt” – Result Counter of the Low-Power Oscillator Trimming Circuit
Table 3.5 Register lpOscTrimCnt
Name
Address
Bits
Default
Access
Description
lpOscTrimCnt[7:0]
[7:0]
00HEX
RO
Result counter of the low-power oscillator
trimming circuit. This value will only be read when
the trimming circuit is inactive (SSW[6] == 0).
78HEX
lpOscTrimCnt[10:8]
Unused
[2:0]
[7:3] 00000BIN
000BIN
RO
RO
79HEX
Unused; always write as 0
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3.3.4 Resets
The main reset source is the integrated power-on-reset circuit, which resets the complete digital core of the SBC
when VDDE drops below 3.0V (typical). There are three other reset sources that reset the complete digital core
of the SBC except the watchdog timer and its configuration registers.
These additional reset sources are
•
Watchdog reset: This reset occurs when the active watchdog timer expires without being handled by the
user’s software.
•
•
Software reset: This reset can be generated by the user by writing the value A9HEX to register swRst.
PMU error reset: This reset occurs if the power management unit (PMU) goes into an invalid state
(e.g., due to cosmic radiation).
If any of these four resets occurs, the power-on procedure is executed, which powers up the required analog
blocks and starts the download procedure for the OTP. This download procedure transfers the OTP contents into
the appropriate registers if the OTP content is valid. The MCU_RSTN pin is driven low, which can be used to
reset the connected external microcontroller. The microcontroller reset is released after the power-up procedure
has finished.
The MCU_RSTN pin is also driven low when the system goes to OFF or ULP State because the power supplies
to the microcontroller (VDDP, VDDC) are disabled in these power-down states. In this case, the MCU_RSTN low
state is released after a wake-up event has occurred and the power supplies to the external microcontroller have
stabilized.
Another possible reset source for the external microcontroller is VddpReset, which is also generated by the
power-on-reset circuit when VDDE drops below 4.05V (typical). In this case, it cannot be guaranteed that VDDP,
which is needed for correct operation of the external microcontroller, is still valid if VDDP is trimmed to the higher
level of 3.3V (see section 3.12.5).
The digital core of the SBC observes the input from the power-on-reset block and generates the MCU_RSTN
signal only when all of the following conditions are true:
•
•
•
VDDP is trimmed to 3.3V (bit vddpTrimof register pwrTrimis set to 1).
The ZSSC1750/51 system is in the Full-Power State (FP).
VDDP reset is not disabled (bit disVddpRstof register funcDisis set to 0; see Table 3.8).
3.3.4.1
The Reset Status
The external microcontroller can easily check the reason for being reset by a single-byte transfer to the SBC
(SPI address byte only) and evaluating SSW[10:8], which contains the reason for the last reset (reset status).
This value can be evaluated by the user’s software for different actions after reset:
Reset status 0: In this case, the reset was generated by the power-on-reset cell. The SBC was reset, and a
MCU_RSTN signal was generated to reset the external microcontroller.
Reset status 1: The watchdog timer was not handled and has expired (see section 3.4). The SBC logic
(except the watchdog timer and its configuration registers) was reset and a MCU_RSTN
signal was generated to reset the external microcontroller
Reset status 2: Only a MCU_RSTN signal was generated to reset the external microcontroller due to a
wakeup from the ULP or OFF State.
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Reset status 3: The user’s software has forced a reset. The SBC logic (except the watchdog timer and its
configuration registers) was reset and a MCU_RSTN signal was generated to reset the
external microcontroller.
Reset status 4: VDDP has dropped below 3.3V, and the external microcontroller was active. Only a
MCU_RSTN signal was generated to reset the external microcontroller.
Reset status 5: The PMU is in an illegal state. The SBC logic was reset (except the watchdog timer and its
configuration registers) and a MCU_RSTN signal was generated to reset the external
microcontroller.
3.3.4.2
The Low-Voltage Flag
The low-voltage flag is part of the analog block. The low-voltage flag is at low-level state after power-on-reset. It
can be set by the user’s software by writing the value ‘1’ to bit lvfSet in register cmdExe. It is cleared by the
power-on-reset cell when VDDE drops below 1.9V (typical). When VDDE drops below this threshold, it cannot be
guaranteed that the VDDL voltage is high enough to provide a reliable SBC digital supply. The low-voltage flag is
mapped to SPI SSW[11]where the user’s software can read its value.
3.3.4.3
Register “swRst” – Software Reset
Table 3.6 Register swRst
Name
Address
Bits
Default
Access
Description
swRst
80HEX
[7:0]
00HEX
WO
Writing A9HEX to this register forces a software
reset, which generates a MCU_RSTN signal to
reset the external microcontroller as well as the
SBC digital core except the watchdog timer and its
configuration registers. Always reads as 0.
3.3.4.4
Register “cmdExe” – Triggering Command Execution by Software
Table 3.7 Register cmdExe
Name
Address
Bits
Default
Access
Description
wdogClr
[0]
0BIN
RW
Writing 1 to this bit clears the watchdog timer. This
bit is cleared by hardware after the watchdog is
cleared. As long as the clear procedure is active,
any further writes to this bit are rejected.
Strobe register; write 1 to start the download
procedure from the OTP; always reads as 0.
Strobe register; write 1 to set the low-voltage flag;
always reads as 0.
otpDownload
lvfSet
[1]
[2]
1BIN
0BIN
WO
WO
RO
68HEX
Unused
[7:3] 00000BIN
Unused; always write as 0.
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3.3.4.5
Register “funcDis” – Disabling VDDP Reset and STO Output Pin
Table 3.8 Register funcDis
Name
Address
Bits
Default
Access
Description
disVddpRst
[0]
0BIN
RW
When set to 1, VddpReset does not generate a
MCU_RSTN signal to reset the external
microcontroller.
When set to 1, the output driver of the STO pin is
disabled.
B9HEX
disStoOut
Unused
[1]
0BIN
RW
RO
[7:2] 000000BIN
Unused; always write as 0.
3.4 SBC Watchdog Timer (WD_TIMER Block)
The SBC contains a configurable watchdog timer (down counter) for the ZSSC1750/51 when it is running using
the clock from the low-power oscillator. It is used to recover from an invalid software or hardware state. To avoid
a reset of the system, the watchdog must be periodically serviced. The only part of the system that will not be
reset by the watchdog reset is the watchdog itself and its configuration registers.
Figure 3.2 Structure of the Watchdog Timer
Configurable
Prescaler
1 : 1
1 : 125
1 : 1250
1 : 12500
wdogCnt (register file)
wdIrq (IRQ ctrl)
lpClk
(125 kHz)
16-Bit Down
Counter
==
0?
wdogPrescaleCfg
(register file)
set
&
&
wdogIrqFuncEna (register file)
wdRst (RstCtrl)
set
O
R
By default, the watchdog timer is active starting with a counter value of FFFFHEX and a prescaler of 125. This is
done to guarantee that the boot code of the external microcontroller has enough time to finish. During the
initialization phase of the system, the user’s software can disable, reconfigure, and restart the watchdog.
Disabling the watchdog before configuration is required as all write accesses to the register wdogPresetVal
and the register wdogCfg except the bits wdogLock and wdogEna (see Table 3.12) are blocked when the
watchdog is active. As it takes multiple low-power clock cycles until the enable signal is evaluated inside the
watchdog clock domain, the SSW[7] bit (wdActive) must be checked to determine if write accesses are
possible. To avoid any malfunction during reconfiguration, the prescaler registers are set to 0 and the counter
register is set to FFFFHEX at disable.
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When the watchdog is disabled, configuration is possible. The register wdogPresetValcontains the value that
will be copied into the down counter in the first enable cycle or when the watchdog timer is serviced via the
wdogClr bit in register cmdExe. The field wdogPrescaleCfg in register wdogCfg configures the prescaler.
The resolution and maximum timeout for the watchdog depend on the configuration as shown in Table 3.9.
Table 3.9 Resolution and Maximum Timeout for Prescaler Configurations
Prescaler Configuration
Resolution
8µs
Maximum Timeout
524 ms
wdogPrescaleCfg Setting
0
1
2
3
1:1
1:125
1ms
10ms
100ms
65.5 s
1:1250
1:12500
655.3 s
6553.5 s
As the maximum timeout value might still be too small for some applications, the user can use the wdogPmDis
bit in register wdogCfgto select whether the watchdog timer will be halted during any power-down state (bit set
to 1) or not (bit set to 0).
It is also possible to use the watchdog timer (WDT) as a wake-up source. When the wdogIrqFuncEna bit in
register wdogCfgis set to 1 and the down counter reaches 0, an interrupt is generated (instead of a reset that
would wake up the system) and the down counter reloads the preset value and continues its operation. When
the watchdog timer expires for a second time without service, the watchdog reset is generated. If the
wdogIrqFuncEnabit is set to 0, the reset is already generated when the timer expires for the first time.
After reconfiguration, the watchdog timer is re-enabled. To avoid further (accidental) changes to the watchdog
timer configuration registers, the user can set the wdogLockbit inside the register wdogCfgto 1. If this bit is set,
all write accesses are blocked. The wdogLockbit will only be cleared by a power-on reset.
The WDT can also be disabled by driving the WDT_DIS pin HIGH. In this case it is halted, but still can be
cleared via the wdogClr bit in register cmdExe (see Table 3.7). This functionality is useful in the external
microcontroller’s in-circuit programming mode to disable a reset generated by the watchdog timer.
To perform the required period servicing of the watchdog timer, the user must write the value 1 to the wdogClr
bit in register cmdExe. To avoid any malfunction if the watchdog is serviced too often, any consecutive write
accesses to the wdogClrbit are blocked until the first clear process has finished.
Important: The preset value programmed to the wdogPresetVal register must never be 0HEX as this would
immediately cause a reset forcing the system into a dead lock. It is strongly recommended that the user’s
software checks the programmed reload value before re-enabling the watchdog.
Important: The preset value must not be too small. The user must take into account critical system timings
including power-up times and flash programming/erasing times.
Note: The reconfiguration of the registers wdogPresetVal and wdogCfg, including bits wdogEna and
wdogLock,can be done in a single SPI burst write access.
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3.4.1 Watchdog Registers
3.4.1.1
Register “wdogPresetVal” – Preset Value for the Watchdog Timer
Table 3.10 Register wdogPresetVal
Important: The preset value programmed to this register must never be 0HEX (see section 3.4 above).
Name
Address
Bits
Default
Access
Description
Lower byte of the preset value of the watchdog
timer. This value is loaded into the lower byte of
the watchdog counter when the watchdog is
enabled or when the watchdog is cleared.
wdogPresetVal[7:0]
72HEX
[7:0]
FFHEX
RW
Note: This bit can only be written when the
watchdog is not locked (wdogLock== 0) and
when the watchdog is inactive (SSW[7]== 0).
Upper byte of the preset value of the watchdog
timer. This value is loaded into the upper byte of
the watchdog counter when the watchdog is
enabled or when the watchdog is cleared.
wdogPresetVal[15:8]
73HEX
[7:0]
FFHEX
RW
Note: This bit can only be written when the
watchdog is not locked (wdogLock== 0) and
when the watchdog is inactive (SSW[7] == 0).
3.4.1.2
Register “wdogCnt” – Current Value of Watchdog Timer
Table 3.11 Register wdogCnt
Name
Address
Bits
Default
Access
Description
wdogCnt[7:0]
wdogCnt[15:8]
70HEX
71HEX
[7:0]
[7:0]
00HEX
00HEX
RO
RO
Lower byte of current watchdog timer value
Upper byte of current watchdog timer value
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3.4.1.3
Register “wdogCfg” – Watchdog Timer Configuration Register
Table 3.12 Register wdogCfg
Name
Address
Bits
Default
Access
Description
wdogEna
Global enable bit for the watchdog timer.
[0]
1BIN
RW
Note: This bit can only be written when the
watchdog is not locked (wdogLock == 0).
wdogPmDis
When this bit is set to 1, PMU stops the watchdog
during any power-down state.
[1]
[2]
0BIN
RW
RW
Note: This bit can only be written when the
watchdog is not locked (wdogLock== 0).
wdogIrqFuncEna
When this bit is set to 1, the watchdog reloads the
preset value when expiring for the first time and
generates an interrupt instead of a reset. A reset
will always be generated when the watchdog timer
expires for the second time.
0BIN
Note: This bit can only be written when the
watchdog is not locked (wdogLock== 0) and when
the watchdog is inactive (SSW[7] == 0)
74HEX
wdogPrescaleCfg
Prescaler configuration:
0
1
2
3
No prescaler active
Prescaler of 125 is active
Prescaler of 1250 is active
Prescaler of 12500 is active
[4:3]
01BIN
RW
Note: This bit can only be written when the watch-
dog is not locked (wdogLock== 0) and when the
watchdog is inactive (SSW[7] == 0)
Unused
[6:5]
7
00BIN
RO
Unused; always write as 0.
wdogLock
When this bit is set to 1, all write accesses to the
other bits of this register as well as to the
wdogPresetValregisters are ignored. This bit can
only be written to 1 and is only cleared by a power-
on reset.
0BIN
RWS
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3.5 SBC Sleep Timer (GP_TIMER Block)
The integrated sleep timer (up counter) in the GP_TIMER (general-purpose timer) block is only active when the
system is in any low-power state and it is running with the 125kHz clock from the low-power oscillator.
The sleep timer consists of three blocks:
•
•
•
A fixed prescaler that divides the incoming 125kHz clock from the low-power oscillator by 12500 to get a
timer resolution of 10 Hz.
A 16-bit counter that generates an interrupt (signal: stlrq) when the timer reaches the programmed
compare value in the sleepTCmpregister (see Table 3.14).
A 12-bit counter that triggers the PMU (with signal stAdcTrigger) when the timer reaches the programmed
compare value in the sleepTAdcCmpregister (see Table 3.13) to power-up the ADC blocks and to
perform measurements if one of the discrete measurement scenarios are configured.
Figure 3.3 Structure of the Sleep Timer
sleepTCmp (register file)
stIrq (IRQ ctrl)
sleepTCurCnt (register file)
stAdcTrigger (PMU)
16-Bit
Counter
==
?
lpClk
(125 kHz)
Prescaler
1 : 12500
cntClk
(10 Hz)
12-Bit
Counter
==
?
sleepTAdcCmp (register file)
When the system goes from the Full-Power (FP) State to any power-down state on request by the user, the
prescaler and both counters are cleared and the 16-bit counter is enabled. Every 100ms, triggered by the pre-
scaler, the 16-bit counter is incremented until it reaches the programmed compare value sleepTCmp. When the
compare value is reached, the timer stops and the interrupt controller is triggered to set the corresponding status
flag (see section 3.6.1.1). The sleep timer is also stopped when the system returns to the FP State. The user can
determine the sleep duration by reading the register sleepTCurCnt, which returns the value of the 16-bit
counter (see Table 3.15).
Note: Although the timer stops and the interrupt status bit is set when the compare value is reached, the system
remains in the power-down state if the corresponding interrupt is not enabled to drive the interrupt line IRQN (bit
1 in the irqEna register; see Table 3.17).
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Equation (2) can be used to determine the correct sleep time to be programmed. The sleep timer expires after
100ms for a compare value of 0, after 200ms for a compare value of 1, and so on.
Sleep Time = 100ms ∗
(
sl eepTCmp + 1
)
(2)
The 12-bit counter that triggers the PMU is only enabled during any power-down state when any discrete
measurement scenario is configured. In this case, the counter is incremented each 100ms triggered by the
prescaler. When the counter reaches the programmed compare value sleepTAdcCmp, a strobe for the PMU is
generated and the 12-bit counter is reset to 0. Then it continues its operation. This counter is only stopped when
the system returns to the FP State, but it continues to operate when the sleep timer has expired if it was not
enabled to wake up the system.
Equation (3) can be used to determine the correct ADC trigger time to be programmed. The ADC trigger timer
expires after 100ms for a compare value of 0, after 200ms for a compare value of 1, and so on.
In general
ADC Trigger Time =100ms ∗
(
sl eepTAdcCmp + 1
)
(3)
Important: When both the sleep timer for wake-up and the ADC trigger timer for discrete measurements are
used, special care must be taken when programming the compare values because when the sleep timer expires,
the wake-up condition has higher priority over an active ADC measurement or an ADC trigger strobe.
3.5.1 Sleep Timer Registers
3.5.1.1
Register “sleepTAdcCmp” – Compare Value for ADC Trigger Timer
Table 3.13 Register sleepTAdcCmp
Name
Addr
Bits
Default
Access
Description
Lower byte of compare value for the ADC trigger
timer; the ADC trigger timer is only active if the
system is in LP or ULP State and any discrete
measurement scenario is configured generating
periodic strobes for the PMU.
sleepTAdcCmp[7:0]
60HEX [7:0]
00HEX
RW
ADC trigger time = 100 ms (sleepTAdcCmp+ 1)
Upper byte of compare value for ADC trigger timer;
ADC trigger timer is only active when the system is
in LP or ULP State and any discrete measurement
scenario is configured generating periodic strobes
for the PMU.
sleepTAdcCmp[15:8] 61HEX [7:0]
00HEX
RW
ADC trigger time = 100 ms (sleepTAdcCmp+ 1)
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3.5.1.2
Register “sleepTCmp” – Compare Value for Sleep Timer
Table 3.14 Register sleepTCmp
Name
Addr
Bits
Default
Access
Description
sleepTCmp[7:0]
62HEX [7:0]
00HEX
RW
Lower byte of compare value for sleep timer; sleep
timer is only active if the system is in LP or ULP
State.
Sleep time = 100 ms (sleepTCmp + 1)
Upper byte of compare value for sleep timer; sleep
timer is only active when the system is in LP or ULP
State.
sleepTCmp[15:8]
63HEX [7:0]
00HEX
RW
Sleep time = 100 ms (sleepTCmp+ 1)
3.5.1.3
Register “sleepTCurCnt” – Current Value of Sleep Timer
Table 3.15 Register sleepTCurCnt
Name
Addr
Bits
Default
Access
Description
sleepTCurCnt[7:0]
20HEX [7:0]
00HEX
RO
Lower byte of the current sleep timer value. Since the
timer is stopped in FP State, the duration of the last
power-down state can be determined:
Sleep time = 100ms (sleepTCurCnt+ 1)
Note: Value is only valid when SSW[1](sleep timer
valid stValid) is set.
sleepTCurCnt[15:8] 21HEX [7:0]
00HEX
RO
Upper byte of the current sleep timer value. Since the
timer is stopped in FP State, the duration of the last
power-down state can be determined:
Sleep time = 100ms (sleepTCurCnt + 1)
Note: Value is only valid when SSW[1](stValid) is
set.
3.6 SBC Interrupt Controller (IRQ_CTRL Block)
There are 16 different interrupt sources in the SBC system, each having a dedicated interrupt status bit in the
irqStat register (see Table 3.16) and a dedicated interrupt enable bit in the irqEna register (see Table
3.17). The interrupt controller captures each interrupt source in the interrupt status register independently of the
interrupt enable settings. The interrupt controller combines all enabled interrupt status bits into the low-active
interrupt signal that is used to drive the interrupt pin IRQN of the SBC and to wake up the system by the PMU.
This means that interrupt status bits, which can always be set even when disabled, can only generate a wake-up
event and drive the interrupt pin IRQN when they are enabled.
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Figure 3.4 Generation of Interrupt and Wake-up
irqStat[0]
&
irqEna[0]
.
.
.
IRQN
O
R
irqStat[15]
wake-up
(to PMU)
&
irqEna[15]
The user can determine the interrupt reason by reading the interrupt status register irqStat. The interrupt
status register is cleared on each read access. Therefore the user’s software must ensure that it stores the read
interrupt status value if needed to avoid loss of information.
3.6.1.1
Interrupt Sources
The bit mapping is the same for the interrupt enable register irqEna (see Table 3.17) and the interrupt status
register irqStat (see Table 3.16):
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Watchdog Timer Interrupt; status is set by the watchdog timer when the interrupt functionality of
the watchdog timer is enabled and the watchdog timer expires for the first time.
Sleep Timer Interrupt; status is set by the sleep timer when the sleep timer reaches the
programmed compare value.
LIN TXD Timeout Interrupt (for ZSSC1750 only); status is set by the LIN support logic when the
TXD input from the external microcontroller is low for more than 10.24ms.
LIN Short Interrupt (for ZSSC1750 only); status is set by the LIN support logic when a short is
detected in the LIN PHY.
LIN Wakeup Interrupt (for ZSSC1750 only); status is set by the LIN support logic when a wake-up
frame is detected on the LIN bus.
Current Conversion Result Ready Interrupt; status is set by the ADC unit when a single current
measurement (register adcCrcl== 0) or multiple current measurements defined by adcCrcl
(register adcCrcl≠ 0) have been completed and the result is available.
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Bit 6:
Voltage Conversion Result Ready Interrupt; status is set by the ADC unit when a single voltage
measurement (register adcVrcl== 0) or multiple voltage measurements defined by the adcVrcl
(register adcVrcl≠ 0) have been completed and the result is available.
Bit 7:
Bit 8:
Temperature Conversion Result Ready Interrupt; status is set by the ADC unit when a single
temperature measurement has been completed and the result is available.
Current Comparator Interrupt; status is set by the ADC unit when the Current Threshold Counter
Mode is enabled (register adcAcmp[2:1]≠ 00) and the absolute value of multiple current
measurements (defined by register adcCtcl) exceeds the programmed current threshold (register
adcCrth).
Note: If the threshold counter mode is enabled but adcCtclis 0, this bit is always set indepen-
dently of the threshold.
Bit 9:
Voltage Comparator Interrupt; status is set by the ADC unit if the VThWuEnabit (adcAcmp[8]) is
set to 1 and a single measured voltage or the accumulated voltage measurements (depends on
configured mode) drop below the programmed (register adcVTh) voltage threshold.
Bit 10: Temperature Threshold Interrupt; status is set by the ADC unit when the TWuEnabit
(adcAcmp[10]) is set to 1 and a temperature measurement is outside the specified temperature
interval defined by registers adcTminand adcTmax.
Bit 11: Current Accumulator Threshold Interrupt; status is set by the ADC unit when the CAccuThEna
bit (adcAcmp[3]) is set to 1 and the accumulated current values rise above the programmed
threshold value (register adcCaccTh) for a positive threshold value or fall below the programmed
threshold value for the negative threshold value.
Bit 12: Current Overflow Interrupt; status is set by the ADC unit when the COvrEnabit (adcAcmp[4]) is
set to 1 and the compensated value of a current measurement is outside of the representable
range.
Bit 13: Voltage/Temperature Overflow Interrupt; status is set by the ADC unit when the VTOvrEnabit
(adcAcmp[5]) is set to 1 and the compensated value of a voltage or temperature measurement is
outside of the representable range.
Bit 14: Current Over-Range Interrupt; status is set by the ADC unit when the COvrEnabit
(adcAcmp[4]) is set to 1 and the input from the current ADC is overdriven.
Bit 15: Voltage/Temperature Over-Range Interrupt; status is set by the ADC unit when the VTOvrEna
bit (adcAcmp[5]) is set to 1 and the input from the voltage/temperature ADC is overdriven.
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3.6.1.2
Register “irqStat” – Interrupt Status Register
Table 3.16 Register irqStat
Name
Address
Bits
Default
Access
Description
irqStat[7:0]
00HEX
[7:0]
00HEX
RC
Lower byte of the interrupt status register as
defined in section 3.6.1.1; each bit is set by
hardware and cleared on read access.
Upper byte of interrupt status register as defined
in section 3.6.1.1; each bit is set by hardware and
cleared on read access.
irqStat[15:8]
01HEX
[7:0]
00HEX
RC
Note: To avoid loss of information, the hardware set condition has a higher priority than the read clear condition.
3.6.1.3
Register “irqEna” – Interrupt Enable Register
Table 3.17 Register irqEna
Name
Address
Bits
Default
Access
Description
irqEna[7:0]
54HEX
[7:0]
00HEX
RW
Lower byte of the interrupt enable register as
defined in section 3.6.1.1; only enabled interrupts
can drive the interrupt line and wake up the
system; the bit mapping is the same as for the
interrupt status register.
irqEna[15:8]
55HEX
[7:0]
00HEX
RW
Upper byte of the interrupt enable register as
defined in section 3.6.1.1; only enabled interrupts
can drive the interrupt line and wake up the
system; the bit mapping is the same as for the
interrupt status register.
Note: The interrupt enable bit for the LIN wake-up interrupt (irqEna[4]) is also used as the enable for the LIN
wake-up (for ZSSC1750 only) frame detector within the PMU.
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3.7 SBC Power Management Unit (SBC_PMU Block)
The power management unit (PMU) controls placing the SBC into the selected power down state, controlling the
power down signals for the different analog blocks, and controlling the clocks for the digital logic. It also controls
the other digital modules during the power-down state.
The system provides four different power states:
FP (Full-Power State)
In this state, all blocks are powered except the ADCs if the user’s software has
not enabled them. All internal clocks are active (divClk and muxClk are 4MHz)
and the external microcontroller is also powered and clocked through pins
VDDP, VDDC, and MCU_CLK. When powered and enabled by software, the
ADC clocks are generated from the clock from the high-precision oscillator.
LP (Low-Power State)
In this state, the high-precision oscillator and the LIN transmitter (ZSSC1750
only) are powered down. The clock for the external microcontroller (MCU_CLK)
is stopped, but the microcontroller remains powered through VDDP and/or
VDDC. Depending on the selected measurement scenario, the ADCs are also
powered down during times of inactivity. Otherwise the ADC clocks are
generated from the low-power oscillator.
ULP (Ultra-Low-Power State) In this state, the high-precision oscillator and the LIN transmitter (ZSSC1750
only) are powered down. The optional external microcontroller clock MCU_CLK
is stopped and the supply voltages for the external microcontroller (VDDP,
VDDC) are powered down. Depending on the selected measurement scenario,
the ADCs are also powered down during times of inactivity. Otherwise, the
ADC clocks are generated from the clock from the low-power oscillator.
OFF (Off State)
In this state, all analog blocks except the digital power supply for the SBC and
the RX part of the LIN PHY (ZSSC1750 only) are powered down. The external
microcontroller clock MCU_CLK is stopped, and the supply voltages for the
external microcontroller (VDDP, VDDC) are powered down.
For the ZSSC1750/51 to enter any of the power-down states (LP, ULP, or OFF), the user’s software must first
set the pdState field of register pwrCfgLp to select the state (see Table 3.19) and enable the interrupts
needed as the wakeup source before writing A9HEX to register gotoPd(see Table 3.20). Immediately after A9HEX
is written to the gotoPdregister, the CSN line must be driven high. Although for all other register accesses, the
CSN line can be kept low and the next SPI transfer can follow immediately, it is mandatory to drive CSN high for
the power-down command. Otherwise, the PMU remains in the FP State.
Important: If no interrupt is enabled, the system can only be awakened by power-on-reset!
Note: The CSN line must be driven high to go to power-down after writing the value A9HEX to register gotoPd.
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The following tasks are always performed on transition to any power-down state by the PMU:
•
•
Both ADCs are stopped. Any active measurement is interrupted. ADC control is transferred to the PMU.
Those configuration values that can be configured independently for the Full-Power State and power-down
states are switched to the power-down settings.
•
•
•
•
•
The sleep timer is cleared and enabled.
The clock on the MCU_CLK pin is stopped.
The high-precision oscillator is powered down.
The TX part of the LIN PHY is powered down (ZSSC1750 only).
The source for the muxClk changes from divClk to lpClk.
If any of the enabled interrupts occurs and the interrupt pin IRQN is driven low, the system wakes up
immediately; any ADC measurement that is active during the power-down state is stopped. All mandatory blocks
are powered up, and the system waits for stabilization before re-enabling the clock output MCU_CLK for the
external microcontroller.
If any of the enabled interrupts is already active on reception of the power-down command or becomes active on
transition to the requested power-down state, the system rejects the power-down command or re-enables those
blocks that are already powered down. Depending on the time when the power-down procedure was interrupted,
it is possible that the sleep timer was not cleared. In this case, the sleep timer valid flag is cleared, signaling that
the sleep timer value in register sleepTCurCntis not valid. This flag is mapped to SSW[1].
3.7.1 FP State
After the initial power-on reset when the OTP contents are downloaded into the registers and all blocks have
stabilized, the system enters the FP State. In this state, all voltage regulators, both oscillators and the LIN PHY
(ZSSC1750 only) are powered but the ADCs are still powered down.
Important: Both ADCs are powered down after power-on reset.
To be able to use the ADCs, the user must first power up the required ADCs by programming register
pwrCfgFp, bits pwrAdcI and/or pwrAdcV (see Table 3.18). The first bit enables the current ADC and the
second bit enables the voltage/temperature ADC. In this register are three other bits that can be set by the user,
but they should be handled with care as the system consumes less power when any of these bits is set but the
accuracy of the measurement results is reduced:
•
•
•
lpEnaFp
ulpEnaFp
if set to 1, the bias current for analog blocks is reduced to 10%
if set to 1, the bias current for analog blocks is reduced to 5%
pdRefbufOcFp if set to 1, the offset cancellation circuit inside the reference buffer is powered down
Note: If both lpEnaFpand ulpEnaFPare set to 1, the bias current for analog blocks is reduced to 15%.
Important: These settings are only used in FP State. For configuration for the power-down states, the
pwrCfgLpregister must be used.
The settings in register pwrCfgFpare preserved when entering any power-down state by executing the power-
down command. The PMU overrides these settings or switches to the settings made in register pwrCfgLp on
transition to the power-down state. When the system wakes up and returns to the FP State, the PMU restores
the settings as configured in pwrCfgFp regardless of whether any ADC was powered in power-down state or
not.
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3.7.2 LP and ULP States
The LP and ULP power-down states are used to save power while doing measurements with lower accuracy. In
both states, the TX part of the LIN PHY and the high-precision oscillator are powered down and the external
microcontroller clock is stopped. The internal clock muxClk is driven by the low-power oscillator with a frequency
of 125kHz while the internal clock divClk is stopped. In ULP State, the two voltage regulators VDDP (IO voltage
for SBC and external microcontroller) and VDDC (optional core voltage for external microcontroller) are powered
down. In this case, the SLEEPN pin is driven low to indicate this state. The state of the ADCs and the other
analog blocks needed for measurements depends on the configured measurement setup for the power-down
state (see following subsections). The blocks are powered when they are needed for measurement and powered
down when they are not needed for measurement. This is controlled by the PMU as well as the control signals
(start, stop, mode) for the digital ADC unit.
The main configuration register for the power-down behavior is register pwrCfgLp (see Table 3.19). The field
pdStateis used to select the power-down state to be entered on reception of the power-down command, and
the field pdMeasis used to define the measurement setup to be used during the power-down state.
There are three other bits to configure the power-down behavior:
•
•
•
lpEnaLpif set to 1, the bias current for analog blocks is reduced to 10%
ulpEnaLp if set to 1, the bias current for analog blocks is reduced to 5%
pwrRefbufOcLpif set to 1, the offset cancellation circuit in the reference buffer is powered up
Note: If both lpEnaLpand ulpEnaLpare set to 1, the bias current for analog blocks is reduced to 15%.
For the corresponding bits for the FP State, lpEnaFpand ulpEnaFpin register pwrCfgFp(see Table 3.18), the
meaning is the same, but the default settings are different. While there is no bias current reduction during FP
State (default setting for both bits is 0), the default bias current for the LP and ULP States is reduced to 10%.
The meaning of the control bit for the offset cancellation differs: the FP State control bit is a power-down signal;
the LP/ULP State control bit is a power-up bit. While the offset cancellation is enabled by default during the FP
State (pdRefbufOcFp == 0), the offset cancellation is disabled by default during the LP or ULP State
(pdRefbufOcLp== 0). Both bits are configurable by the user.
On transition to the LP or ULP State, the sleep timer and the ADC trigger timer are cleared. While the sleep timer
is always enabled during power-down states, the ADC trigger timer is only enabled when performing discrete
measurements. If the sleep timer interrupt is enabled, the system wakes up when the sleep timer expires. If the
sleep timer interrupt is not enabled, the sleep timer stops when it expires, but the ADC trigger timer, if enabled
due to the measurement configuration, continues its operation. For wake-up, other interrupts must be enabled;
e.g., LIN wakeup (for ZSSC1750 only).
Note: The sleep timer is always active during the LP and ULP States.
Note: When reading the sleep timer value after wake-up by another enabled interrupt, the sleep timer is only
valid when it has not reached its compare value although the valid flag says valid. Whether the sleep timer is
valid can be determined by the sleep timer status bit.
When the system wakes up and returns to FP State, the sleep timer is stopped. The user’s software can read the
sleep timer value to determine the duration of the power-down state.
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3.7.2.1
Performing No Measurements during LP/ULP State
When the LP or ULP State has been entered, all analog blocks related to ADCs are powered down. If the system
goes to power down without performing any measurements, only three different wake-up sources are possible:
the watchdog timer interrupt, the sleep timer interrupt, and the LIN wakeup interrupt (for ZSSC1750 only).
Important: At least one of these interrupts must be enabled, as otherwise the system can only wake up via
power-on reset. If no interrupt is enabled, the system cannot wake up.
To go to LP or ULP State without performing measurements, the following tasks must be done:
•
Enable at least one of the following interrupts:
. Set irqEna[0]to 1 to enable the watchdog interrupt to wake up the system.
. Set irqEna[1]to 1 to enable the sleep timer to wake up the system.
. Set irqEna[4]to 1 to enable the LIN wake-up detector and to enable the system to wake up due to a
LIN wakeup frame (for ZSSC1750 only).
•
•
Set up the sleep timer compare value (register sleepTCmp) if needed.
Configure the pwrCfgLpregister as follows:
. Set pdStateto 0 or 1 to configure the LP State or to 2 to configure the ULP State.
. Set pdMeasto 0 to configure the system to perform no measurements.
. Set lpEnaLp, ulpEnaLpand pwrRefbufOcLp as needed.
Write A9HEX to register gotoPdand then drive the CSN line high.
•
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFpare restored.
When all blocks have stabilized, the external microcontroller clock MCU_CLK is re-enabled, and if coming out of
the ULP State, the microcontroller reset MCU_RST is released.
Figure 3.5 LP/ULP State without any Measurements
Note: the sleep timer is used as the wake-up source in this example, but it could also be the watchdog timer
interrupt or the LIN wakeup interrupt.
I
gotoPd
Command
Wakeup
Due to
Sleep
Timer
Interrupt
t
FP
LP / ULP
FP
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3.7.2.2
Performing Discrete Measurements of Current during LP/ULP State
The system can be configured to periodically enable the current ADC and to measure the current during the LP
or ULP State. The current ADC can be configured to perform several current measurements during each
measurement phase (green boxes in Figure 3.6).
Upon entering the LP/ULP State and between the measurements, the current ADC is powered down. The
voltage/temperature ADC is powered down for the entire power-down period. The PMU powers up the current
ADC when triggered by the ADC trigger timer. Possible wake-up sources during this scenario are the watchdog
timer interrupt, the sleep timer interrupt, the LIN wakeup interrupt (for ZSSC1750 only), or any of the ADC
interrupts related to current.
Important: When no interrupt is enabled, the system cannot wake up.
To go to LP or ULP State and perform discrete current measurements, the following tasks must be done:
•
Enable at least one of the following interrupts:
. Set irqEna[0]to 1 to enable the watchdog interrupt to wake up the system.
. Set irqEna[1]to 1 to enable the sleep timer to wake up the system.
. Set irqEna[4]to 1 to enable the LIN wake-up detector and to enable the system to wake up due to a
LIN wakeup frame (for ZSSC1750 only).
. Enable any ADC interrupt related to current (see section 3.6.1.1).
Set up the sleep timer compare value (register sleepTCmp) if needed.
Set up the ADC trigger timer compare value (register sleepTAdcCmp) as needed.
Configure the pwrCfgLp register as follows:
•
•
•
. Set pdStateto 0 or 1 to configure LP State or to 2 to configure ULP State.
. Set pdMeasto 1 to configure the system to perform discrete current measurements.
. Set lpEnaLp, ulpEnaLpand pwrRefbufOcLpas needed.
•
Write A9HEX to register gotoPdand then drive the CSN line high.
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFpare restored.
When all blocks have stabilized, the external microcontroller clock is re-enabled and, if coming out of ULP State,
the microcontroller reset is released.
Important: If any measurement is active while an enabled interrupt occurs (e.g., the sleep timer expires), the
measurement is interrupted and the system returns to FP State.
In the example shown in Figure 3.6, the first wakeup is by the ADC and the second wake-up is by the sleep
timer; however, the wakeups could be other combinations of the watchdog timer interrupt, sleep timer interrupt,
and/or LIN wakeup interrupt (ZSSC1750 only).
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Figure 3.6 LP/ULP State Performing Only Current Measurements
I
gotoPd
gotoPd
Command
Command
ADC
Trigger
Time
Wakeup
Due to
Sleep
Current
Wakeup
Current Only
Measurements
Timer
Interrupt
t
FP
LP / ULP
FP
LP / ULP
FP
3.7.2.3
Performing Discrete Measurements of Current, Voltage, and Internal Temperature during
LP/ULP State
During the LP or ULP State, the system can be configured to periodically enable both ADCs and measure
current, voltage, and internal or external temperature (see section 3.7.2.4 for external temperature). The
sequence can be selected in the pdMeas bit field [4:2] in register pwrCfgLp, which also selects whether
internal or external temperature is measured. The period between each measurement is determined by the ADC
trigger timer (sleepTAdcCmp).
The current ADC can be configured to perform multiple current measurements during each measurement
window (green and orange boxes in Figure 3.7 to Figure 3.9) while the voltage/temperature ADC can be
configured to perform multiple voltage or internal temperature measurements (orange boxes in Figure 3.7 to
Figure 3.9). After performing the configured number of voltage measurements, the PMU changes the
configuration for the voltage/temperature ADC and performs a single measurement of the internal temperature.
Voltage and temperature are not measured in each sample period if the ADCs are configured for measuring only
current in a specified number of initial loops. The user can configure register discCvtCnt(see Table 3.21) so
that in the first discCvtCntsamples, only current is measured before voltage and temperature are measured in
the next sample.
Upon entering the LP/ULP State and between the measurements, both ADCs are powered down. The PMU
powers up the current ADC when triggered by the ADC trigger timer. The voltage/temperature ADC is only
powered up after discCvtCntcurrent-only measurements have been performed. Possible wake-up sources in
this setup are all interrupts except LIN short and LIN TXD timeout interrupts (ZSSC1750 only).
Important: When no interrupt is enabled, the system cannot wake up.
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To go to the LP or ULP State and perform measurements of discrete current, voltage, and internal temperature,
the following tasks must be done:
•
Enable at least one of the following interrupts:
. Set irqEna[0] to 1 to enable the watchdog interrupt to wake up the system.
. Set irqEna[1] to 1 to enable the sleep timer to wake up the system.
. Set irqEna[4]to 1 to enable LIN wake-up detector and to enable the system to wake up due to a LIN
wakeup frame (for ZSSC1750).
. Enable any ADC interrupt (see section 3.6.1.1).
•
•
•
Configure the sleep timer compare value (register sleepTCmp) if needed.
Set up the ADC trigger timer compare value (register sleepTAdcCmp) as needed.
Configure the pwrCfgLpregister as follows:
. Set pdStateto 0 or 1 to configure the LP State or to 2 to configure the ULP State.
. Set pdMeasto 2 to configure the system to perform discrete current, voltage, and internal temperature
measurements.
. Set lpEnaLp, ulpEnaLpand pwrRefbufOcLpas needed.
•
•
Set discCvtCntas needed. This register defines the number of current-only measurement loops before
performing measurements of all three parameters.
Write A9HEX to register gotoPdand then drive the CSN line high.
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFpare restored.
When all blocks have stabilized, the external microcontroller clock is re-enabled and if coming out of the ULP
State, the microcontroller reset is released.
Important: If any measurement is active while an enabled interrupt occurs (e.g., the sleep timer expires) the
measurement is interrupted and the system returns to the FP State.
Note: If register discCvtCntis set to 0, voltage and temperature are measured in each loop (default setting).
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Figure 3.7 LP/ULP State Performing Current, Voltage, and Temperature Measurements
with discCvtCnt== 2
I
gotoPd
Command
ADC
Trigger
Time
Wakeup
Due to
Sleep
Timer
Interrupt
t
FP
LP / ULP
FP
Current measurement only
Measurement of current, voltage and temperature
Figure 3.8 LP/ULP State Performing Current, Voltage, and Temperature Measurements
with discCvtCnt== 5
I
gotoPd
Command
Wakeup due
to Voltage,
Temperature
or Current
ADC
Trigger
Time
ADC Interrupt
t
FP
LP / ULP
FP
Current measurement only
Measurement of current, voltage, and temperature
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Figure 3.9 LP/ULP State Performing Current, Voltage, and Temperature Measurements
with discCvtCnt== 1
I
gotoPd
ADC
Trigger
Time
Command
Wakeup
Due to
Current
ADC
Interrupt
t
FP
LP / ULP
FP
Current measurement only
Measurement of current, voltage and temperature
3.7.2.4
Performing Discrete Measurements of Current, Voltage, and External Temperature during
LP/ULP State
During the LP or ULP State, the system can be configured to periodically enable both ADCs and measure
current, voltage, and external temperature. This setup is the same as the configuration described in the previous
section, except that the external instead of the internal temperature is measured. To use this option, pdMeas
must be set to 3.
3.7.2.5
Performing Continuous Measurements of Current during LP/ULP State
The system can be configured to perform continuous current measurements during the LP or ULP State. While
the current ADC is powered up during the entire power-down state, the voltage/temperature ADC is powered
down.
The current ADC is powered up on entering the LP/ULP State if it was not already powered up during the FP
State. The ADC trigger timer is not enabled as the measurement is continuous. Possible wake-up sources during
this scenario are the watchdog timer interrupt, the sleep timer interrupt, the LIN wakeup interrupt (for ZSSC1750
only), or any of the ADC interrupts related to current.
Important: If no interrupt is enabled, the system cannot wake up.
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To go to the LP or ULP State with continuous current measurements, the following tasks must be done:
•
Enable at least one of the following interrupts:
. Set irqEna[0]to 1 to enable the watchdog interrupt to wake up the system.
. Set irqEna[1]to 1 to enable the sleep timer to wake up the system.
. Set irqEna[4]to 1 to enable the LIN wake-up detector and to enable the system to wake up due to a
LIN wakeup frame (for ZSSC1750 only).
. Enable any ADC interrupt related to current (see section 3.6.1.1).
Setup the sleep timer compare value (register sleepTCmp) if needed.
Configure the pwrCfgLpregister as follows:
•
•
. Set pdStateto 0 or 1 to configure LP State or to 2 to configure ULP State.
. Set pdMeasto 4 to configure the system to perform continuous current measurements.
. Set lpEnaLp, ulpEnaLp, and pwrRefbufOcLpas needed.
Write A9HEX to register gotoPdand then drive the CSN line high.
•
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFpare restored.
When all blocks have stabilized, the external microcontroller clock is re-enabled and if coming out of ULP State,
the microcontroller reset is released.
Important: If any measurement is active while an enabled interrupt occurs (e.g., the sleep timer expires), the
measurement is interrupted and the system returns to FP State.
Figure 3.10 LP/ULP State Performing Continuous Current-Only Measurements
Note: The sleep timer interrupt or an ADC interrupt related to current is used as the wake-up source in this
example, but it could also be the watchdog timer interrupt or the LIN wakeup interrupt (ZSSC1750 only).
I
gotoPd
Command
Wakeup Due to
Sleep Timer or
Current ADC
Current measurement only
Interrupt
t
FP
LP / ULP
FP
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3.7.2.6
Performing Continuous Current and Voltage Measurements during LP/ULP State
The system can be configured to perform continuous current and voltage measurements during the LP or ULP
State. Both ADCs are powered up during the entire power-down state. The ADCs are powered up on entering
the LP/ULP State if they were not already powered up during the FP State. The ADC trigger timer is not enabled
as the measurement is continuous. Possible wake-up sources during this scenario are the watchdog timer
interrupt, the sleep timer interrupt, the LIN wakeup interrupt (for ZSSC1750 only), or any of the ADC interrupts
related to current or voltage.
Important: If no interrupt is enabled, the system cannot wake up.
To go to LP or ULP State and perform continuous current and voltage measurements, follow these steps:
•
Enable at least one of the following interrupts:
. Set irqEna[0]to 1 to enable the watchdog interrupt to wake up the system.
. Set irqEna[1]to 1 to enable the sleep timer to wake up the system.
. Set irqEna[4]to 1 to enable the LIN wake-up detector and to enable the system to wake up due to a
LIN wakeup frame (for ZSSC1750 only).
. Enable any ADC interrupt related to current.
•
•
Set up the sleep timer compare value (register sleepTCmp) if needed.
Configure the pwrCfgLpregister as follows:
. Set pdStateto 0 or 1 to configure the LP State or to 2 to configure the ULP State.
. Set pdMeasto 5 to configure the system to perform continuous current and voltage measurements.
. Set lpEnaLp, ulpEnaLp, and pwrRefbufOcLpas needed.
Write A9HEX to register gotoPdand then drive the CSN line high.
•
When an enabled interrupt occurs, the system wakes up and the settings from register pwrCfgFpare restored.
When all blocks have stabilized, the external microcontroller clock MCU_CLK is re-enabled and if coming out of
ULP State, the microcontroller reset MCU_RST is released.
Important: If any measurement is active while an enabled interrupt occurs (e.g., the sleep timer expires), the
measurement is interrupted and the system returns to the FP State.
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Figure 3.11 Performing Continuous Current and Voltage Measurements during LP/ULP State
Note: The sleep timer interrupt or an ADC interrupt related to voltage or current is used as the wake-up source in
this example, but it could also be the watchdog timer interrupt or the LIN wakeup interrupt (for ZSSC1750 only).
I
gotoPd
Command
Wakeup Due
to Sleep Timer,
Voltage ADC, or
Measurement of current and voltage
Current ADC
Interrupt
t
FP
LP / ULP
FP
3.7.2.7
Performing Continuous Measurements of Current and Internal Temperature during
LP/ULP State
This setup is the same as the configuration described in the previous section, except that the internal tem-
perature instead of the voltage is measured. To use this option, pdMeas must be set to 6. Possible wake-up
sources during this scenario are the watchdog timer interrupt, the sleep timer interrupt, the LIN wakeup interrupt
(for ZSSC1750 only), or any of the ADC interrupts related to current or temperature.
3.7.2.8
Performing Continuous Measurements of Current and External Temperature during
LP/ULP State
This setup is the same as the configuration described in the previous section, except that the external
temperature instead of the internal temperature is measured. To use this option, pdMeas must be set to 7.
Possible wake-up sources during this scenario are the watchdog timer interrupt, the sleep timer interrupt, the LIN
wakeup interrupt (for ZSSC1750 only), or any of the ADC interrupts related to current or temperature.
3.7.3 OFF State
The OFF State is the power-down state with the lowest current consumption, and no ADC measurements are
possible. It is intended for long periods of inactivity; e.g., when a car is shipped around the world. During this
state, all oscillators and clocks are turned off, the external microcontroller is not powered, and most of the analog
blocks are powered down. Only the SBC’s digital core and the RX part of the LIN PHY remain powered. The
system can only wake up at the detection of a LIN wakeup frame (for ZSSC1750 only) or after power-on reset
(for ZSSC1750/51). To go to the OFF State, the following tasks must be done:
•
Set irqEna[4]to 1 to enable the LIN wake-up detector and to enable the system to wake up due to a
LIN wakeup frame (for ZSSC1750 only).
•
•
Set pdStateto 3 to configure the OFF State as the power-down state to be entered.
Write A9HEX to register gotoPdand drive the CSN line high.
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For the ZSSC1750 only, when the LIN RXD line goes low during the OFF State, the low-power oscillator is re-
enabled and the digital logic checks if the LIN RXD line is low for a time equal or more than 150µs. If this is true,
the complete system returns to the FP State and the external microcontroller is powered up, reset, and clocked
again. If the LIN RXD line was low for less than 150µs, the low-power oscillator is powered down again and the
system remains in OFF State.
Important: If the LIN wakeup interrupt is not enabled, the system only can only wake up by a power-on reset.
3.7.4 Registers for Power Configuration and the Discreet Current Measurement Count
3.7.4.1
Register “pwrCfgFp” – Power Configuration Register for the FP State
Table 3.18 Register pwrCfgFp
Name
Address
Bits
Default
Access
Description
pwrAdcI
pwrAdcV
[0]
[1]
0BIN
0BIN
RW
RW
When set to 1, the current ADC is powered.
When set to 1, the voltage/temperature ADC is
powered.
Reserved
lpEnaFp
[2]
[3]
0BIN
0BIN
RW
RW
Reserved; always write as 0.
When set to 1, the bias current of the analog blocks
is reduced to 10% in the FP State.
Note: if ulpEnaFpis also set to 1, the bias current
of the analog blocks is reduced to 15%.
53HEX
ulpEnaFp
[4]
0BIN
RW
When set to 1, the bias current of the analog blocks
is reduced to 5% in the FP State.
Note: if lpEnaFpis also set to 1, the bias current
of the analog blocks is reduced to 15%.
When set to 1, the offset cancellation of the
reference buffer is powered down.
pdRefbufOcFp
Unused
[5]
0BIN
RW
RO
[7:6]
00BIN
Unused; always write as 0.
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3.7.4.2
Register “pwrCfgLp” – Power Configuration Register for Power-Down States
Table 3.19 Register pwrCfgLp
Name
Address
Bits
Default
Access
Description
pdState
[1:0]
00BIN
RW
Select the power-down state to be entered:
0 or 1 LP State
2
3
ULP State
OFF State
pdMeas
[4:2]
000BIN
RW
Type of measurements to be performed during the
LP or ULP State:
0
1
No measurements
Discrete measurements of
current
2
3
Discrete measurements of
current, voltage, and
internal temperature
Discrete measurements of
current, voltage, and
external temperature
Continuous measurements
of current
Continuous measurements
of current and voltage
Continuous measurements
of current and internal
temperature
4
5
6
64HEX
7
Continuous measurements
of current and external
temperature
lpEnaLp
[5]
[6]
[7]
1BIN
0BIN
0BIN
RW
RW
RW
When set to 1, the bias current of the analog blocks
is reduced to 10% in the LP/ULP State.
Note: if ulpEnaLpis also set to 1, the bias current
of the analog blocks is reduced to 15%.
When set to 1, the bias current of the analog blocks
is reduced to 5% in the LP/ULP State.
Note: If lpEnaLpis also set to 1, the bias current
of the analog blocks is just reduced to 15%.
When set to 1, the offset cancellation of the
reference buffer is powered in LP/ULP State while
performing measurements.
ulpEnaLp
pwrRefbufOcLp
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3.7.4.3
Register “gotoPd” – Enter Power-Down State
Table 3.20 Register gotoPd
Name
Address
Bits
Default
Access
Description
gotoPd
65HEX
[7:0]
00HEX
WO
Writing A9HEX to this register triggers the PMU to
enter the configured power-down state when the
CSN line is driven high.
3.7.4.4
Register “discCvtCnt” – Configuration Register for Discrete Measurements
Table 3.21 Register discCvtCnt
Name
Address
Bits
Default
Access
Description
discCvtCnt
5FHEX
[7:0]
00HEX
RW
Defines the number of "current only" measurements
before performing one measurement of current,
voltage, and temperature when pdMeas is 2 or 3.
3.8 ZSSC1750/51 ADC Unit
The measurement subsystem incorporates two independent and synchronized high-resolution ADCs for
monitoring two channels (SD_ADC blocks). The conversion scheme is based on the sigma-delta modulation
(SDM) principle. One channel (ADC-I) is exclusively used for current measurement and includes a pre-amplifier
with offset cancellation circuitry. The second channel (ADC-V/T) can be programmed for measuring either
voltage or temperature (internal or external).
The raw conversion data can be post-processed by calibration data to achieve a minimum offset and gain error
(gain and offset correction). The conversion results are stored in the register file from which they can be read via
the SPI digital communication interface. A completed conversion is flagged by a “data ready” signal that can be
used as an interrupt source for the external microcontroller. A functional block diagram of the analog circuitry is
shown in Figure 3.12.
The purpose of this analog architecture is to achieve a maximum level of diagnostic capability and flexibility as
well as best accuracy.
The digital ADC unit consists of the data processing unit and control logic. The control logic generates the clocks
and control signals for the analog SD-ADCs as well as control signals for the data processing part of the ADC
unit.
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Figure 3.12 Functional Block Diagram of the Analog Measurement Subsystem
cSel
VDDA
cSel
VSSA
fINT / fDEC
fiSC
fiSC
IM
sinc4
INP
IPZ1
Digital
Filter
MPX1
PGA-2
SG-Modulator-1
INN
VSSA
PA-C
PGA-1
IPZ2
VREF 1.2V
MPX2
VCM
VSSA
pd_vbat
VREFLP 1.2V
fSDM
VREF 1.2V
VCM
VBAT
VDDA
pd_inamp
VSSA
SC-Clock
Generator
VBATP
VBATN
fINT / fDEC
RREF
MPX3
fiSC
IPZ3
IPZ4
NTH
NTL
sinc4
Digital
Filter
RNTC
SG-Modulator-2
CVDA
pdExtTemp
VPTAT
On-Chip
Temperature
Sensor
Analog-2-Digital Conversion
PA-T
vtSel
VSSA
VCM=VDDA/2
PA-C = Preamplifier Current; PA-T = Preamplifier Temperature; MPX = Multiplexer; PGA = Programmable Gain Amplifier
3.8.1 ADC Clocks
Two clocks are generated in the digital part of the ADC unit and are driven to the analog part. The SDM clock is
used for both SD-ADCs. The chop clock is used for the chopping operation within the SD-ADCs. The base for
both clocks is the multiplexed clock muxClk, which is a 4MHz clock in FP State and a 125kHz clock in LP/ULP
State.
3.8.1.1
ADC Clocks in FP State
In the FP State, the SDM clock is generated from the 4MHz clock by dividing it by two times the value prog-
rammed into bit field sdmClkDivFp in register sdmClkCfgFp (see Table 3.24):
fHP
fSDM
=
fHP = 4MHz
(4)
2∗sdmClkDivFp
Important: When sdmClkDivFpis set to 0, the frequency of SDM clock is 2MHz.
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The chop clock is generated from the SDM clock by further dividing it by 2, 4, 8, or 16 depending on the setting
of the sdmChopClkDivfield in register adcGomd (see Table 3.55):
fCHOP = fSDM ∗2-(sdmClkChopDiv+1)
(5)
Although the clock bases used to generate the SDM and the chop clock have a frequency of 4MHz, the position
of the clock edges used for the clock generation can be shifted relative to the 4MHz clock used for the digital
logic to obtain optimal noise behavior for the analog section. The 4MHz clock used to generate the SDM clock
(CLKSDMBASE) is delayed relative to the 4MHz clock used for the digital logic (CLKMUXCLK) by one to four 20MHz
clock cycles (CLKHPOSC) depending on the settings of the field sdmPos in register sdmClkCfgFp (Table 3.24).
The 4MHz clock used to generate the chop clock (CLKCHOPBASE) is delayed relative to the 4MHz clock used for
the digital logic (CLKSDMBASE) by zero to four 20MHz clock cycles depending on the settings of field sdmPos2and
field sdmPos in register sdmClkCfgFp. The delay in the number of 20MHz clock cycles of the chop clock
relative to the SDM clock can be calculated using the following formula:
delay = (sdmPos2- sdmPos)mod5
(6)
Important: The delay programmed into field sdmPos2 is related to CLKMUXCLK, not to CLKSDMBASE. Table 3.22
shows the value that must be programmed into field sdmPos2 depending on the field sdmPos and the desired
delay.
Table 3.22 Value for sdmPos2Depending on sdmPosand Desired Clock Delay from SDM to Chop Clock
sdmPos2
Delay
sdmPos =0
sdmPos =1
sdmPos=2
sdmPos=3
0
1
2
3
4
0
1
2
3
4
1
2
3
4
0
2
3
4
0
1
3
4
0
1
2
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Figure 3.13 FP ADC Clocking Scheme for sdmPos= sdmPos2= 2; sdmClkDivFp= 1; sdmChopClkDiv= 0
CLKHPOSC
CNT
4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
CLKMUXCLK
CLKSDMBASE
CLKCHOPBASE
SDM clock
CHOP clock
Figure 3.14 FP ADC Clocking for sdmPos= 1 and sdmPos2= 4; sdmClkDivFp= 1; sdmChopClkDiv= 0
CLKHPOSC
CNT
4
0
1
2
3
4
0
1
2
3
4
0
1
2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
CLKMUXCLK
CLKSDMBASE
CLKCHOPBASE
SDM clock
CHOP clock
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Figure 3.15 FP ADC Clocking for sdmPos= 3 and sdmPos2= 0; sdmClkDivFp= 1; sdmChopClkDiv= 0
CLKHPOSC
CNT
4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
CLKMUXCLK
CLKSDMBASE
CLKCHOPBASE
SDM clock
CHOP clock
Figure 3.16 FP ADC Clocking for sdmPos= 0 and sdmPos2= 3; sdmClkDivFp= 1; sdmChopClkDiv= 0
CLKHPOSC
CNT
4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2
CLKMUXCLK
CLKSDMBASE
CLKCHOPBASE
SDM clock
CHOP clock
3.8.1.2
ADC Clocks in the LP/ULP State
In the LP or ULP State, the SDM clock is generated from the 125 kHz clock (CLKLPOSC) by dividing it by two times
the value programmed into register sdmClkDivLp(see Table 3.23):
fLP
fSDM
=
; fLP = 125kHz
(7)
2∗s dmCl k Di v Lp
Important: When sdmClkDivLpis set to 0, the frequency of the SDM clock is 62.5 kHz.
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The chop clock is generated from the SDM clock by further dividing it by 2, 4, 8, or 16 depending on the setting
of the sdmChopClkDivfield in register adcGomd:
fCHOP = fSDM ∗ 2-(sdmChopClkDiv +1)
(8)
Both the SMD and chop clocks are generated from the same 125kHz clock that is used for the digital logic.
Shifting of the clocks used to generate the SDM and chop clock is not possible and not needed as the analog
clocks are generated on the falling clock edge where the digital logic is already stable and will not influence the
analog section.
Figure 3.17 LP/ULP ADC Clocking Scheme; sdmClkDivLp= 5; sdmChopClkDiv= 0
CLKLPOSC
SDM clock
CHOP clock
3.8.1.3
Register “sdmClkCfgLp” – Configuration Register for the SDM Clocks in the LP/ULP State
Table 3.23 Register sdmClkCfgLp
Name
Address
Bits
Default
Access
Description
sdmClkDivLp[7:0]
sdmClkDivLp[9:8]
B0HEX
[7:0]
[1:0]
18HEX
00BIN
RW
RW
Clock divider value for the SDM clock in the LP
and ULP States related to the 125KHz base clock.
With sdmClkDivLP = 0, the divider value is 2.
Unused; always write as 0.
B1HEX
Unused
[7:2] 00 0000BIN
RO
3.8.1.4
Register “sdmClkCfgFp” – Configuration Register for the SDM Clocks in the FP State
Table 3.24 Register sdmClkCfgFp
Name
Address
Bits
Default
Access
Description
sdmClkDivFp[7:0]
sdmClkDivFp[9:8]
B2HEX
[7:0]
[1:0]
08HEX
00BIN
RW
RW
Clock divider value for the SDM clock in the FP
State related to the 4MHz base clock fHP.
If 0, then the SDM clock is 2MHz.
Unused; always write as 0
Position of the chop clock (CLKCHOPBASE) relative
to the base clock CLKMUXCLK (possible values = 0
to 4)
Unused
sdmPos2
[2]
0BIN
RO
RW
[5:3] 010BIN
B3HEX
sdmPos
[7:6]
10BIN
RW
Position of the SDM clock (CLKSDMBASE) relative to
the base clock CLKMUXCLK
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3.8.2 ADC Data Path
The incoming 2nd and 3rd order bit streams from the analog part of the SD-ADCs are first captured and then
driven through a 3rd order noise shaping filter as illustrated in Figure 3.18. The digital conversion is accomplished
by a 4th order low-pass filter (sinc4 decimation filter). The bit stream capturing and the noise shaping filter cannot
be directly changed by the user (no configuration registers), but the selected oversampling rate (adcSamp
register field osr) affects the sinc4 decimation filter (one output value per N input values).
Figure 3.18 Functional Block Diagram of the Digital ADC Data Path
{000, BIST bitstream}
4
4
4
sinc
Decimation
SDM 1
SDM 2
Filter
Noise
Bitstream
Capture
Cancellation
Post Filter
Data Post
Correction
Result Register
A simple post filter (moving average filter) is placed behind the sinc4 decimation filter. The user can select the
averaging function (no averaging; 2-stage averaging; or 3-stage averaging) via the avgFiltCfg bit field in the
adcSamp register (see Table 3.56) when chopping is disabled (see section 3.8.4.4). When chopping is enabled,
the 2-stage averaging is used independently of the filter configuration.
The function of the 2-stage averaging filter is
x (t) + x (t -1)
in
in
x
(t) =
(9)
out
2
The function of the 3-stage averaging filter is
xin(t) + 2∗ xin(t -1) + xin(t - 2)
xout (t) =
(10)
4
Where t = current sample
t-1 = previous sample
t-2 = sample before previous sample, etc.
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3.8.2.1
Data Post-Correction Block
The data post-correction block performs the offset and gain correction of the post-filtered conversion data as well
as the over-range and the overflow detection.
Figure 3.19 Data Post Correction
Post-Filter
Channel 1
x
x
+
Post-Filter
Channel 2
First, an over-range check is performed on the incoming data. Values that are outside the interval [-0.75; 0.75)
are always mapped to the corresponding interval boundary. This is done for better results as the ADC accuracy
decreases for large input values. The user can enable a “set interrupt” strobe for each of the two channels by
setting the adcAcmpregister bits COvrEnaand VTOvrEnato 1 (see Table 3.54).
Note: The “set interrupt” strobes go to the interrupt controller. They have a different meaning than the corres-
ponding “interrupt enable” bits (interrupt bits [15:14] in the irqEnaregister). The “set interrupt” bits are used to
select whether the interrupt status bits will be set or not; the “interrupt enable” bits select whether the interrupt
status bits will drive the interrupt line or not.
After the over-range check, a programmable offset, interpreted as a number in the range [-1.0; 1.0), is added to
the data. Three registers allow setting different offsets for current, voltage, and temperature: adcCoff,
adcVoff, and adcToff (see Table 3.25, Table 3.27, and Table 3.29 respectively).
The offset correction is followed by two multiplication stages. In the first multiplication stage, individual gain
factors for current (adcCgan), voltage (adcVgan), or temperature (adcTgan), interpreted as numbers in the
range [0.0; 2.0), are multiplied by the offset corrected data (see Table 3.26, Table 3.28, and Table 3.30
respectively). The second multiplication stage is used to shift the significant data into the most significant bits of
the result register. The data is multiplied by 1, 2, 4, or 8, which can be individually selected for current, voltage,
and temperature via the curPoCoGain, voltPoCoGain, and tempPoCoGain fields in the adcPoCoGain
register (see Table 3.31).
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Figure 3.20 Data Representation through Data Post Correction including Over-Range and Overflow Levels
Note: the yellow area represents the usable data space to avoid overflow when the post correction gain is 2.
Input to Data
Post-Correction
Gain and Offset
Correction
Post-Correction
Overflow
1
2.4V
FFFFFFHEX
E00000HEX
7FFFFFHEX
600000HEX
7FFFFFHEX
600000HEX
Over-Range
3/4 1.8V
1/2 1.2V
C00000HEX
400000HEX
400000HEX
800000HEX
000000HEX
000000HEX
0
0.0V
poCoGain = 2
400000HEX
200000HEX
C00000HEX
A00000HEX
C00000HEX
A00000HEX
-1/2 -1.2V
-3/4 -1.8V
-1 -2.4V
Over-Range
000000HEX
800000HEX
800000HEX
Overflow
Unsigned
Signed
Signed
An overflow check is performed on the output of the second multiplication stage as the result might be out of the
representable range of [-1.0; 1.0). The user can also enable a “set interrupt” strobe for each of the two channels
by setting the adcAcmpregister bits COvrEnaand/or VTOvrEnato 1 (same bits as for the over-range check).
Note: Although the same “set interrupt strobe enable” bit is used for over-range and overflow, independent
interrupt status bits can be individually enabled or disabled.
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Figure 3.21 illustrates the common enable CovrEna for the interrupt strobes for current over-range and
overflow. The function of VTOvrEna as the common enable for the interrupt strobes for voltage/temperature
over-range and overflow conditions is similar.
Figure 3.21 Common Enable for the “set overrange” and “set overflow” Interrupt Strobes for Current
irqStat[12]
current overflow detected
COvrEna
(current overflow)
set interrupt
set interrupt
&
&
irqStat[14]
(current overrange)
current overrange detected
3.8.2.2
Register “adcCoff” – Offset Correction Value for Current Channel
Table 3.25 Register adcCoff
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
00HEX
adcCoff[7:0]
adcCoff[15:8]
adcCoff[23:16]
33HEX
34HEX
35HEX
[7:0]
[7:0]
[7:0]
RW
RW
RW
Offset value for current value; interpreted as a
number in the range [-1.0; 1.0) formatted in 2’s
complement representation. Programmable offset
range = +/- 2 VREF; VREF= full-scale range ADC.
Note: The initial value is loaded from OTP after
reset.
3.8.2.3
Register “adcCgan” – Gain Correction Value for Current Channel
Table 3.26 Register adcCgan
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
80HEX
adcCgan[7:0]
adcCgan[15:8]
adcCgan[23:16]
30HEX
31HEX
32HEX
[7:0]
[7:0]
[7:0]
RW
RW
RW
Gain value for current value; interpreted as a
number in the range [0.0; 2.0).
Note: The initial value is loaded from OTP after
reset.
3.8.2.4
Register “adcVoff” – Offset Correction Value for Voltage Channel
Table 3.27 Register adcVoff
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
00HEX
adcVoff[7:0]
adcVoff[15:8]
adcVoff[23:16]
39HEX
3AHEX
3BHEX
[7:0]
[7:0]
[7:0]
RW
RW
RW
Offset value for voltage value; interpreted as a
number in the range [-1.0; 1.0) formatted in 2’s
complement representation. Programmable offset
range = +/- 2 VREF; VREF= full-scale range ADC.
Note: The initial value is loaded from OTP after
reset.
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3.8.2.5
Register “adcVgan” – Gain Correction Value for Voltage Channel
Table 3.28 Register adcVgan
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
80HEX
adcVgan[7:0]
adcVgan[15:8]
adcVgan[23:16]
36HEX
37HEX
38HEX
[7:0]
[7:0]
[7:0]
RW
RW
RW
Gain value for voltage value; interpreted as a
number in the range [0.0; 2.0)
Note: The initial value is loaded from OTP after
reset.
3.8.2.6
Register “adcToff” – Offset Correction Value for Temperature Channel
Table 3.29 Register adcToff
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
adcToff[7:0]
adcToff[15:8]
3EHEX
3FHEX
[7:0]
[7:0]
RW
RW
Offset value for temperature value; interpreted as
a number in the range [-1.0; 1.0)
Note: The initial value is loaded from OTP after
reset.
3.8.2.7
Register “adcTgan” – Gain Correction Value for Temperature Channel
Table 3.30 Register adcTgan
Name
Address
Bits
Default
00HEX
Access
Description
adcTgan[7:0]
adcTgan[15:8]
3CHEX
3DHEX
[7:0]
[7:0]
RW
RW
Gain value for temperature value; interpreted as
a number in the range [0.0; 2.0)
80HEX
Note: The initial value is loaded from OTP after
reset.
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3.8.2.8
Register “adcPoCoGain” – Post Correction Gain Configuration
Table 3.31 Register adcPoCoGain
Name
Address
Bits
Default
Access
Description
Post correction gain for the current channel:
curPoCoGain
[1:0]
00BIN
RW
0
1
2
3
Gain factor is 1
Gain factor is 2
Gain factor is 4
Gain factor is 8
voltPoCoGain
tempPoCoGain
Unused
[3:2]
[5:4]
[7:6]
00BIN
00BIN
00BIN
RW
RW
RO
Post correction gain for the voltage channel:
0
1
2
3
Gain factor is 1
Gain factor is 2
Gain factor is 4
Gain factor is 8
57HEX
Post correction gain for the temperature channel:
0
1
2
3
Gain factor is 1
Gain factor is 2
Gain factor is 4
Gain factor is 8
Unused; always write as 0.
3.8.3 ADC Operating Modes and Result Registers
3.8.3.1 Single Measurement Results
Each value coming from the data post-correction block is the result of a single measurement. These values are
signed and stored in the corresponding result registers adcCdat, adcVdat, adcTdat,or adcRdat(see Table
3.32 through Table 3.35).The following formulas can be used to calculate the battery current and the battery
voltage from the result register values:
adcCdat ∗ 2∗ VREF
IBAT
=
(11)
23
∗
∗ ∗
GANA GPOCO
RSHUNT
2
adcVdat ∗ 24 ∗ 2∗ VREF
VBAT
=
(12)
223 GPOCO
∗
Where:
IBAT
Battery current
VBAT
Battery voltage
GANA
Analog gain in current path (pgaIfc pga1 pga2; see Table 3.36)
Digital gain in post-correction stage (second multiplication; see Table 3.31)
Shunt resistance
GPOCO
RSHUNT
VREF
Reference voltage
adcCdat Register value for current
adcVdat Register value for voltage
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3.8.3.2
Register “adcCdat” – Single Current Measurement Value
Table 3.32 Register adcCdat
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
00HEX
adcCdat[7:0]
adcCdat[15:8]
adcCdat[23:16]
02HEX
03HEX
04HEX
[7:0]
[7:0]
[7:0]
RO
RO
RO
Conversion result of a single current
measurement (signed value)
3.8.3.3
Register “adcVdat” – Single Voltage Measurement Value
Table 3.33 Register adcVdat
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
00HEX
adcVdat[7:0]
adcVdat[15:8]
adcVdat[23:16]
05HEX
06HEX
07HEX
[7:0]
[7:0]
[7:0]
RO
RO
RO
Conversion result of a single voltage
measurement (signed value)
3.8.3.4
Registers “adcTdat” and “adcRdat” – Single Temperature Measurement Values
Table 3.34 Register adcTdat
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
adcTdat[7:0]
adcTdat[15:8]
0AHEX
0BHEX
[7:0]
[7:0]
RO
RO
Conversion result of a single temperature value
(signed value; inverted); this value is either the
internally measured temperature or the NTC value
of an external temperature measurement.
Important: This value is sign-inverted.
Table 3.35 Register adcRdat
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
adcRdat[7:0]
adcRdat[15:8]
08HEX
09HEX
[7:0]
[7:0]
RO
RO
Conversion result of a single temperature
measurement by reading a voltage across the
reference resistor (external temperature
measurement only).
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3.8.3.5
Register “adcGain” – Analog Gain Configuration in the Current Path
Table 3.36 Register adcGain
Name
Address
Bits
Default
Access
Description
pgaIfc
[1:0]
00BIN
RW
Sets the gain of the PA-C preamplifier in the
analog current path:
0
1
2
3
Gain factor is 1
Gain factor is 2
Gain factor is 4
Gain factor is 8
pga1
pga2
[3:2]
[4]
00BIN
RW
Sets the gain of the PGA-1 programmable gain
amplifier in the analog current path:
0
1
2
3
Gain factor is 1
Gain factor is 2
Gain factor is 4
Gain factor is 8
52HEX
0BIN
RW
RO
Sets the gain of PGA-2 programmable gain
amplifier in the analog current path:
0
1
Gain factor is 4
Gain factor is 8
Unused
[7:5] 000BIN
Unused; always write as 0.
3.8.3.6
Result Counter Functionality and Conversion Ready Strobes
Three status bits are available in the interrupt status (irqStat[7:5]) that signal that the conversion of current,
voltage, or temperature has been completed. The “set interrupt” strobe is generated for each completed
temperature measurement. For the voltage and current measurements, the user can independently select
whether the corresponding “set interrupt” strobe will be generated after each single measurement (SRCS –
single result count sequence) or after N measurements (MRCS – multi-result count sequence).
The register adcCrcl configures the number of current measurements before the current conversion ready
strobe is generated; the maximum number is 65535 (see Table 3.37). Setting this register to 0 disables the result
count functionality, which means that SRCS is configured. The present result counter value can always be read
from the register adcCrcv(see Table 3.38). The result counter is reset when the bit field startAdcCin register
adcCtrl is set (rising edge) in the FP State (see Table 3.58) or at the start of the first measurement in LP/ULP
State. It is set to 1 at the end of the first measurement after the limit defined in adcCrclhas been reached.
The register adcVrcl configures the number of measurements before the voltage conversion ready strobe is
generated, the maximum number is 15 (see Table 3.39). Setting this register to 0 disables the result count
functionality, which means that SRCS is configured. The present result counter value can always be read from
the register adcVrcv(see Table 3.40). The result counter is reset when startAdcVin register adcCtrl is set
(rising edge) in the FP State or at the start of the first measurement in the LP/ULP State. It is set to 1 at the end
of the first measurement after the limit defined in adcVrclwas reached.
Note: Setting register adcCrclor adcVrclto 1 also leads to SRCS in the corresponding channel.
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3.8.3.7
Register “adcCrcl” – Current Result Count Limit
Table 3.37 Register adcCrcl
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
adcCrcl[7:0]
adcCrcl[15:8]
40HEX
41HEX
[7:0]
[7:0]
RW
RW
Number of current measurements before the
current conversion ready strobe is generated.
Note: Setting this bit to 0 disables this
functionality, and the strobe is generated after
each current measurement.
3.8.3.8
Register “adcCrcv” – Current Result Count Value
Table 3.38 Register adcCrcv
Name
Address
Bits
Default
Access
Description
00HEX
00HEX
adcCrcv[7:0]
adcCrcv[15:8]
1BHEX
1CHEX
[7:0]
[7:0]
RO
RO
Present value of the current result counter.
3.8.3.9
Register “adcVrcl” – Voltage Result Count Limit
Table 3.39 Register adcVrcl
Name
Address
Bits
Default
Access
Description
0000BIN
adcVrcl
[3:0]
RW
Number of voltage measurements before the
voltage conversion ready strobe is generated.
Note: Setting this bit to 0 disables this
functionality, and the strobe is generated after
each voltage measurement.
45HEX
0000BIN
Unused
[7:4]
RO
Unused; always write as 0.
3.8.3.10 Register “adcVrcv” – Voltage Result Count Value
Table 3.40 Register adcVrcv
Name
Address
Bits
Default
Access
Description
0000BIN
0000BIN
adcVrcv
Unused
[3:0]
[7:4]
RO
RO
Present value of the voltage result counter.
Unused; always write as 0.
1EHEX
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3.8.3.11 Current Threshold Comparator Functionality
The current threshold comparator functionality is used to monitor the current level and to generate an interrupt
(irqStat[8]) if the absolute current value exceeds a programmable limit for a configurable number of
conversion results. This functionality is enabled if the field ctcvMode in register adcAcmp is set to a non-zero
value (see Table 3.54Table 3.58). If enabled, this function is always triggered when a new current value is
measured. The absolute value of the most significant 17 bits of the measured current value is compared to the
expanded programmable threshold register adcCrth(see Table 3.41):
abs
(
adcCdat
[
23 : 7
]
)
≥
{
0,adcCr t h
}
(13)
When the current threshold comparator functionality is enabled, the current threshold counter is used to count
the number of conversions where the absolute current value is above the threshold. If the absolute current value
is greater than or equal to the programmed threshold (above formula is true), the internal current threshold
counter is incremented (until it reaches its maximum value FFHEX). Otherwise the counter is either decremented
(if ctcvMode field in register adcAcmp set to 1) or reset (if ctcvMode set to 2), or it remains unchanged (if
ctcvModeset to 3). The present value of the current threshold counter can be read from the register adcCtcv
(see Table 3.43).
Note: When bit field ctcvModein register adcAcmp is set to 00BIN, the current threshold comparator function-
ality is disabled and register adcCrtvis always 0.
Note: When ctcvModeis set to 01BIN, the current threshold counter is not decremented when the counter is 0.
After each comparison of the absolute current value versus the current threshold level and after the current
threshold counter has been updated, the internal current threshold counter is compared to the current threshold
counter limit (register adcCtcl; see Table 3.42). Whenever the current threshold counter is greater than or
equal to the programmable limit, a “set interrupt” strobe is generated.
Note: When the current threshold counter has reached its limit and it is configured to keep its value if the limit is
not reached, a “set interrupt” strobe is generated for each new measurement even if the new value is below
threshold.
The current threshold counter is reset to 0 for the following conditions:
•
•
•
•
If ctcvModeis set to 2 and the absolute current value is below the programmed threshold adcCrth
On assertion of startAdcC(rising edge) in the FP State
At the start of the first conversion in the LP or ULP State
Each time the result counter is reset (if the result counter is enabled) and the current threshold counter
reset mode bit (bit ctcvRstModein register adcAcmp) is set to 1
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3.8.3.12 Register “adcCrth” – Absolute Current Threshold
Table 3.41 Register adcCrth
Name
Address
Bits
Default
Access
Description
adcCrth[7:0]
adcCrth[15:8]
42HEX
43HEX
[7:0]
[7:0]
00HEX
00HEX
RW
RW
Absolute current threshold (unsigned value).
When using current comparator threshold
functionality, the absolute current value is
compared to {0, adcCrth}.
3.8.3.13 Register “adcCtcl” – Current Threshold Counter Limit
Table 3.42 Register adcCtcl
Name
Address
Bits
Default
Access
Description
adcCtcl
44HEX
[7:0]
00HEX
RW
Current threshold counter limit.
This register defines the number of current
measurements that must be greater than or equal
to the threshold adcCrthbefore the interrupt is
set.
3.8.3.14 Register “adcCtcv” – Current Threshold Counter Value
Table 3.43 Register adcCtcv
Name
Address
Bits
Default
Access
Description
adcCtcv
1DHEX
[7:0]
00HEX
RO
Present current threshold counter value.
3.8.3.15 Current Accumulator Functionality
The current accumulator functionality is used to sum up all current conversion results. The present accumulator
value can be read from the register adcCaccu (signed value; see Table 3.45). Positive conversion results
increment the accumulator register, negative conversion results decrement it. The accumulator register saturates
at its minimum and maximum value.
The current accumulator is reset to 0 under these conditions:
•
•
•
On assertion of startAdcC(rising edge) in the FP State
At the start of the first conversion in the LP or ULP State
Each time the result counter is reset (if the result counter is enabled) and the current accumulator reset
mode bit (bit accuRstModein register adcAcmp) is set to 1
Note: The current accumulator functionality can be used to calculate the mean value of the current.
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The current accumulator is also compared to a programmable signed accumulator threshold value (register
adcCaccTh). This comparison can be used to generate a “set interrupt” strobe for irqStat[11]; however, to
enable the generation of the “set interrupt” strobe, bit CAccuThEna in register adcAcmp must be set to 1 (see
Table 3.54). The “set interrupt” strobe is always generated on update of the accumulator register when
•
•
•
adcCaccThis greater than 0 and adcCaccuis greater than adcCaccTh
adcCaccThis lower than 0 and adcCaccuis lower than adcCaccTh
adcCaccThis equal to 0 and adcCaccuis not equal to 0
3.8.3.16 Register “adcCaccTh” – Current Accumulator Threshold Value
Table 3.44 Register adcCaccTh
Name
Address
Bits
Default
Access
Description
adcCaccTh[7:0]
adcCaccTh[15:8]
adcCaccTh[23:16]
adcCaccTh[31:24]
48HEX
49HEX
4AHEX
4BHEX
[7:0]
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
00HEX
RW
RW
RW
RW
Signed threshold value for current accumulator
mode
3.8.3.17 Register “adcCaccu” – Current Accumulator Value
Table 3.45 Register adcCaccu
Name
Address
Bits
Default
Access
Description
adcCaccu[7:0]
0CHEX
0DHEX
0EHEX
0FHEX
[7:0]
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
00HEX
RO
RO
RO
RO
Present current accumulator value
adcCaccu[15:8]
adcCaccu[23:16]
adcCaccu[31:24]
3.8.3.18 Voltage Threshold Comparator and Voltage Accumulator Functionality
The ZSSC1750/51 also provides a threshold comparator as well as an accumulator comparator for the battery
voltage channel but with reduced functionality.
If the VThSel bit in register adcAcmp is set to 0, the absolute value of the most significant 17 bits of a single
voltage measurement (register adcVdat) is compared to the programmable voltage threshold (register adcVTh;
see Table 3.46). In this case, register adcVTh is interpreted as an unsigned value. There is also no counter
functionality. Whenever the absolute voltage value is below the programmed threshold, a “set interrupt” strobe
for irqStat[9]is generated if the strobe generation is enabled (the field VThWuEnain register adcAcmpis set
to 1).
abs
(
adcVdat
23 : 7
)
<
{
0,adcVTh
}
(14)
When bit VThSelin register adcAcmpis set to 1, the voltage accumulator functionality is enabled. The voltage
result counter functionality must also be enabled (register adcVrcl> 0). The voltage accumulator functionality is
used to sum up all voltage conversion results. In contrast to the current channel, only the upper 20 bits of the
voltage conversion results are accumulated. The present accumulator value can be read from the register
adcVaccu(signed value; see Table 3.47). Positive conversion results increment the accumulator register; neg-
ative conversion results decrement it. The accumulator register saturates at its minimum and maximum value.
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The voltage accumulator is reset to 0 under these conditions:
•
•
•
On assertion of startAdcV(rising edge) in the FP State
At start of the first conversion in the LP or ULP State
Each time the result counter is reset (if the result counter is enabled)
Note: The voltage accumulator functionality can be used to calculate the mean value of the voltage.
After the last accumulation within an MRCS, the upper 16 bits of the voltage accumulator are compared to the
voltage threshold adcVTh, which is interpreted as a signed value in this case. This comparison can be used to
generate a “set interrupt” strobe for irqStat[9]; however, to enable the generation of the “set interrupt” strobe,
bit VThWuEnain register adcAcmpmust be set to 1.
The “set interrupt” strobe is generated when
•
•
•
adcVThis greater than 0 and adcVaccuis less than or equal to adcVTh
adcVThis lower than 0 and adcVaccuis greater than or equal to adcVTh
adcVThis equal to 0 and adcVaccuis equal to 0
Important: The threshold adcVTh is either interpreted as an unsigned or signed value depending on the
operation mode (VThSel).
Note: The voltage comparators compare only on the MSBs of the conversion result, so it might be beneficial to
use the post-correction gain functionality to shift left the results to increase the accuracy of the comparison.
3.8.3.19 Register “adcVTh” – Voltage Threshold Value
Table 3.46 Register adcVTh
Name
Address
Bits
Default
Access
Description
adcVTh[7:0]
adcVTh[15:8]
46HEX
47HEX
[7:0]
[7:0]
00HEX
00HEX
RW
RW
Voltage threshold.
If VThSel == 0, then adcVThis interpreted as an
unsigned value and it is compared to the absolute
value of a single voltage conversion.
If VThSel== 1, then adcVThis interpreted as a
signed value and it is compared to the accumu-
lated voltage conversion results at the end of an
MRCS.
3.8.3.20 Register “adcVaccu” – Voltage Accumulator Value
Table 3.47 Register adcVaccu
Name
Address
Bits
Default
Access
Description
adcVaccu[7:0]
adcVaccu[15:8]
adcVaccu[23:16]
10HEX
11HEX
12HEX
[7:0]
[7:0]
[7:0]
00HEX
00HEX
00HEX
RO
RO
RO
Present voltage accumulator value
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3.8.3.21 Minimum and Maximum Values of Current and Voltage
For current and voltage measurements, the minimum and maximum values are determined on the upper 16 bits
of the corresponding conversion results. These values can be read from registers adcCmax, adcCmin,
adcVmax, and adcVmin. These registers are reset in the same manner as the corresponding accumulator
registers. These values are only provided for statistical reasons and can be used to assess the accumulated
current or voltage values when used for mean value calculation.
Note: As the minimum and maximum values are only determined on the 16 MSBs of the corresponding con-
version results, it might be beneficial to use the post correction gain functionality to shift left the results to
increase the accuracy of the comparison.
3.8.3.22 Register “adcCmax” – Maximum Current Value
Table 3.48 Register adcCmax
Name
Address
Bits
Default
Access
Description
adcCmax[7:0]
adcCmax[15:8]
13HEX
14HEX
[7:0]
[7:0]
00HEX
80HEX
RO
RO
Upper 16 bits of the maximum measured current
value (signed value)
3.8.3.23 Register “adcCmin” – Minimum Current Value
Table 3.49 Register adcCmin
Name
Address
Bits
Default
Access
Description
adcCmin[7:0]
adcCmin[15:8]
15HEX
16HEX
[7:0]
[7:0]
FFHEX
7FHEX
RO
RO
Upper 16 bits of the minimum measured current
value (signed value)
3.8.3.24 Register “adcVmax” – Maximum Voltage Value
Table 3.50 Register adcVmax
Name
Address
Bits
Default
Access
Description
adcVmax[7:0]
adcVmax[15:8]
17HEX
18HEX
[7:0]
[7:0]
00HEX
80HEX
RO
RO
Upper 16 bits of the maximum measured voltage
value (signed value)
3.8.3.25 Register “adcVmin” – Minimum Voltage Value
Table 3.51 Register adcVmin
Name
Address
Bits
Default
Access
Description
adcVmin[7:0]
adcVmin[15:8]
19HEX
1AHEX
[7:0]
[7:0]
FFHEX
7FHEX
RO
RO
Upper 16 bits of the minimum measured voltage
value (signed value)
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3.8.3.26 Temperature Limits
The user can define an upper (register adcTmax) and a lower (register adcTmin) limit for the external and
internal temperature measurement. On each update of register adcTdat(see Table 3.34), the upper 8 bits are
compared to the signed limit values. This can be used to generate a “set interrupt” strobe for irqStat[10] if
the value for adcTdat is outside the interval [adcTmin; adcTmax] and the TWuEna bit in register adcAcmp is
set to 1 (see Table 3.54).
Note: The minimum and maximum values are only compared to the 8 MSBs of the conversion result, so it might
be beneficial to use the post correction gain functionality to shift left the results to increase the accuracy of the
comparison.
Important: The value stored in register adcTdatis inverted: the value given in register adcTmaxis the value for
the lower temperature interrupt threshold and the value given in register adcTmin is the value for the higher
temperature interrupt threshold.
3.8.3.27 Register “adcTmax” – Upper Boundary for Temperature Interval
Table 3.52 Register adcTmax
Name
Address
Bits
Default
Access
Description
adcTmax
4CHEX
[7:0]
00HEX
RW
Lower boundary for the temperature interval
compared to the upper bits of adcTdat.
3.8.3.28 Register “adcTmin” – Lower Boundary for Temperature Interval
Table 3.53 Register adcTmin
Name
Address
Bits
Default
Access
Description
adcTmin
4DHEX
[7:0]
00HEX
RW
Upper boundary for the temperature interval
compared to the upper bits of adcTdat.
3.8.3.29 Miscellaneous Registers
The registers defined in the next three sections provide settings that enable interrupts or control various
functions related to the ADCs.
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3.8.3.30 Register “adcAcmp” – ADC Function Enable Register
Table 3.54 Register adcAcmp
Name
Address
Bits
Default
Access
Description
anaGndSw
[0]
0BIN
RW
If set to 1, the signal pdExtTemp (see Figure
3.12), which is normally controlled by the PMU, is
forced to 1. In this case, the transistor shown in
Figure 3.12 is not conducting.
ctcvMode
[2:1]
00BIN
RW
Current threshold comparator mode:
0
The Current Threshold Comparator
Mode is disabled.
1
adcCtcv is decremented when the
absolute current value is below the
threshold and incremented otherwise.
adcCtcv is reset when the absolute
current value is below the threshold
and incremented otherwise.
adcCtcvretains its value when the
absolute current value is below the
threshold and incremented otherwise.
2
3
4EHEX
CAccuThEna
COvrEna
[3]
[4]
[5]
0BIN
1BIN
1BIN
RW
RW
RW
If set to 1, enables the strobe to interrupt the
controller when the current accumulator exceeds
its threshold.
If set to 1, enables the strobes to interrupt the
controller when an over-range or overflow has
been detected in the current channel.
If set to 1, enables the strobes to interrupt the
controller when an over-range or overflow has
been detected in the voltage/temperature
channel.
VTOvrEna
ctcvRstMode
accuRstMode
VThWuEna
[6]
[7]
[0]
0BIN
0BIN
0BIN
RW
RW
RW
If set to 1, then adcCtcvis reset when the
current result counter is reset (adcCrcv).
If set to 1, then adcCaccuis reset when the
current result counter is reset (adcCrcv).
If set to 1, enables the strobe to interrupt the
controller for the voltage threshold comparator
and voltage accumulator functionality.
If set to 0, the absolute value of the single voltage
conversion result is compared to the threshold
adcVTh.
VThSel
[1]
0BIN
RW
4FHEX
If set to 1, the accumulated results of all voltage
conversions within an MRCS are compared to the
threshold adcVTh.
TWuEna
Unused
[2]
0BIN
RW
RO
If set to 1, enables the strobe to interrupt the
controller for checking the temperature limits.
Unused; always write as 0.
[7:3] 0 0000BIN
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3.8.3.31 Register “adcGomd” – Reference Voltage and SDM Configuration
Table 3.55 Register adcGomd
Name
Address
Bits
[1:0]
Default
Access
Description
Selection of the voltage reference:
vrefSel
00BIN
RW
0
1
2
3
vbgh (high precision bandgap)
vbgl (low power bandgap)
vcm (common mode voltage)
External reference voltage
sdmChopClkDiv
sdmSetup
[3:2]
[7:4]
00BIN
RW
RW
Clock divider value for the chop clock
related to the SDM clock. See equation (5)
in section 3.8.1.1 for the FP State and
equation (8) in section 3.8.1.2 for the
LP/ULP State.
50HEX
0001BIN
Configuration of the initial setup procedure:
0
1
Execute 4 SDM clock cycles
Execute 8 SDM clock cycles
…
7
Execute 512 SDM clock cycles
8-15 Execute 1024 SDM clock cycles
3.8.3.32 Register “adcSamp” – Oversampling and Filter Configuration
Table 3.56 Register adcSamp
Name
Address
Bits
Default
Access
Description
osr
[1:0]
00BIN
RW
Oversampling rate:
0
1
2
3
256x oversampling
128x oversampling
64x oversampling
32x oversampling
Unused
avgFiltCfg
[2]
[4:3]
0BIN
00BIN
RO
RW
Unused; always write as 0.
Configuration of post filter (averaging filter) :
0-1 No averaging
51HEX
2
3
2-stage averaging filter
3-stage averaging filter
chopPause
Unused
[5]
0BIN
RW
RO
Length of pause in chopping mode:
0
1
8 SDM clock cycles
16 SDM clock cycles
[7:6]
00BIN
Unused; always write as 0.
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3.8.4 ADC Control and Conversion Timing
In the FP State, the ADC unit is running with the 4MHz clock derived from the HP oscillator. Its operation can be
fully controlled by the external microcontroller via register settings. In the LP or ULP State, the ADC unit is
running with the 125 kHz clock from the LP oscillator. Basic configurations for the ADC unit are taken from the
register file; however, its operation is fully controlled by the PMU.
3.8.4.1
ADC Operation in the FP State
Before any of the ADCs can be used in the FP State, they must be powered up by setting the pwrAdcIbit for
the current ADC and/or the pwrAdcV bit for the voltage/temperature ADC in the pwrCfgFp register to 1 (see
Table 3.18). These bits can be kept set to 1 when entering one of the power-down states as the PMU takes over
the control of the power signals.
The user can select which kind of operation will be performed by the ADCs and can control the input multiplexers
shown in Figure 3.12 by setting the field adcModein the adcCtrlregister appropriately (see Table 3.58).
The following settings are possible:
Table 3.57 adcModeSettings
adcMode
Current ADC Configuration
Voltage / Temperature ADC Configuration
Current
INP/INN
Current
INP/INN
Current
INP/INN
Voltage
0
Divided VBAT/VSSA
External temperature
VDDA/NTH and NTH/NTL
Internal temperature
VPTAT/VREF
1
2
3
4
5
6
7
Offset Calibration Mode; shortened inputs
VCM/VCM
VCM/VCM
Gain Calibration Mode @ maximum (positive) input
VREF / VSSA 1)
VREF/VSSA
Gain Calibration Mode @ minimum (negative) input
VSSA / VREF 1)
1 mV internal test voltage
1 mV/VSSA
VSSA / VREF
Voltage
Divided VBAT/VSSA
Test Mode; each multiplexer is individually controlled by the following:
cSelfield in adcChanregister (Table 3.59) vtSelfield in adcChanregister
1)
The two gain calibration modes cause an ADC over-range error in the current ADC as the minimum gain of PGA2 is 4. Therefore these modes are not
usable for the current ADC.
After setting the desired mode of operation, the user must start the conversion by setting the startAdcCbit in
the adcCtrl register (see Table 3.58) for the current channel and/or the startAdcV bit for the voltage/
temperature channel to 1. After an initial setup phase, measurement results are stored in the corresponding
result registers. By controlling the startAdcbits, the user is able to generate an individual conversion sequence
(ADC operation stops after one conversion sequence has finished) or continuous conversion (ADC operation
continues after one conversion sequence has finished).
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A conversion sequence is defined as a series of several measurements. The number of measurements to be
performed is controlled by the result counter functionality, so it is possible to have multiple measurements per
conversion sequence (MRCS) or just a single measurement (SRCS). At the end of one conversion sequence,
the “set interrupt” strobe for the corresponding conversion interrupt ready status bit (irqStat[7:5]) is
generated. Although this strobe is only generated after the last measurement within an MRCS, each
measurement in the MRCS is used for accumulation and minimum/maximum determination.
Note: The MRCS functionality is only available for current and voltage measurements, not for temperature
measurements.
To perform an individual conversion sequence for a SRCS or MRCS, the user must generate a strobe signal on
the corresponding startAdcbit by setting the startAdcbit to 1 (rising edge) first and then to 0 (falling edge).
The rising edge of startAdc signals the ADC to start the conversion. On this start signal, the corresponding
adcActive flag is set to 1, which can be read from bits 4 and 5 in the SSW (see section 3.1.1). When the
conversion sequence has finished, the corresponding ready signal is generated. At that time, the internal logic
evaluates the status of the startAdcbit again. If it was cleared already as required for an individual conversion
sequence, the ADC stops its operation and clears the adcActive flag. This behavior is shown in Figure 3.22
and Figure 3.23.
Figure 3.22 Individual SRCS
startAdc
adcActive
ready
result
a
Setup Time and Single
Measurement
Note that the ADC stops since startAdcis low at the end of the conversion sequence for the individual SRCS.
Figure 3.23 Individual MRCS (Example for Result Counter of 3)
startAdc
adcActive
ready
result
a
b
c
Setup Time and Single
Measurement
Single Measurement
Note that the ADC stops since startAdcis low at the end of the conversion sequence for an individual MRCS.
Important: The ready strobe shown in Figure 3.22 and Figure 3.23 is used to set the interrupt status bit, but the
interrupt status bit remains set until it is cleared by the user’s software.
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To perform a continuous conversion sequence for SRCS or MRCS, the user must set the corresponding
startAdcbit to 1 (rising edge). The rising edge of startAdcsignals the ADC to start the conversion. On this
start signal, the corresponding adcActive flag is set to 1, which can be read from bits 4 and 5 in the SSW.
When one conversion sequence has finished, the corresponding ready signal is generated. At that time, the
internal logic evaluates the status of the startAdcbit again. As the startAdcbit is still 1, the ADC continues
its operation but without the need for the setup time. This behavior is shown in Figure 3.24 and Figure 3.25.
Figure 3.24 Continuous SRCS
startAdc
adcActive
ready
result
a
b
c
d
Setup Time and Single
Measurement
Single Measurement
Note that the ADC continues since startAdcis high at the end of the conversion sequence for a continuous
SRCS.
Figure 3.25 Continuous MRCS (Example for Result Counter of 3)
startAdc
adcActive
ready
result
a
b
c
d
e
f
g
Setup Time and Single
Measurement
Single Measurement
Note that the ADC continues since startAdcis high at the end of the conversion sequence for a continuous
MRCS.
When a continuous conversion sequence is performed that will be stopped after the present active conversion
sequence has completed, the user only needs to clear the startAdcbit of the channel that will be stopped.
Then the user can either wait for the next interrupt, which will be set by the last ready strobe, or check the
corresponding adcActivebit in the SSW.
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Figure 3.26 Stopping Continuous SRCS
startAdc
adcActive
ready
result
d
e
f
g
h
i
j
Single Measurement
Note that the ADC stops since startAdcis low at the end of the conversion sequence for a continuous SRCS.
When a conversion sequence is performed that will be interrupted (stopped immediately), the user must clear the
startAdc bit of the channel that will be stopped (when set) and must set the stopAdc bit in the adcCtrl
register to 1. In the ADC unit, the stopAdcbit is only evaluated when the startAdcbit of a channel is low and
the corresponding adcActivebit is high.
Figure 3.27 Stopping Continuous MRCS (Example for Result Counter of 3)
startAdc
adcActive
ready
result
b
c
d
e
f
g
h
i
Single Measurement
Note that the ADC stops since startAdcis low at the end of the conversion sequence for a continuous MRCS;
otherwise the stopAdc bit is ignored. Therefore there is only one stopAdc bit that is used for both channels.
This allows the user to stop both channels by clearing both startAdc bits when setting the stopAdc bit or to
stop only one channel by keeping one startAdcbit high.
The signal behavior for interrupting a channel is shown in Figure 3.28 and Figure 3.29.
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Figure 3.28 Interrupting a Continuous SRCS
startAdc
stopAdc
adcActive
ready
result
d
e
f
g
h
i
Single Measurement
Note that the ADC immediately stops since startAdcis low and stopAdc is high.
Figure 3.29 Interrupting a Continuous MRCS (Example for Result Counter of 3)
startAdc
stopAdc
adcActive
ready
result
b
c
d
e
f
g
Single Measurement
Note that the ADC immediately stops since startAdcis low and stopAdcis high.
Important: The stopAdcbit is only evaluated when startAdcbit is low.
Note: The interrupt sequence shown in Figure 3.28 and Figure 3.29 is also performed by the PMU on transition
from the FP State to any power-down state as well as on transition from any power-down state to the FP State.
This allows the user to keep the startAdc bits set on transition to any power-down state. After wake-up, the
ADCs continue the operation they performed before going to power-down.
Most of the register settings that influence both ADC channels (e.g., oversampling rate) can only be changed
when both ADC channels are inactive. As explained above, this is not true for the stopAdc bit. The adcMode
field can also be changed while any ADC channel is active. This is useful for continuing with current
measurements in the first ADC channel while changing the second ADC channel from voltage to temperature
measurements (as an example). On the rising edge of its startAdcbit, each ADC channel stores internally the
mode it is configured for and keeps this setting until the next rising edge of its startAdcbit. When one channel
is reconfigured while the other one is active, this channel does not start immediately after being re-enabled but
synchronizes to the active channel so that the results are generated at the same time. See Figure 3.30.
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Figure 3.30 Signal Behavior of adcMode
adcMode (Reg)
2
0
startAdcC
adcMode(Adc1)
adcActive1
ready1
0
SetupTime
+ 1 Meas
result1
1
2
3
4
5
6
7
8
2
9 0 1 2 3 4 5 6 7 8 9 0 1 2
startAdcV
adcMode(Adc2)
adcActive2
ready2
0
Sync + Setup
Time
Setup Time
+ 1 Meas
+ 1 Meas
result2
1
2
3
4
5
0 1 2 3 4 5 6 7 8 9 0
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3.8.4.2
Register “adcCtrl” – ADC Control Register
Table 3.58 Register adcCtrl
Name
Address
Bits
Default
Access
Description
startAdcC
[0]
0BIN
RW
Start signal for the current ADC; used in the FP
State, ignored in other states.
startAdcV
stopAdc
[1]
[2]
0BIN
0BIN
RW
RW
RW
Start signal for the voltage/temperature ADC;
used in the FP State, ignored in other states.
Stop signal for both ADCs; used in the FP State,
ignored in other states.
ADC multiplexer configuration; used in the FP
State, ignored in other states; for settings 0, 1, 2,
and 6, the first value is applied to the current
ADC, the second to the voltage/temperature ADC.
(See section 3.8.4.1 for more details.)
adcMode
[5:3] 000BIN
0
1
Measure current and voltage
Measure current and external
temperature
56HEX
2
Measure current and internal
temperature
3
4
Offset calibration
Gain calibration @ maximum (positive)
input
5
Gain calibration @ minimum (negative)
input
6
7
Internal test voltage and voltage
Test Mode (control multiplexer via the
adcChanregister’s cSeland vtSel
fields)
chopEna
Unused
[6]
[7]
0BIN
0BIN
RW
RO
If set to 1, Chopping Mode is enabled.
Unused; always write as 0.
3.8.4.3
ADC Operation in LP/ULP State
During the LP or ULP State, the ADCs are fully controlled by the PMU depending on the settings of register
pwrCfgLp (see Table 3.19). The PMU overrides the settings of the startAdc bits, the stopAdc bit, and
adcMode field. The settings of pwrAdcI and pwrAdcV are also ignored until the system wakes up. While no
further settings are required for the continuous measurement set-ups, the user can independently configure how
many current and/or voltage measurements happen within a single measurement window. For current (the green
and orange boxes In Figure 3.6 to Figure 3.9), the number of current measurements in each window is
configured by the setting of adcCrcl (see Table 3.37). For voltage (the orange boxes shown in Figure 3.6 to
Figure 3.9), the number of voltage measurements in each window is configured by the setting of adcVrcl(see
Table 3.39).There is always only one temperature measurement as the last measurement made by the
voltage/temperature ADC in a sample period.
Important: If an interrupt wakes up the system before the end of a measurement window, the conversion
sequence is interrupted and less than the configured number of measurements will have been completed. This
can be checked by the registers adcCrcv(see Table 3.38) and adcVrcv (see Table 3.40).
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3.8.4.4
ADC Conversion Timing
The complete conversion process is controlled by an internal state machine that guarantees that only valid
measurement results are used. The base for all ADC timings is the SDM clock, which is generated from the
4MHz clock in FP State or from the 125kHz clock in LP and ULP State. After the ADC measurement has been
started (rising edge of startAdc), the state machine always introduces a configurable number of SDM clock
cycles (field sdmSetupin register adcGomd; see Table 3.55) to allow the analog part of the SDM to settle. After
this delay, the incoming bit streams are used to fill the sinc4 decimation filter. This lasts 4 times the sample rate,
which is configured by the oversampling rate (the osrfield in register adcSamp; see Table 3.56). Then the first
valid result value comes from the decimation filter.
Figure 3.31 Timing for Current, Voltage, and Internal Temperature Measurements without Chopping for
Different Configurations of the Average Filter
sdmSetup
startAdc
Sample Rate tS
Time to Fill Filter: 4 * tS
Conversion
Result (no avg)
M(tN)
M(tN+1
)
M(tN+2
M(tN+1
M(tN)
)
M(tN+3
M(tN+2
M(tN+1
)
)
)
M(tN+4
M(tN+3
M(tN+2
)
)
)
M(tN+5
M(tN+4
M(tN+3
)
)
)
ready (no avg)
Time to Fill Filter: 5 * tS
Conversion
Result (2x avg)
M(tN)
)
ready (2x avg)
Time to Fill Filter: 6 * tS
Conversion
Result (3x avg)
ready (3x avg)
M = measurement; t = time.
For current, voltage, or internal temperature measurement without chopping, when only one input source must
be measured, this is the first valid value. The time when the first valid result is present also depends on the
configuration of the average filter (the avgFiltCfgfield in register adcSamp). If no averaging is used, the first
valid value is also the first valid result stored in adcCdat, adcVdat, or adcTdat. For the 2-stage or 3-stage
average filter, respectively, two or three valid values are needed to calculate a valid result. This adds an
additional delay, respectively, of 1 or 2 times the sample rate.
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For external temperature measurement without chopping, two input sources must be measured: the voltage drop
over the reference resistor (the result is stored in register adcRdat) and the voltage drop over the NTC resistor
(result stored in register adcTdat). The sdmSetup time is only introduced at the beginning of the conversion
sequence (the rising edge of startAdc). Each single measurement of one of the two values needs 4 times the
sample rate when averaging is disabled, or respectively, 5 or 6 times the sample rate when using the 2-stage or
3-stage average filter. This also means that a complete pair of values used to calculate one external temperature
value needs 8 (10 or 12 for averaging) times the sample rate because for each value, the pipeline of the sinc4
decimation filter must be filled first.
Figure 3.32 Timing for External Temperature Measurements without Chopping when No Average
Filter is Enabled
sdmSetup
startAdc
ref_not_ntc
conversion
result (no avg)
adcTdat
MNTC(tN)
MNTC(tN+1
)
MNTC(tN+2)
adcRdat
MREF(tN)
MREF(tN+1
)
MREF(tN+2)
ready (no avg)
M = measurement; t = time.
Note that using an average filter will lead, respectively, to 5 and 6 conversion results during each high and low
phase of ref_not_ntc.
The timings shown in the previous two figures are without chopping, which means that the differential input
signal is always applied in the same manner to the analog SD-ADC. Although this kind of measurement is fast
(one result value after each sample time), it has the drawback that it also converts any offset present in the
analog blocks. This would lead to less accurate measurement results. To overcome this, chopping can be
enabled (bit chopEna in register adcCtrl; see Table 3.58). When chopping is enabled, the differential input
signal is directly applied to the analog SD-ADC the first time and inverted the second time. Taking this into
account in the digital part removes the offset applied by the ADC itself:
(
+ offset) + (-1)∗(-
+ offset)
Vin
Vin
data =
=
(15)
Vin
2
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For current, voltage, or internal temperature measurement with Chopping Mode enabled (chopEnaset to 1), this
leads to a timing similar to the external temperature measurement without chopping and averaging since two
values are measured: the normal input and the inverted input. Each single measurement of one of the two values
needs 4 times the sample rate as no averaging of the single measurement is performed. Instead, the average
filter is automatically configured as a 2-stage average filter to calculate the formula above. The second difference
is that a small pause (chopping pause) is introduced each time the chop control signal changes to allow the
analog blocks to settle due to the input change. This is possible since the chopEna bit influences both ADC
paths. The length of the chop pause is either 8 or 16 SDM clock cycles, which can be configured using the
chopPausebit in register adcSamp.
Figure 3.33 Timing for Current, Voltage, and Internal Temperature Measurements using Chopping
Example shown is for current measurement:
sdmSetup
startAdc
chopPause
chopPause
chop ctrl
Conversion
Result (chop)
M+
M-
M+
M-
M+
M-
MCHP(tN) =
0.5*(M+-M-)
MCHP(tN+1) =
-0.5*(M--M+)
MCHP(tN+2) =
0.5*(M+-M-)
MCHP(tN+3) =
-0.5*(M--M+)
adcCdat
ready (chop)
M = measurement; t = time.
For external temperature measurement using chopping, two different input sources must be measured twice,
non-inverted and inverted, which leads to four values to be measured to determine a result. To keep both ADC
paths aligned, the chopPauseis introduced for each measured value.
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Figure 3.34 Timing for External Temperature Measurements using Chopping
sdmSetup
startAdc
ref_not_ntc
chop ctrl
chopPause
Conversion
Result (chop)
M+
M-NTC
M+
M-REF
M+
M-NTC
M+
REF
M-REF
NTC
REF
NTC
adcTdat
0.5*(M+NTC(tN) - M-NTC(tN))
0.5*(M+NTC(tN+1) - M-NTC(tN+1))
adcRdat
0.5*(M+REF(tN) - M-REF(tN))
ready (chop)
M = measurement; t = time.
Important: The timings only show the principle. Additional small delays such as pipeline delays are not included.
3.8.5 Diagnostic Features
3.8.5.1
ADC Analog Multiplexer Control for Diagnosis and Test
In the FP State, the three multiplexers shown in Figure 3.12 can be directly controlled via the register adcChan
(see Table 3.59) when the adcModefield in register adcCtrlis set to 7 (see Table 3.58). For other settings of
adcMode, the settings of register adcChanare ignored and both multiplexers for input selection are controlled
either by the adcModefield in the FP State or by the PMU in LP or ULP State.
The vtSel field in register adcChan is used to select the input sources of the voltage/temperature ADC. The
cSelfield in register adcChanis used to select the input sources of the current ADC.
Important: the reference voltage (non-inverted as well as inverted) cannot be measured by the current ADC as
the minimum gain of PGA-2 is 4, which causes an ADC over-range error.
For some settings of adcMode, cSel, and vtSel, the reference voltage is applied to the ADCs. The user can
select the source of the reference voltage with the vrefSelfield in register adcGomd(see Table 3.55). As can
be seen from Figure 3.12, the user’s software can connect internal current sources to the input wires of the INP
and INN pins as well as to the input wires of the NTH and NTL pins. To enable the different current sources for
the four input wires, the corresponding enable bit in register currentSrcEnamust be set to 1 (see Table 3.62).
Important Warning: Do not enable both current sources on the same input at the same time.
Important: The current sources can be enabled independent of the adcMode.
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3.8.5.2
Register “adcChan” – Analog Multiplexer Configuration
Table 3.59 Register adcChan
Name
Address
Bits
Default
Access
Description
vtSel
[2:0] 000BIN
RW
When adcMode == 7, this field selects the
differential sources for the voltage/temperature ADC:
vtSel
000BIN
001BIN
010BIN
011BIN
100BIN
101BIN
110BIN
111BIN
inp
VDDA
NTL
VPTAT
VBATP
VBGH (i.e., VREF
VBGL (i.e., VREFLP
VCM
inn
NTH
NTH
VBGH (i.e., VREF
VBATN
VSSA
VSSA
VCM
)
)
)
High impedance
High impedance
cSel
[5:3] 000BIN
RW
When adcMode== 7, this field selects the
D0HEX
differential sources for the current ADC:
000BIN
001BIN
010BIN
011BIN
100BIN
101BIN
110BIN
111BIN
INP
INP
INP
INP
1 mV
Unused
Unused
VCM
INN
INN
INN
INN
VSSA
VCM
Unused
Unused
[6]
[7]
0BIN
0BIN
RW
RW
Unused; always write as 0.
Unused; always write as 0.
3.8.6 Digital Features
3.8.6.1 Built-in Self-Test (BIST)
The digital ADC BIST feature allows the user to test the digital logic of the ADC data path. The BIST feature is
enabled by setting the bistEna bit in register adcDiag to 1 (see Table 3.61). When the BIST feature is
enabled, the same programmable bit stream is applied to both inputs of the decimation filter instead of the
outputs from the noise cancellation filters. The ADCs must also be set into operation as during normal operation.
The bit stream to be applied to the decimation filter is programmed to the lower 30 bits of register adcCaccTh
(see Table 3.44). These 30 bits function as a shift-rotate register as shown in Figure 3.35, and the output of the
lowest bit is used as the bit stream for the BIST.
Important: Since register adcCaccTh is used for the BIST, the current accumulator threshold functionality
cannot be used.
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Figure 3.35 Usage of Register adcCaccThfor the Digital ADC BIST
Bitstream
for BIST
. . .
X
X
1
0
1
0
1
0
1
0
29
28
27
26
3
2
1
0
Table 3.60 shows four example bit streams as well as the expected output stored in the corresponding data
registers adcCdat, adcVdat, adcTdat, and/or adcRdat if enabled. In these examples, the offset correction
value (e.g., register adcCoff) is set to 0, the gain correction value (e.g., register adcCgan) is set to 1.0, and the
post correction gain factor (e.g., bit field curPoCoGain [1:0] in register adcPoCoGain) is set to gain factor 1
(bit field set to 00BIN) and then to gain factor 2 (bit field set to 01BIN).
Table 3.60 Example Results of BIST
Result Data
Result Data
1/0
Bit
Bit Stream
(xPoCoGain = Gain Factor 1, (xPoCoGain = Gain Factor 2,
Ratio
Bit Field = 00BIN)
Bit Field = 01BIN)
100000_100000_100000_100000_100000
20820820HEX
111110_111110_111110_111110_111110
3EFBEFBEHEX
10010_10010_10010_10010_10010_10010
25294A52HEX
10110_10110_10110_10110_10110_10110
2D6B5AD6HEX
800000HEX
(negative over-range)
7FFFFFHEX
1/6
5/6
2/5
3/5
AAAAAAHEX
555555HEX
E66666HEX
199999HEX
(positive over-range)
CCCCCCHEX
333332HEX
3.8.6.2
Decimation Filter Output Test
The decimation filter output test allows the user to observe the outputs of both decimation filters. This feature is
enabled by setting bit rawEnain register adcDiagto 1. When this feature is enabled, the 32-bit output value of
the decimation filter for the current ADC is stored in registers adcCmax (MSBs; see Table 3.48) and adcCmin
(LSBs; see Table 3.49) and the 32-bit output value of the decimation filter for the voltage/temperature ADC is
stored in registers adcVmax(MSBs; see Table 3.50) and adcVmin(LSBs; see Table 3.51). The ADCs must also
be set into operation as during normal operation.
Note: When this feature is enabled, all normal ADC operations described in the previous sections function as
described except the minimum and maximum functionality for the current and voltage values because the
registers are used for this test function.
Note: This feature can be combined with the digital ADC BIST feature.
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3.8.6.3
ADC Interface Test
The ADC interface test allows the user to observe the incoming 2nd and 3rd order bit streams from both analog
parts of the SD-ADCs. This feature is enabled by setting bit adcIfTestEnain register adcDiagto 1. The digital
part of the ADC unit must be enabled as for normal operation as it generates the correct sample strobe for the
test logic. This function is only available in the FP State as it runs on the 20MHz clock from the high-precision
oscillator. All sampled values (4 bits) are shifted out of the STO pad. To enable the user to synchronize on the
sampled data, a 1 and a 0 are shifted out before each 4-bit value as shown in Figure 3.36.
Figure 3.36 Bit Stream of ADC Interface Test at STO Pad
2nd
I
3rd I 2nd V 3rd V
Note: This feature can be combined with the digital ADC BIST feature and with the decimation filter output test.
3.8.6.4
Register “adcDiag” – Enable Register for Test and Diagnosis Features
Table 3.61 Register adcDiag
Name
Address
Bits
Default
Access
Description
bistEna
rawEna
[0]
[1]
0BIN
0BIN
RW
RW
If set to 1, enables BIST.
If set to 1, enables the decimation filter output test
(ADC raw data test).
adcIfTestEna
Unused
stopClkChop
[2]
0BIN
RW
RW
RW
If set to 1, enables the serial ADC test.
Unused; always write as 0.
Disable signal for the global chopper (overall analog
and digital part chopping). Keep this bit ‘0’ in
application if chopping is required.
[5:3] 000BIN
[6]
D1HEX
0BIN
clkChopEna
[7]
1BIN
RW
Enable signal for internal chopper of the sigma-delta
modulator input stage. Keep this bit ‘0’ in application.
3.8.6.5
Register “currentSrcEna” – Enable Register for Current Source
Table 3.62 Register currentSrcEna
Name
Address
Bits
Default
Access
Description
inampInpSrcEna
Unused
inampInnSrcEna
Unused
[0]
[1]
[2]
[3]
[4]
0BIN
0BIN
0BIN
0BIN
0BIN
RW
RW
RW
RW
RW
Enable 50µA current source to INP.
Unused; always write as 0.
Enable 50µA current source to INN.
Unused; always write as 0.
psrcEnVbat
Enable 50µA current source on NTH.
D2HEX
psinkEnVbat
nsrcEnVbat
nsinkEnVbat
[5]
[6]
[7]
0BIN
0BIN
0BIN
RW
RW
RW
Enable -50µA current source on NTH.
Enable 50µA current source on NTL.
Enable -50µA current source on NTL.
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3.9 SBC LIN Support Logic (for ZSSC1750 only)
The ZSSC1750 LIN support logic handles two error conditions: a LIN dominant timeout on the TXD pin and a
short to VBAT on the LIN pin. Figure 3.37 illustrates the error protection logic discussed in the next sections.
Figure 3.37 Protection Logic of the LIN TXD Line
detLinShort
detTxdTimeout
O
R
FP state (PMU)
&
txdProtDis (register file)
TXD (from external MCU)
O
R
LIN-TXD
(LIN-PHY)
3.9.1 LIN Wakeup Detection
A LIN master generates a LIN wakeup frame by driving a dominant value of 0 of at least 250μs on the LIN bus.
The standard requires that a LIN slave must recognize a LIN wakeup when the LIN bus is low for more than
150μs.
There is a 6-bit counter running with the 125kHz LP clock implemented in the ZSSC1750 to support the LIN
wakeup detection. When the function is disabled (irqEn[4] is set to 0), the counter is set to 20HEX and no
interrupt can occur. When the function is enabled (irqEn[4] is set to 1), the LIN RXD line is observed. When
the LIN RXD line is high, the counter is set to 00HEX. When the LIN RXD line becomes low, the counter is
incremented in each clock cycle until it reaches the value 20HEX where it stops incrementing. When the counter is
equal to the programmed wakeup delay (register linWuDelay; see Table 3.66), a set strobe for the corres-
ponding interrupt is generated, which causes the system to wake up.
The register linWuDelay has a default value of 14HEX. This setting guarantees that no low level less than
150μs on the LIN RXD line causes a wakeup due to the inaccuracy of the LP oscillator.
3.9.2 TXD Timeout Detection
The digital LIN controller in the external microcontroller must ensure that it does not completely block the LIN bus
due to continuously transmitting a dominant value of 0. As it is still possible that the TXD line from the external
microcontroller is stuck at 0 due to a software or hardware error in the external microcontroller or a broken
connection between the external microcontroller and the ZSSC1750, the LIN support logic observes the TXD line
in FP State to detect if the TXD line is erroneously low. The timeout detection circuit can handle baud rates down
to 1kBaud, where the maximum time that a digital LIN controller (slave device!) can transmit a low level is 9ms
(start bit and 8 data bits). To overcome inaccuracies of the internal clocks, the internal logic and untrimmed LIN
nodes, the timeout value is 10.24ms.
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On detection of a TXD timeout, an internal flag (detTxdTimeoutin Figure 3.37) is set to the high level, which
forces the LIN TXD line to 1, and the corresponding interrupt status (irqStat[2]) is set. While the interrupt
status bit is cleared on read access to the interrupt status register, the internal flag remains high, also keeping
LIN TXD at the high level. The status of the internal flag is mirrored in SSW[2]. To clear this internal flag and to
be able to transmit again via the LIN bus, a value of 1 must be written to bit clrTxdTimeoutin register linCfg
(see Table 3.64).
3.9.3 LIN Short Detection
The LIN PHY contains a function to detect a short to VBAT on the LIN bus by sensing the current through the
open-drain output transistor in the LIN PHY. When the current is too high, the LIN PHY drives the SHORT signal
going to the digital block to the high level (see Figure 3.38). Under normal circumstances, the LIN PHY signals a
short only if a dominant value of 0 will be transmitted, but the bus remains at its recessive high level. However,
high current consumption is also possible due to EMC events. To increase the safety of the system and to avoid
misinterpretation, the incoming SHORT signal is gated and filtered.
First, the SHORT signal from the LIN PHY is driven through a configurable gating block inside the digital block.
The gating block is configured using register linShortDelay(see Table 3.65). If register linShortDelayis
set to a value not equal to 0, the TXD line going to and the RXD line coming from the LIN PHY are observed.
When the TXD line becomes low while the RXD line remains high, the gating block waits for linShortDelay
times 4MHz clock cycles before opening the gate. The gate is closed when either TXD becomes high again or
RXD becomes low (see Figure 3.38). This feature is used to evaluate the SHORT signal only when a dominant
value of 0 is transmitted, but the bus remains at its recessive high level as well as to eliminate the delay from the
TXD line through the LIN PHY back to the RXD line.
Figure 3.38 Waveform Showing the Gating Principle for Non-zero Values of linShortDelay
TXD
RXD
en gate
linShortDelay x 250ns
gated SHORT
When the register linShortDelayis set to 0, the gate for the SHORT signal is always open. This means that
the SHORT signal is always passed through the gating block even when the TXD line is high or the RXD line is
low.
The gated SHORT signal is applied to a configurable de-bouncing filter. This de-bouncing filter is configured
using register linShortFilter (see Table 3.64), and it monitors the gated SHORT signal using the internal
4MHz clock. When the gated SHORT signal is continuously high for (linShortFilter + 1) clock cycles, the
LIN short interrupt status bit (irqStat[3]) is set, enabling the user’s software running on the connected
external microcontroller to respond to this situation. The interrupt status bit is cleared on read access to the
interrupt status register.
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The software can also enable the hardware to protect the TXD line in the case of a detected short condition.
When the shortProtEnabit in register linCfg(see Table 3.63) is set to 1 and a short condition is detected by
the de-bouncing filter, an internal flag (detLinShortin Figure 3.37) is set to the high level, which forces the LIN
TXD line high. The status of the internal flag is mirrored in SSW[3]. The internal flag remains high until it is
explicitly cleared by the software by writing a value of 1 to the clrLinShortbit in register linCfg.
3.9.4 LIN Testing
The LIN TXD line protection features (TXD timeout, LIN short, LP State) might restrict the possibility of testing
the LIN PHY. Therefore the protection can be disabled by setting the txdProtDis bit in register linCfg to 1
(see Figure 3.37).
Important Warning: This must never be done during normal operation. The IC will not be damaged, but com-
munication errors will not be detected.
3.9.4.1
Register “linCfg” – LIN Configuration Register (ZSSC1750 Only)
Table 3.63 ZSSC1750 Register linCfg
Important: For the ZSSC1751 this register is not used and must remain as the default setting.
Name
Address
Bits
Default
Access
Description
linFastEna
[0]
0BIN
RW
When set to 1, the slew rate control in the LIN PHY
transmitter is disabled allowing higher LIN data rates
of up to 125kBaud (non-standard feature).
When set to 1, all protection features that force the
LIN TXD line to 1 are overwritten (for test purposes
only).
txdProtDis
[1]
0BIN
RW
shortProtEna
Unused
clrTxdTimeout
[2]
[3]
[4]
0BIN
0BIN
0BIN
RW
RO
RWS
If set to 1, enables the LIN short protection.
Unused; always write as 0.
Strobe register; write 1 to clear the detected TXD
timeout flag and to release the protection of the LIN
TXD line.
B4HEX
clrLinShort
Unused
[5]
0BIN
RWS
RO
Strobe register; write 1 to clear the detected LIN
SHORT flag and to release the protection of the LIN
TXD line.
[7:6]
00BIN
Unused; always write as 0.
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3.9.4.2
Register “linShortFilter” Configuration for the LIN Short De-bounce Filter (ZSSC1750 Only)
Table 3.64 ZSSC1750 Register linShortFilter
Important: For the ZSSC1751 this register is not used and must remain as the default setting.
Name
Address
Bits
Default
Access
Description
linShortFilter
B5HEX
[7:0]
0FHEX
RW
Filter configuration for the LIN short detector.
This register defines the number of 4MHz clock
cycles (linShortFilter+ 1) where the gated
LIN SHORT signal in the LIN PHY must be high to
detect a SHORT condition on the LIN bus.
3.9.4.3
Register “linShortDelay” –Configuration Register LIN Short TX-RX Delay (ZSSC1750 Only)
Table 3.65 ZSSC1750 Register linShortDelay
Important: For the ZSSC1751 this register is not used and must remain as the default setting.
Name
Address
Bits
Default
Access
Description
linShortDelay
B6HEX
[7:0]
4FHEX
RW
Delay configuration for gating the LIN SHORT
signal.
This register defines the number of 4MHz clock
cycles where TXD is low and RXD is high before
the gating logic of the LIN SHORT signal from the
LIN PHY is removed. When RXD becomes low or
TXD becomes high, the gating logic is reactivated.
Note: When linShortDelayis set to 0, the
TXD and RXD levels are ignored and the LIN
SHORT signal is not gated.
3.9.4.4
Register “linWuDelay” – Configuration Register for LIN Wakeup Time (ZSSC1750 Only)
Table 3.66 ZSSC1750 Register linWuDelay
Important: For the ZSSC1751 this register is not used and must remain as the default setting.
Name
Address
Bits
Default
Access
Description
linWuDelay
[4:0] 10100BIN
RW
LIN wakeup time.
This register defines the number of 125 kHz clock
cycles where LIN-RXD must be low before a LIN
wakeup conditions is detected.
B7HEX
Important Warning: Do not set to 0.
Unused
[7:5]
000BIN
RO
Unused; always write as 0
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3.10 ZSSC1750/51 OTP (CONFIG REGISTER)
The ZSSC1750/51 has an integrated 32x8 bit one-time programmable (OTP) memory that contains the required
trimming data as well as the traceability information. The default (erased) state of the OTP cells is 0. Because
some of the programmed trim bits are critical for operation, such as the voltage trim bits, redundancy is imple-
mented for the lower quarter of the OTP memory. This part of the OTP contains only up to four bits of information
that are programmed to bits [3:0] as well as to bits [7:4]. During the download procedure, the correct content is
determined by combining bit 0 and bit 4, bit 1 and bit 5, bit 2 and bit 6, and bit 3 and bit 7 via an OR gate.
Table 3.67 OTP Memory Map
OTP
SPI
Bit
Copy
Redun- Byte
Name
Description
Address Address
Range to Reg. dancy
Order
OTP_VALID
LIN_TRIM
VDD_TRIM
00HEX
01HEX
02HEX
E0HEX
E1HEX
E2HEX
0
3:0
3:0
No
Yes
Yes
Yes
Yes
Yes
---
---
[0]: OTP content valid
[3:0]: IBIAS_LIN_TRIM[3:0]
--- [0]: VDDC trim bit
[1]: VDDP trim bit
[3:2]: vbgh_trim[1:0]
BG_TRIM
IREF_OSC_0
IREF_OSC_1
03HEX
04HEX
05HEX
E3HEX
E4HEX
E5HEX
3:0
3:0
3:0
Yes
Yes
Yes
Yes
Yes
Yes
---
LSB
[3:0]: vbgh_trim[5:2]
[3:0]: IREF_OSC_TC_TRIM[3:0]
MSB [0]: IREF_OSC_TC_TRIM[4]
LSB [2]: IBIAS_LIN_TRIM[4]
[3]: IREF_OSC_TRIM[0]
IREF_OSC_2
IREF_OSC_3
IREF_LP_OSC
ADCCGAN_0
ADCCGAN_1
ADCCGAN_2
ADCCOFF_0
ADCCOFF_1
ADCCOFF_2
ADCVGAN_0
ADCVGAN_1
ADCVGAN_2
ADCVOFF_0
ADCVOFF_1
ADCVOFF_2
ADCTGAN_0
ADCTGAN_1
06HEX
07HEX
08HEX
09HEX
0AHEX
0BHEX
0CHEX
0DHEX
0EHEX
0FHEX
10HEX
11HEX
12HEX
13HEX
14HEX
15HEX
16HEX
E6HEX
E7HEX
E8HEX
E9HEX
EAHEX
EBHEX
ECHEX
EDHEX
EEHEX
EFHEX
F0HEX
F1HEX
F2HEX
F3HEX
F4HEX
F5HEX
F6HEX
3:0
3:0
6:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
---
MSB
---
LSB
---
MSB
LSB
---
MSB
LSB
---
MSB
LSB
---
MSB
LSB
MSB
[3:0]: IREF_OSC_TRIM[4:1]
[3:0]: IREF_OSC_TRIM[8:5]
Trim value for the low-power oscillator
Gain for the current measurement
Offset for the current measurement
Gain for the voltage measurement
Offset for the voltage measurement
Gain for the temperature
measurement
ADCTOFF_0
ADCTOFF_1
17HEX
18HEX
F7HEX
F8HEX
7:0
7:0
Yes
Yes
No
No
LSB
MSB
Offset for the temperature
measurement
---
19HEX
F9HEX
---
No
No
--- Unused
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OTP
SPI
Bit
Copy
Redun- Byte
Name
Description
Address Address
Range to Reg. dancy
Order
LOT_ID_0
LOT_ID_1
WAFER_NO_0
WAFER_NO_1
DIE_POS_0
DIE_POS_1
1AHEX
1BHEX
1CHEX
1DHEX
1EHEX
1FHEX
FAHEX
FBHEX
FCHEX
FDHEX
FEHEX
FFHEX
7:0
7:0
7:0
7:0
7:0
7:0
No
No
No
No
No
No
No
No
No
No
No
No
LSB
MSB
LSB
MSB
LSB
MSB
Lot ID number
Wafer number
Die position
After reset of the SBC, the OTP download procedure is automatically triggered. First, the OTP contents are
checked for validity (“bit 0 OR bit 4” must be equal to 1). If the content is not valid, the download procedure is
stopped. Otherwise, the information stored at OTP addresses 1 to 18HEX is copied into the corresponding
registers. The download procedure can also be started by the user by writing the value 1 into the otpDownload
bit in register cmdExe(see Table 3.7). Special care must be taken after starting the OTP download procedure as
the system must not go to the power-down state as long as the download procedure is active. The status of the
download procedure is signaled to the user via the SSW bit 0: the OTP download procedure is active when
SSW[0] = 1.
In addition to being read by triggering the OTP download procedure that copies the OTP contents into the
corresponding registers, the raw contents of the OTP can be read by the user via the SPI interface at SPI
addresses E0HEX to FFHEX. This might be useful for checking the contents of the OTP. For the lowest quarter of
the OTP, this is useful for checking that no bit has changed its value. The user might also choose to implement
redundancy for the other values by mirroring the contents into the nonvolatile memory on the external micro-
controller.
3.11 Miscellaneous Registers
3.11.1.1 Register “pullResEna” – Pull-down Resistor Control Register
CSN, SCLK, MOSI, TXD, TRSTN, TCK, TMS, and WDT_DIS each contain a configurable internal pull-down
resistor that is active by default. The pull-down resistors are present to prevent a floating input pin if the bonding
wire is broken and to enable the system to detect such a broken wire or broken connections with the external
microcontroller.
Example: If the bonding wire at TXD is broken, the pull-down resistor would drive TXD low continuously and the
LIN TXD timeout detector will trigger and inform the external microcontroller that an error is present.
Directly behind the input pins is a secondary protection stage because VDDP is disabled in some power-down
states. The ZSSC1750/51’s three SPI inputs, CSN, SCLK, and MOSI, as well as the TXD input, are only enabled
in FP State. The WDT_DIS input is enabled as long as MCU_RSTN is high (in the FP or LP State) while the
ZSSC1750/51’s three test inputs, TRSTN, TCK, and TMS, are only enabled when TEST is high.
Note: Because the TEST input pin also contains a pull-down resistor, disabling the pull-down resistors for the
three test input pins is safe as long as TEST is low.
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Table 3.68 Register pullResEna
Name
Address
Bits
Default
Access
Description
pullResEnaCsn
[0]
1BIN
RW
When set to 1, the pull-down resistor behind the
CSN pin is connected to the pin.
pullResEnaSpiClk
pullResEnaMosi
pullResEnaTxd
pullResEnaTrstn
pullResEnaTck
pullResEnaTms
pullResEnaWdtDis
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1BIN
1BIN
1BIN
1BIN
1BIN
1BIN
1BIN
RW
RW
RW
RW
RW
RW
RW
When set to 1, the pull-down resistor behind the
SCLK pin is connected to the pin.
When set to 1, the pull-down resistor behind the
MOSI pin is connected to the pin.
When set to 1, the pull-down resistor behind the
TXD pin is connected to the pin.
When set to 1, the pull-down resistor behind the
TRSTN pin is connected to the pin.
When set to 1, the pull-down resistor behind the
TCK pin is connected to the pin.
When set to 1, the pull-down resistor behind the
TMS pin is connected to the pin.
When set to 1, the pull-down resistor behind the
WDT_DIS pin is connected to the pin
B8HEX
3.11.1.2 Register “versionCode” – Version Code of SBC
The version code of the SBC is 200HEX
.
Table 3.69 Register versionCode
Name
Address
Bits
Default
Access
Description
versionCode[7:0]
versionCode[11:8]
Unused
BAHEX
[7:0]
[3:0]
[7:4]
00HEX
0010BIN
0000BIN
RO
RO
RO
Version code of the SBC.
BBHEX
Unused; always write as 0.
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3.11.1.3 Register “pwrTrim” – Trim Register for the Voltage Regulators and Bandgap
Table 3.70 Register pwrTrim
Name
Address
Bits Default
Access
Description
vddcTrim
[0]
0BIN
RW
Trim register for VDDC regulator:
0
1
VDDC is trimmed to 1.2V
VDDC is trimmed to 1.8V
Note: This register is set by the OTP download
procedure when the OTP content is valid.
Trim register for the VDDP regulator:
vddpTrim
vbghTrim
[1]
0BIN
RW
RW
C0HEX
0
1
VDDP is trimmed to 2.5V
VDDP is trimmed to 3.3V
Note: This register is set by the OTP download
procedure when the OTP content is valid.
Trim register for the high-precision bandgap.
Note: This register is set by the OTP download
procedure when OTP content is valid.
[7:2] 011111BIN
Important Warning: Changing the settings of bits vddcTrim and vddpTrim could cause damage to the
connected external microcontroller or cause it to malfunction!
3.11.1.4 Register “ibiasLinTrim” – Trim Register for the Bias Current of the LIN Block
Table 3.71 Register ibiasLinTrim
Name
Address
Bits
Default
Access
Description
ibiasLinTrim
[4:0] 10000BIN
RW
Trim register for the bias current of the LIN block:
0
1
Smallest value
Largest value
C3HEX
Note: This register is set by the OTP download
procedure when OTP contents are valid.
Unused; always write as 0.
Unused
[7:5]
000BIN
RO
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3.12 Voltage Regulators
In addition to the battery voltage (VBAT), four additional voltage domains are implemented in the ZSSC1750/51
as described in the following sections. The VDDA supply voltage for the analog sections is generated in the
VDDA_REG block and available on the VDDA pin. The VDDL voltage for the digital sections during the
ZSSC1750/51’s LP State is generated in the LP_REG block and output on the VDDL pin, and it can be used as
an optional low-power supply for the external microcontroller. The VDDP supply voltage for the SBC’s I/O circuits
is generated in the VDDP_REG block and output on the VDDP pin as an optional supply for the external
microcontroller. The VDDC supply voltage, an optional supply for the external microcontroller, is generated in the
VDDC_REG block and output on the VDDC pin. The regulators are low-dropout regulators (LDOs). The VDDL
regulator, which is active in the low-power states, has very low power consumption.
3.12.1 VDDE
The following blocks are connected directly to VDDE
:
•
•
•
•
•
•
•
•
Low-power bandgap
High-precision bandgap
High-precision oscillator
POR
Regulator for VDDA
Regulator for VDDL
Regulator for VDDC
Regulator for VDDP
3.12.2 VBAT
VBAT is the input for the battery voltage measurement using the voltage ADC. It is connected to a resistive
divider, dividing VBAT to a usable single-ended voltage for the voltage ADC (maximum 1.2V).
3.12.3 VDDA
The analog regulator provides a 2.5V output and can drive up to 10mA of load current. The output voltage is
continuously regulated with respect to the bandgap voltage (vbgh). A resistor chain generates the appropriate
voltage for the feedback comparison with the bandgap voltage so that the correct voltage is generated. This
internal regulated voltage serves as a supply voltage for the analog blocks. The analog regulator can be
switched off (e.g., in Sleep Mode).
The following blocks are connected directly to VDDA:
•
•
•
•
•
•
•
Level-Shifter
PGA
Divider
Temperature Measurement
SD-ADC Channel 1 (current)
SD-ADC Channel 2 (voltage and temperature)
All blocks necessary for data acquisition (current, voltage, and temperature measurements)
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3.12.4 VDDL
The VDDL regulator provides the supply voltage for the ZSSC1750/51’s digital domain. This regulator remains
active in ULP and OFF States. The following blocks are connected directly to VDDL:
•
•
•
•
LIN PHY control (ZSSC1750 only)
Power Management Unit
All ZSSC1750/51 registers
Watchdog timer
3.12.5 VDDP
The peripheral regulator provides 3.3V. The VDDP regulator can drive up to 40mA of load current and can be
switched off (e.g., in Sleep Mode). This voltage is recommended for the supply of the external microcontroller to
ensure matching I/O voltage levels as the I/O blocks of the ZSSC1750/51 are also connected directly to VDDP.
VDDP can be trimmed to the lower range given in specification 1.3.9 using the vddpTrimbit field in Table 3.70.
Important Warning: An improper vddpTrim setting could cause damage to the connected external
microcontroller or cause it to malfunction! See section 3.3.4 regarding VDDP trimming and the reset function.
3.12.6 VDDC
The core regulator provides 1.8V. This regulator can drive up to 40mA of load current and can be switched off
(e.g., in Sleep Mode).This voltage can be used for powering the core of an external microcontroller that requires
a lower core voltage than VDDP.
VDDC can be trimmed to the lower range given in specification 1.3.8 using the vddcTrimbit field in Table 3.70.
Important Warning: An improper vddcTrim setting could cause damage to the connected external
microcontroller or cause it to malfunction!
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4 ESD / EMC
The ZSSC175x is designed to maximize EM immunity and minimize emissions. (References to LIN
communication are only applicable to the ZSSC1750.)
Functional status A: According to specifications; no LIN communication errors; memory content must not be
lost; no wake-up from Sleep Mode; no reset.
Functional status B: According to specifications; offset error extended to < 100mA; no LIN communication
errors; memory content must not be lost; no wake-up from Sleep Mode; no reset.
Functional status C: Measurement tolerance beyond specifications; LIN communication errors allowed;
memory content must not be lost; reset allowed.
During EM exposure, all functions perform as designed; after exposure, all functions return automatically to
within normal limits; memory functions always remain in functional status A.
4.1 Electrostatic Discharge
Table 4.1 ESD Protection According to AEC-Q100 Rev. G
No.
Parameter
Condition
IEC 61000-4-2
Min
±6
Max
Unit
kV
kV
kV
V
4.1.1. ESD, LIN on system level 1)
4.1.2. ESD, BAT+ on system level 2)
4.1.3. ESD, HBM, all other pins
4.1.4. ESD, CDM, corner pins
4.1.5. ESD, CDM, all other pins
IEC 61000-4-2
AEC Q 100-002
AEC Q 100-011
AEC Q 100-011
±6
±2
±750
±500
V
1) For higher ESD levels additional diode is required (see Figure 4 1).
2) With external protection diode GSOT36 (see Figure 4.1).
4.2 Power System Ripple Factor
Component functionality meets these specifications.
UN = 13.5V
Voltage variation: sine wave
Amplitude GV = ±2V
Frequency range: 50Hz ≤ f ≤ 25kHz (linear sweep width for 10 minutes)
Ri of output stage ≤ 100mΩ
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4.3 Application Circuit Examples for EMC Conformance
The final application might require adaption of the external circuit for EMC compliance in the target system as
shown in Figure 4.1 and Figure 4.2.
Figure 4.1 Optional External Components for ZSSC1750
Ferrite Llin -
BLM21AG221SN1D
or
Cddl
10nF
Resistor Rlin - 20Ω
Cddc
2.2µF
Rbat
LIN
BAT+
Clin
220pF
Cbat
100nF
Cddp
2.2µF
100Ω
Dlin
GSOT36
Dbat
GSOT36
VBAT
VDDE
LIN
1
Ddde
Rdde Cdde1
Cdde2
100nF
VSSLIN
BAS21 2.2Ω
10µF
VSSE
VSSA
INP
TESTH
TESTL
.
n.c
n.c
.
Cinp
10nF
Chassis
Rinp
GND
wdt_dis
mcu_clk
WDT_DIS
MCU_CLK
220Ω
Rshunt
Cin
100nF
100µΩ
ZSSC1750
Rinn
INN
BAT-
220Ω
Cinn
10nF
VSSA
VDDA
STO
TCK
TMS
sto
tck
Cdda
Rref
75kΩ
470nF
NTH
NTL
tms
TRSTN
VSSN
Rntc
10kΩ
Cntc
470pF
trstn
RXD
rxd
txd mcu_rstn irqn csn
sclk mosi miso
Figure 4.2 Optional External Components for ZSSC1751
Cddl
10nF
Cddc
2.2µF
Rbat
BAT+
Cbat
100nF
Cddp
2.2µF
100Ω
Dbat
GSOT36
VBAT
VDDE
NC
VSS
1
Ddde
Rdde Cdde1
Cdde2
100nF
BAS21 2.2Ω
10µF
VSSE
VSSA
INP
TESTH
TESTL
.
n.c
n.c
.
Cinp
10nF
Chassis
Rinp
GND
wdt_dis
mcu_clk
WDT_DIS
MCU_CLK
220Ω
Rshunt
Cin
100nF
100µΩ
ZSSC1751
Rinn
INN
BAT-
220Ω
Cinn
10nF
VSSA
VDDA
STO
TCK
TMS
sto
tck
Cdda
Rref
75kΩ
470nF
NTH
NTL
tms
TRSTN
VSSN
Rntc
10kΩ
Cntc
470pF
trstn
NC
NC
VDDP
open
mcu_rstn irqn csn
sclk mosi miso
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ZSSC1750 / ZSSC1751 Datasheet
5 Pin Configuration and Package
Figure 5.1 ZSSC1750/51 PQFN36 6x6mm Package Pin-out (Top View)
ZSSC1750
ZSSC1751
36
34
32
30
35
33
31
29
28
36
34
32
30
35
33
31
29
28
1
2
3
4
5
6
7
8
27 VSSLIN
26 TESTH
25 TESTL
24 WDT_DIS
VDDE
VSSE
VSSA
INP
1
2
3
4
5
6
7
8
27 VSS
VDDE
VSSE
VSSA
INP
26 TESTH
25 TESTL
24 WDT_DIS
EXPOSED PAD
(pin 37)
EXPOSED PAD
(pin 37)
MCU_CLK
23
22
INN
VSSA
VDDA
MCU_CLK
23
22
INN
VSSA
VDDA
STO
STO
TCK
21
20
TCK
21
20
NTH
NTL
TMS
NTH
NTL
TMS
TRSTN
9
19
TRSTN
9
19
10
12
14
16
11
13
15
17
18
10
12
14
16
11
13
15
17
18
(1): See Table 5.1 for proper pin termination for no-connection (NC) pins.
Table 5.1 ZSSC1750/51 Pins Description
Note: See important notes at the end of the table.
Pin
1
Pin Name
VDDE
VSSE
VSSA
INP
Type
Supply
Supply
Supply
Analog
Analog
Supply
Analog
Analog
Analog
Digital
N/A
Mode
Input
Input
Input
Input
Input
Input
Output
Input
Input
Output
N/A
Description
Power supply
2
Power ground
3
Analog voltage ground
4
Positive input for current channel
Negative input for current channel
Analog voltage ground
5
INN
6
VSSA
VDDA
NTH
7
Analog voltage supply
8
Positive input for the temperature channel
Negative input for the temperature channel
LIN receiver output for ZSSC1750 only
Not used in ZSSC1751 – keep open
LIN transmitter input for ZSSC1750 only
9
NTL
RXD
10
11
NC
TXD 1)
Digital
Input
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ZSSC1750 / ZSSC1751 Datasheet
Pin
Pin Name
NC
Type
N/A
Mode
N/A
Description
Not used in ZSSC1751 – connect to VDDP
Reset for external microcontroller
Interrupt for external microcontroller
SPI chip select
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MCU_RSTN
IRQN
Digital
Digital
Digital
Digital
Digital
Digital
Supply
Digital
Digital
Digital
Digital
Digital
Digital
Analog
Analog
Supply
Supply
Analog
N/A
Output
Output
Input
CSN 1)
SCLK 1)
MOSI 1)
MISO
Input
SPI clock
Input
SPI Master output, Slave input
SPI master input, slave output
Digital voltage ground
Output
Input
VSSN
TRSTN 1), 2)
TMS 1), 2)
TCK 1), 2)
STO
Input
Test interface
Input
Test interface
Input
Test interface
Output
Output
Input
Test interface
MCU_CLK
WDT_DIS 1)
TESTL 2)
Clock signal to external microcontroller (20MHz)
Watchdog timer disable pin
Test interface
In/Out
In/Out
Input
2)
TESTH
Test interface
VSSLIN
VSS
LIN ground for ZSSC1750
Power ground for ZSSC1751
LIN bus for ZSSC1750
27
28
Input
LIN
In/Out
N/A
Not used in ZSSC1751 – keep open.
Power ground
NC
29
30
31
32
33
34
35
36
VSSR
VDDL
SLEEPN
TEST
VDDC
VDDP
VPP
Supply
Analog
Digital
Digital
Analog
Analog
Analog
Analog
Supply
Input
Output
Output
Input
SBC digital core supply
SBC power state indicator pin
Test interface enable; connect to ground in application
External microcontroller supply voltage (core)
External microcontroller supply voltage (periphery)
OTP programming voltage
Input for battery voltage monitor
Connect to VSSE in application
Output
Output
Input
VBAT
Input
EXPOSED
PAD
Input
37
1) Digital input with internal pull-down resistor. See parameter RPULL_DOWN in Table 1.3.
2) Connect to ground in application.
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ZSSC1750 / ZSSC1751 Datasheet
Figure 5.2 Package Drawing of the ZSSC1750/51
Dimensions
Min (mm)
(mm)
0.9
A
A1
b
0.8
0
0.05
0.3
0.2
E
0.5 nom
HD
HE
L
5.9
5.9
6.1
6.1
0.45
0.65
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ZSSC1750 / ZSSC1751 Datasheet
6 Ordering Information
Product Sales Code Description
Package
ZSSC1750EA3R
ZSSC1751EA3R
ZSSC1750 Battery Sensing SBC—Temperature Range: -40°C to 125°C PQFN36 6x6 mm, reel
ZSSC1751 Battery Sensing SBC—Temperature Range: -40°C to 125°C PQFN36 6x6 mm, reel
ZSSC1750KIT V1.1 ZSSC1750/51 Evaluation Kit: modular evaluation and development board for ZSSC1750/51, 3 IC
samples, and USB cable, (software and documentation can be downloaded from www.IDT.com)
7
Related Documents
Document
ZSSC1750/51 Feature Sheet
Application Notes
Technical Note – Die Pad Dimensions and Coordinates
Visit the ZSSC175x product pages at www.IDT.com or contact your nearest sales office for the latest version of
these documents.
8
Glossary
Term
ADC
BIST
DAP
ECC
FP
Description
Analog-to-Digital Converter
Built-In Self-Test
Debug Access Port
Error Correction Code
Full Power State
FSR
IFC
Full Scale Range
Current Interface
IFT
Temperature Interface
ITS
Internal Temperature Sensor
Local Interconnect Network
Low Power state
LIN
LP
LSB
MCU
MPX
MRCS
Least Significant Bit or Byte Depending on Context
Micro Controller Unit (external microcontroller)
Multiplexer
Multiple Results per Conversion Sequence
© 2016 Integrated Device Technology, Inc.
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ZSSC1750 / ZSSC1751 Datasheet
Term
MSB
NMI
Description
Most Significant Bit
Non-maskable Interrupt
Negative Temperature Coefficient
One-Time Programmable Memory
Preamplifier for Current
Preamplifier for Temperature
Programmable Gain Amplifier
Power-On-Reset
NTC
OTP
PA-C
PA-T
PGA
POR
PPB
PTAT
SBC
SDM
SPI
Private Peripheral Bus
Proportional to Absolute Temperature
System Basis Chip
Sigma Delta Modulator
System Packet Interface
Single Result per Conversion Sequence
Ultra Low Power State
SRCS
ULP
9 Document Revision History
Revision
Date
Description
1.00
July 10, 2014
April 20, 2016
First release.
Changed to IDT branding.
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance
specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose,
an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual
property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of
Integrated Device Technology, Inc. All rights reserved.
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