IW4081BD [IKSEMICON]
Quad 2-Input AND Gate High-Voltage Silicon-Gate CMOS; 四2输入与门高压硅栅CMOS
| 型号： | IW4081BD |
| 厂家： | 
IK SEMICON CO., LTD |
| 描述： | Quad 2-Input AND Gate High-Voltage Silicon-Gate CMOS |
| 文件： | 总5页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
IW4081B
Quad 2-Input AND Gate
High-Voltage Silicon-Gate CMOS
The IW4081B AND gates provide the system designer with direct
emplementation of the AND function.
•
•
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 μA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4081BN Plastic
IW4081BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Output
PIN 14 =VCC
PIN 7 = GND
A
L
B
L
Y
L
L
L
H
L
H
L
H
H
H
Rev. 00
IW4081B
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +20
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±10
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mW
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
PD
Tstg
TL
Power Dissipation per Output Transistor
Storage Temperature
100
-65 to +150
260
mW
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
°C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
3.0
0
Max
18
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
VIN, VOUT
TA
VCC
+125
V
-55
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
Rev. 00
IW4081B
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
≥-55°C
25°C
≤125
°C
Minimum High-Level VOUT=0.5V or VCC - 0.5V
Input Voltage
5.0
10
15
3.5
7
3.5
7
3.5
7
VOUT=1.0V or VCC - 1.0V
VOUT=1.5V or VCC - 1.5V
11
11
11
VIL
VOH
VOL
Maximum Low -
Level Input Voltage
VOUT=0.5V
VOUT=1.0V
VOUT=1.5V
5.0
10
15
1.5
3
4
1.5
3
4
1.5
3
4
V
V
V
Minimum High-Level VIN=VCC
Output Voltage
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95 14.95
4.95
9.95
Maximum Low-Level VIN=GND or VCC
Output Voltage
5.0
10
15
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
IIN
Maximum Input
Leakage Current
VIN= GND or VCC
VIN= GND or VCC
18
±0.1
±0.1
±1.0
μA
μA
ICC
Maximum Quiescent
Supply Current
(per Package)
5.0
10
15
20
0.25
0.5
1.0
0.25
0.5
1.0
7.5
15
30
5.0
5.0
150
IOL
Minimum Output
Low (Sink) Current
VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
mA
mA
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.36
0.9
2.4
UOL=1.5 V
IOH
Minimum Output
VIN= GND or VCC
High (Source) Current UOH=2.5 V
UOH=4.6 V
5.0
5.0
10
-2.0
-0.64
-1.6
-1.6
-0.51
-1.3
-1.15
-0.36
-0.9
UOH=9.5 V
UOH=13.5 V
15
-4.2
-3.4
-2.4
Rev. 00
IW4081B
AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ, Input tr=tf=20 ns)
VCC
V
Guaranteed Limit
Symbol
Parameter
Unit
ns
≥-55°C
25°C
≤125°C
tPLH, tPHL Maximum Propagation Delay, Input A or B to
Output Y (Figure 1)
5.0
10
15
250
120
90
250
120
90
500
240
180
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN
Maximum Input Capacitance
-
7.5
pF
Figure 1. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
Rev. 00
IW4081B
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
Dimension, mm
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
8
7
14
1
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
-T-
SEATING
PLANE
N
0
°
10
°
M
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
A
14
8
Symbol
MIN
8.55
3.8
MAX
8.75
4
A
B
C
D
F
H
B
P
1.35
0.33
0.4
1.75
0.51
1.27
1
7
G
R x 45
C
1.27
5.27
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0°
8°
0.25 (0.010) M
T
M
C
0.1
0.25
0.25
6.2
K
M
P
NOTES:
0.19
5.8
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
Rev. 00
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