1ED44171N01B [INFINEON]
EiceDRIVER™ 25 V single-channel low-side non-inverting gate driver IC for MOSFETs or IGBTs with typical 2.6 A source and sink currents in a tiny 5-lead PG-SOT23 package. 1ED44171N01B can also be used in conjunction with IPMs, such as IFCM10S60GD, which integrate a PFC IGBT but no PFC gate driver IC.;型号: | 1ED44171N01B |
厂家: | Infineon |
描述: | EiceDRIVER™ 25 V single-channel low-side non-inverting gate driver IC for MOSFETs or IGBTs with typical 2.6 A source and sink currents in a tiny 5-lead PG-SOT23 package. 1ED44171N01B can also be used in conjunction with IPMs, such as IFCM10S60GD, which integrate a PFC IGBT but no PFC gate driver IC. 驱动 双极性晶体管 功率因数校正 |
文件: | 总18页 (文件大小:1058K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1ED44171N01B
Single-channel low-side gate driver IC
Features
Potential applications
CMOS Schmitt-triggered inputs
Under voltage lockout
PFC stages
Home appliances
Air conditioner
Industrial applications
General purpose low-side gate driver for
single-ended topologies
Single pin for fault output and enable
Programmable fault clear time
3.3 V, 5 V and 15 V input logic compatible
25 V VCC voltage supply support (max)
Output in phase with input
-10 Vdc negative input capability of “IN” pin
3 kV ESD HBM
RoHS compliant
Description
The 1ED44171N01B is a low-voltage, power devices (such as: IGBT, MOSFET) non-inverting gate driver. Proprietary latch-up
immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS
or LSTTL output. The output driver features a current buffer stage. The 1ED44171N01B provides an under-voltage lockout
protection and has a FAULT status output (when activated, EN/FLT pin is internally pulled down). The EN/FLT needs to be
externally pulled up to provide normal operation, pulling EN/FLT low disables the driver. The under-voltage lockout
protection holds the output low until VCC supply voltage is within operating range.
Vbus+
AC
(Refer to lead assignments for correct
pin configuration). This diagram shows
electrical connections only. Please refer
VCC
Vdd
1
2
3
EN/FLT VCC
COM
5
4
to our application notes and design tips
for proper circuit board layout.
I/O2
Rg
µC
Vbus-
OUT
IN
I/O1
Gnd
Figure 1
Typical application
Ordering information
Product type
Package
Standard pack
Form
Orderable part number
Quantity
1ED44171N01B
PG-SOT23-5-1
Tape and Reel
3000
1ED44171N01BXTSA1
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC JESD47/22 and J-STD-020.
Datasheet
www.infineon.com/gdLowSide
Please read the Important Notice and Warnings at the end of this document
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Table of contents
Description 1
1
Block diagram........................................................................................................................ 3
2
2.1
2.2
Pin configuration and functionality.......................................................................................... 4
Pin configuration.....................................................................................................................................4
Input/output logic truth table ................................................................................................................5
3
Qualification information........................................................................................................ 6
4
Electrical parameters ............................................................................................................. 7
Absolute maximum ratings.....................................................................................................................7
Recommended operating conditions.....................................................................................................7
Static electrical characteristics...............................................................................................................8
Dynamic electrical characteristics..........................................................................................................8
4.1
4.2
4.3
4.4
5
Application information and additional details.......................................................................... 9
Low side gate driver ................................................................................................................................9
Switching and timing relationships........................................................................................................9
Input logic compatibility.......................................................................................................................10
Undervoltage lockout (VCC)..................................................................................................................10
Fault reporting and programmable fault clear timer ..........................................................................11
Enable input ..........................................................................................................................................11
5.1
5.2
5.3
5.4
5.5
5.6
6
7
8
9
Package outline: PG-SOT23-5-1 .............................................................................................13
Tape and reel details .............................................................................................................14
Part marking information ......................................................................................................15
Similar products ...................................................................................................................16
Revision history.............................................................................................................................17
Datasheet
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Single-channel low-side gate driver IC
1
Block diagram
Vcc
UVLO
UVLO &
Filter
5
1
VCC
4
2
OUT
EN/FLT
Logic
Control
Block
COM
QFLT
3
IN
Figure 2
Block diagram
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2
Pin configuration and functionality
2.1
Pin configuration
Table 1
Pin configuration
Pin no. Name
Function
Enable, fault reporting and fault clear time program pin, three functions:
1. Logic input to enable I/O functionality. I/O logic functions when ENABLE is high.
2. Fault reporting function with undervoltage lockout, this pin has negative logic and an
open-drain output.
EN/FLT
1
3. Fault clear time program with external resistor and capacitor.
COM
IN
Ground
2
3
4
5
Logic input for gate driver output (OUT), in phase
Gate drive output
OUT
VCC
Supply Voltage
1
2
3
5
4
EN/FLT VCC
COM
OUT
IN
Figure 3
PG-SOT23-5-1 (top view)
Datasheet
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2.2
Input/output logic truth table
Table 2
Input/output logic truth table
IN
L
H
UVLO1)
퐄퐍/퐅퐋퐓 2)
OUT
L
H
Note
OUT = L
OUT = H
H
H
H
H
OUT = L and EN/FLT= L (UVLO protection will disable
input signal and internally pull down EN/FLT pin.)
X
X
L
L
L
L
L
OUT = L (Externally pull down EN/FLT pin will disable I/O
logic until EN/FLT returns to high level.)
H
1) UVLO “L” state is under-voltage protection.
2) EN/FLT “H” state is EN/FLT pin externally pulling up and internally pull down MOSFET (QFLT) is off.
(See Block Diagram.)
Datasheet
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3
Qualification information
Industrial 1)
Comments: This family of ICs has passed JEDEC’s Industrial
qualification. Consumer qualification level is granted by
Qualification level
Moisture sensitivity level
ESD
extension of the higher Industrial level.
MSL1 2) 260°C
(per JEDEC standard J-STD-020)
1.5 kV
Charged device model
Human body model
(per ANSI/ESDA/JEDEC standard JS-002)
3 kV
(per ANSI/ESDA/JEDEC standard JS-001)
Class II, Level A
(per JESD78)
Yes
IC latch-up test
RoHS compliant
1)
Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon
sales representative for further information.
2)
Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales
representative for further information.
Datasheet
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4
Electrical parameters
4.1
Absolute maximum ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. The device may not
function or not be operable above the recommended operating conditions and stressing the parts to these levels is not
recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation
ratings are measured under board mounted and still air conditions.
Table 3
Absolute maximum ratings
Definition
Fixed supply voltage
Output voltage (OUT)
Symbol
VCC
VO
Min
– 0.3
- 0.3
– 0.3
– 10
—
Max
25
VCC + 0.3
VCC + 0.3
VCC + 0.3
0.5
Units
V
VEN/FLT
VIN
PD
RthJA
TJ
TS
Voltage at enable and fault reporting pin (EN/FLT)
Logic input voltage ( IN )
Package power dissipation @ TA ≤ 25°C
Thermal resistance, junction to ambient
Junction temperature
W
°C/W
PG-SOT23-5
—
191
150
150
260
– 40
– 55
—
Storage temperature
Lead temperature (soldering, 10 seconds)
°C
TL
4.2
Recommended operating conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to COM unless otherwise stated in the table.
Table 4
Recommended operating conditions
Definition
Symbol
VCC
Min
12.7
COM
0
– 5
– 40
Max
20
VCC
VCC
VCC
125
Units
Fixed supply voltage
VO
VEN/FLT
VIN
Output voltage
V
Voltage at enable and fault reporting pin (EN/FLT)
Logic input voltage ( IN )
Ambient temperature
TA
°C
Datasheet
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4.3
Static electrical characteristics
VCC = 15V, TA = 25°C unless otherwise specified. The VINL, VINH, VENL, VENH, and IIN, IFLT parameters are referenced to COM and are
applicable to input leads: IN and EN/FLT. The VO and IO parameters are referenced to COM and are applicable to the output lead:
OUT.
Table 5
Static electrical characteristics
Symbol Definition
Min
11.2
10.3
—
0.8
1.9
0.8
1.9
—
—
35
-10
—
2
Typ
11.9
11
Max
12.7
11.8
—
1.2
2.3
1.2
2.3
0.1
0.1
70
—
1200
—
—
—
Units Test Conditions
VCCUV+ VCC supply undervoltage positive going threshold
VCCUV- VCC supply undervoltage negative going threshold
VCCUVH VCC supply undervoltage lockout hysteresis
0.9
1.0
2.1
1.0
2.1
0.02
0.02
50
VINL
VINH
VENL
Logic “0” input voltage (OUT = LO)
Logic “1” input voltage (OUT = HI)
Logic “0” disable voltage
V
VENH Logic “1” enable voltage
VOH High level output voltage, VCC -VOUT
VOL Low level output voltage, VOUT
IO = 2 mA
IO = 2 mA
VIN = 5 V
IIN+
IIN-
IQCC
IO+
IO-
IFLT
Logic “1” input bias current IN pin
Logic “0” input bias current IN pin
Quiescent VCC supply current
Output sourcing short circuit pulsed current
Output sinking short circuit pulsed current
EN/FLT pull down sinking current
µA
- 6
VIN = 0 V
VIN = 0 V or 5 V
VO = 0 V, PW ≤ 2 µs
VO = 15 V, PW ≤ 2 µs
VEN/FLT = 0.4 V
VCC = open,
700
2.6
2.6
—
A
mA
V
2
18
VACTSD Active shut down voltage
—
2.0
2.3
IOUT-/IO- = 0.1
4.4
Dynamic electrical characteristics
VCC = 15 V, TA = 25°C, and CL = 1000 pF unless otherwise specified.
Table 6
Dynamic electrical characteristics
Symbol Definition
Min
—
—
Typ
50
50
5
Max
Units
ns
Test Conditions
ton
toff
tr
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
75
75
—
Figure 6
VIN pulse = 5 V
—
tf
Turn-off fall time
—
5
—
Figure 11
VEN pulse = 5 V
Figure 8
tDISA Disable propagation delay
tFLTC FAULT clear time
—
50
75
VCC = 3.3 V
80
103
2
130
µs
µs
RFLTC = 1MΩ to Vdd,
CFLTC = 150pF to COM
Figure 8
*
tvCCUV
—
—
VCC supply UVLO filter time
*Parameter verified by design, not tested in production.
Datasheet
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Single-channel low-side gate driver IC
5
Application information and additional details
Information regarding the following topics is included as subsections within this section of the datasheet.
•
•
•
•
•
•
Low side gate driver
Switching and timing relationships
Input logic compatibility
Undervoltage lockout protection
Fault reporting and programmable fault clear timer
Enable input
5.1
Low side gate driver
The 1ED44171N01B is designed to drive the gate of power devices (such as: IGBT, MOSFET). Figure 4 and Figure 5 illustrate
several parameters associated with the gate driver functionality of the driver. The output current of the driver, used to drive the
gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VOUT
.
Figure 4
Gate output sourcing current
Figure 5
Gate output sinking current
5.2
Switching and timing relationships
The relationships between the input and output signals of the 1ED44171N01B are illustrated below Figure 6. From the figure,
we can see the definitions of several timing parameters (i.e. ton, toff, tr, and tf) associated with this device.
50%
50%
IN
tf
ton
tr
toff
90%
90%
OUT
10%
10%
Figure 6
Switching time waveforms
Datasheet
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5.3
Input logic compatibility
The input of this IC is compatible with standard CMOS and TTL outputs. The 1ED44171N01B has been designed to be
compatible with 3.3 V, 5 V and 15 V logic-level signals. The input high threshold (VINH) is typ. 2.1 V and low threshold (VINL) is typ.
1 V. Input hysteresis offers enhanced noise immunity. The 1ED44171N01B includes an important feature: wherein, whenever
the input pin is in a floating condition, the output is held in the low state. This is achieved using GND pull-down resistors on the
input pin. Figure 7 illustrates an input signal to the 1ED44171N01B, its input threshold values, and the logic state of the IC as a
result of the input signal.
Figure 7
IN input thresholds
5.4
Undervoltage lockout (VCC)
The 1ED44171N01B has internal UVLO protection feature on the VCC pin supply circuit blocks. When VCC bias voltage keeps
lower than the VCCUV- threshold more than UVLO filter time (tVCCUV), the VCC UVLO feature holds the output low, regardless of the
status of the IN input.
At the same time, the internal MOSFET QFLT turns on and the EN/FLT pin is internally pulled down to COM. The EN/FLT output
stays in the low state until the UVLO has been removed; once the UVLO is removed, the internal MOSFET QFLT turns off, and the
voltage on the EN/FLT pin is charged up by external voltage Vdd.
And when VCC is higher than VCCUV+ and longer than fault clear time (tFLTC), the OUT still keeps low until next input signal IN is
high. (See Figure 8)
The filter time (tVCCUV) of about 2 μs helps to suppress noise from the UVLO circuit, so that negative going voltage spikes at the
supply pin will avoid parasitic UVLO events.
Vcc
VCCUV+
VCCUV-
IN
tVCCUV
OUT
tFLTC
QFLT off
EN/FLT
VENH
QFLT off
QFLT on
Figure 8
VCC under voltage protection waveform definitions
Datasheet
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5.5
Fault reporting and programmable fault clear timer
The 1ED44171N01B provides an integrated fault reporting output and an adjustable fault clear timer at the under voltage
condition of VCC. Once the under voltage of VCC occurs, the EN/FLT pin is internally pulled to COM. The EN/FLT output stays in
the low state until the fault condition has been removed and the internal pull down NMOS QFLT turns off, the voltage on the
EN/FLT pin is charged up with external pull-up voltage.
The length of the fault clear time period (tFLTC) is determined by exponential charging characteristics of the capacitor where the
time constant is set by RFLTC and CFLTC. Figure 9 shows that RFLTC is connected between the external supply (Vdd) and the EN/FLT
pin, while CFLTC is placed between the EN/FLT and COM pins. EN/FLT is weakly pulled up to 3.3 V reference voltage with 2.15 M
resistor internally. So the length of the fault clear time period can be determined by using the formula below (If Vdd = 3.3 V).
RFLTC x 2.15M
RFLTC + 2.15M
VENH
Vdd
tFLTC = -
x CFLTC x In(1-
)
)
(
Vbus+
AC
VCC
Vdd
RFLTC
CFLTC
1
2
3
EN/FLT VCC
5
I/O2
Rg
COM
IN
µC
Vbus-
OUT
4
I/O1
Gnd
Figure 9
1ED44171N01B in Boost application
5.6
Enable input
1ED44171N01B provides an enable functionality that allows to shutdown or to enable the output. When EN/FLT is pulled up
(the enable voltage is higher than VENH) the output is able to operate normally, pulling EN/FLT low (the enable voltage is lower
than VENL) the output is disable. The relationships between the input, output and enable signals of the 1ED44171N01B are
illustrated below in Figure 10~12. From these figures, we can see the definitions of several timing parameters and threshold
voltages (i.e. tDISA, VENH and VENL) associated with this device.
High
IN
IN
V
EN
50%
tDISA
OUT
EN/FLT
OUT
90%
Figure 10 Input/output/enable pins timing diagram Figure 11 EN pin switching time waveform
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Figure 12 EN input thresholds
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6
Package outline: PG-SOT23-5-1
Outline dimensions
Footprint dimensions
Figure 13 Package outline
Datasheet
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Tape and reel details
Figure 14 Tape and reel dimensions
Notes: For further details, please visit www.infineon.com/packages
Datasheet
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Part marking information
TOP MARKING
Figure 15 Part marking information
Datasheet
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Similar products
Channels Typ. gate
Part
Max
UVLO
Typ.
prop.
delay
Logic and features
Package
options
drive
(Io+/Io-)
number supply (on/off)
voltage
(on/off)
A
V
V
ns
Single non-inverting channel
Dual OUT pins
Single negative current sense
OCP, fault out and ENABLE
Single negative current sense
OCP, fault out and ENABLE
Single positive current sense
OCP, fault out and ENABLE
1.5 / 1.5 IRS44273L
25
10.2 / 9.2 50 / 50
8.0/7.3 34 / 34
SOT23-5L
SOT23-6-3
SOT23-6-3
PG-DSO-8
SOIC-8L
2.6/2.6
2.6/2.6
1ED44173
1ED44175
25
25
25
25
20
25
25
24
1
11.9/11.4 50 / 50
11.9/11.4 50 / 50
0.8/1.75 1ED44176
IRS4426S
50 / 50 Dual inverting channels
IRS44262S
2.3 / 3.3
10.2 / 9.2 50 / 50 Dual inverting channels
SOIC-8L
2
IRS4427S
50 / 50 Dual non-inverting channels SOIC-8L
Single inverting channel
IRS4428S
50 / 50
SOIC-8L
Single non-inverting channel
Dual non-inverting channels Power Pad
with ENABLE DSO-8
10/10
2ED24427
11.5/10
40 / 55
Datasheet
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Revision history
Document
version
1.0
Date of release
Description of changes
Jan. 17, 2022
Feb. 02, 2022
Datasheet
Final Datasheet
1.1
Datasheet
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Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
Edition 2022-02-02
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
Published by
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
In addition, any information given in this document
is subject to customer’s compliance with its
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applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Email: erratum@infineon.com
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of the
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Document reference
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
相关型号:
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