AUIRLR3636TRR [INFINEON]
Power Field-Effect Transistor, 50A I(D), 60V, 0.0083ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, ROHS COMPLIANT, PLASTIC, DPAK-3;型号: | AUIRLR3636TRR |
厂家: | Infineon |
描述: | Power Field-Effect Transistor, 50A I(D), 60V, 0.0083ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, ROHS COMPLIANT, PLASTIC, DPAK-3 |
文件: | 总12页 (文件大小:263K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
AUTOMOTIVEGRADE
AUIRLR3636
Features
HEXFET® Power MOSFET
l
l
l
l
l
l
l
l
l
Advanced Process Technology
D
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
ID (Package Limited)
60V
5.4m
6.8m
99A
Ultra Low On-Resistance
Logic Level Gate Drive
Advanced Process Technology
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
G
50A
D
Description
Specifically designed for Automotive applications, this HEXFET®
PowerMOSFETutilizesthelatestprocessingtechniquestoachieve
extremely low on-resistance per silicon area. Additional features of
thisdesign area175°Cjunctionoperatingtemperature,fastswitching
speed and improved repetitive avalanche rating . These features
combinetomakethisdesignanextremelyefficientandreliabledevice
foruseinAutomotiveapplicationsandawidevarietyofotherapplications.
S
G
D-Pak
AUIRLR3636
G
D
S
Gate
Drain
Source
Standard Pack
Form
Base Part Number
Package Type
Orderable Part Number
Quantity
75
2000
3000
3000
Tube
AUIRLR3636
AUIRLR3636TR
AUIRLR3636TRL
AUIRLR3636TRR
Tape and Reel
Tape and Reel Left
Tape and Reel Right
AUIRLR3636
D-pak
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; and
functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under
board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.
Symbol
ID @ TC = 25°C
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
Max.
99
Units
ID @ TC = 100°C
ID @ TC = 25°C
IDM
70
A
50
396
143
0.95
±16
170
PD @TC = 25°C
W
Maximum Power Dissipation
Linear Derating Factor
W/°C
V
VGS
EAS
IAR
Gate-to-Source Voltage
mJ
A
Single Pulse Avalanche Energy (Thermally Limited)
Avalanche Current
See Fig.14, 15, 22a, 22b
Repetitive Avalanche Energy
EAR
mJ
22
-55 to + 175
300
Peak Diode Recovery
dv/dt
TJ
V/ns
Operating Junction and
TSTG
°C
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Thermal Resistance
Symbol
Parameter
Typ.
–––
–––
–––
Max.
1.05
50
Units
RθJC
Junction-to-Case
RθJA
RθJA
Junction-to-Ambient (PCB Mount)
Junction-to-Ambient
°C/W
110
HEXFET® is a registered trademark of International Rectifier.
*Qualification standards can be found at http://www.irf.com/
1
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AUIRLR3636
Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
60 ––– –––
––– 0.07 ––– V/°C Reference to 25°C, ID = 5mA
Conditions
VGS = 0V, ID = 250μA
V
V
/ T
(BR)DSS Δ
Δ
Breakdown Voltage Temp. Coefficient
J
–––
–––
1.0
31
5.4
6.6
–––
6.8
8.3
2.5
VGS = 10V, ID = 50A
RDS(on)
Static Drain-to-Source On-Resistance
mΩ
V
GS = 4.5V, ID = 50A
VGS(th)
Gate Threshold Voltage
V
S
Ω
VDS = VGS, ID = 100μA
gfs
Forward Transconductance
––– –––
VDS = 25V, ID = 50A
RG(int)
IDSS
Internal Gate Resistance
Drain-to-Source Leakage Current
–––
0.6
–––
20
––– –––
VDS = 60V, VGS = 0V
μA
––– ––– 250
––– ––– 100
––– ––– -100
VDS = 60V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
V
GS = 16V
nA
VGS = -16V
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
Qg
Total Gate Charge
–––
–––
–––
–––
–––
33
11
15
18
45
49
ID = 50A
Qgs
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
VDS = 30V
VGS = 4.5V
nC
ns
Qgd
Qsync
ID = 50A, VDS =0V, VGS = 4.5V
VDD = 39V
td(on)
tr
––– 216 –––
ID = 50A
td(off)
Turn-Off Delay Time
Fall Time
–––
–––
43
69
–––
–––
RG = 7.5 Ω
VGS = 4.5V
tf
Ciss
Input Capacitance
––– 3779 –––
––– 332 –––
––– 163 –––
––– 437 –––
––– 636 –––
VGS = 0V
Coss
Output Capacitance
Reverse Transfer Capacitance
VDS = 50V
Crss
ƒ = 1.0MHz
pF
Coss eff. (ER)
Coss eff. (TR)
VGS = 0V, VDS = 0V to 48V ,See Fig.11
VGS = 0V, VDS = 0V to 48V
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
D
Continuous Source Current
MOSFET symbol
––– ––– 99
A
(Body Diode)
Pulsed Source Current
(Body Diode)
showing the
integral reverse
G
ISM
––– ––– 396
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
–––
–––
–––
V
TJ = 25°C, IS = 50A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 51V,
–––
–––
–––
–––
–––
27
32
31
43
2.1
ns
IF = 50A
di/dt = 100A/μs
Qrr
Reverse Recovery Charge
nC
A
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
ꢀ Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 50A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.136 mH
RG = 25Ω, IAS = 50A, VGS =10V. Part not recommended for use
above this value .
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniquea refer to applocation
note # AN- 994 echniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
.
.
ISD ≤ 50A, di/dt ≤ 1109 A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
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AUIRLR3636
1000
100
10
1000
100
10
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
TOP
TOP
BOTTOM
BOTTOM
2.7V
2.7V
60μs PULSE WIDTH
1
60μs PULSE WIDTH
Tj = 175°C
≤
≤
Tj = 25°C
1
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 50A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60μs PULSE WIDTH
0.1
1
2
3
4
5
6
7
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
5.0
100000
10000
1000
V
= 0V,
= C
f = 1 MHZ
GS
I = 50A
D
V
= 48V
C
C
C
+ C , C
SHORTED
ds
DS
VDS= 30V
= 12V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
iss
gs
gd
= C
rss
oss
gd
V
DS
= C + C
ds
gd
C
iss
C
oss
C
rss
100
0
5
10 15 20 25 30 35 40
Q , Total Gate Charge (nC)
1
10
, Drain-to-Source Voltage (V)
100
V
G
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
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AUIRLR3636
1000
100
10
1000
100
10
OPERATION IN THIS AREA LIMITED BY R (on)
DS
T
= 175°C
J
100μsec
T
= 25°C
LIMITED BY PACKAGE
J
1msec
10msec
1
1
DC
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
1.6
GS
0.1
0.1
0.1
1
10
100
0.1
0.4
V
0.7
1
1.3
1.9
V
, Drain-to-Source Voltage (V)
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
80
75
70
65
60
55
50
110
Id = 5mA
100
90
80
70
60
50
40
30
20
10
0
Limited By Package
-60 -40 -20 0 20 40 60 80 100120140160180
25
50
75
100
125
150
175
T
, Temperature ( °C )
T
, Case Temperature (°C)
J
C
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
0.8
800
I
D
5.69A
10.64A
700
600
500
400
300
200
100
0
TOP
0.6
0.4
0.2
0.0
BOTTOM 50A
0
5 10 15 20 25 30 35 40 45 50 55 60 65
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
V
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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AUIRLR3636
10
1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.1
0.02028
0.29406
0.49179
0.24336
0.000011
0.000158
0.001393
0.00725
τ
τ
J τJ
τ
Cτ
0.02
0.01
1τ1
Ci= τi/Ri
τ
τ
τ
2 τ2
3τ3
4τ4
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤj = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1.0% Duty Cycle
= 50A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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AUIRLR3636
3.0
2.5
2.0
1.5
1.0
0.5
0.0
14
12
10
8
I = 20A
F
V
= 51V
R
T = 25°C
J
T = 125°C
J
6
I
= 100μA
D
ID = 250μA
I
= 1.0mA
4
D
ID = 1.0A
2
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
400
600
800
1000
T
, Temperature ( °C )
di /dt (A/μs)
J
F
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
350
300
250
200
150
100
50
16
I
= 20A
= 51V
I = 30A
F
F
14
12
10
8
V
V
= 51V
R
R
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
6
4
2
0
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/μs)
di /dt (A/μs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
350
I
= 30A
= 51V
F
300
250
200
150
100
50
V
R
T = 25°C
J
T = 125°C
J
0
0
200
400
600
800
1000
di /dt (A/μs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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AUIRLR3636
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
•
dv/dt controlled by RG
• Driver same type as D.U.T.
RG
+
-
Body Diode
Inductor Current
Forward Drop
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2μF
12V
.3μF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
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AUIRLR3636
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
PartNumber
AULR3636
Date Code
Y= Year
WW= Work Week
A= Automotive, LeadFree
IR Logo
YWWA
XX or XX
Lot Code
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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AUIRLR3636
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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AUIRLR3636
Qualification Information†
Automotive
††
(per AEC-Q101)
Qualification Level
Comments: This part number(s) passed Automotive qualification.
IR’s Industrial and Consumer qualification level is granted by
extension of the higher Automotive level.
Moisture Sensitivity Level
D-PAK
MSL1
Class M4 (+/- 600V)†††
Machine Model
AEC-Q101-002
Class H1C (+/- 2000V)†††
AEC-Q101-001
Human Body Model
ESD
Class C5 (+/- 2000V)†††
AEC-Q101-005
Charged Device
Model
RoHS Compliant
Yes
Qualification standards can be found at International Rectifiers web site: http//www.irf.com/
Exceptions (if any) to AEC-Q101 requirements are noted in the qualification report.
Highest passing voltage.
10
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AUIRLR3636
IMPORTANTNOTICE
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make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to
discontinueanyproductorserviceswithoutnotice. Partnumbersdesignatedwiththe“AU”prefixfollowautomotiveindustryand /orcustomer
specific requirements with regards to product discontinuance and process change notification. All products are sold subject to IR’s terms
and conditions of sale supplied at the time of order acknowledgment.
IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR’s standard
warranty. Testing and other quality control techniques are used to the extent IR deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
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and agree that, if they use any non-designated products in automotive applications, IR will not be responsible for any failure to meet such
requirements.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel:(310)252-7105
11
www.irf.com © 2014 International Rectifier
Submit Datasheet Feedback
April 09, 2014
AUIRLR3636
Revision History
Date
Comments
•
•
•
•
Added "Logic Level Gate Drive" bullet in the features section on page 1
Updated data sheet with new IR corporate template
Updated package outline on page 8.
3/18/2014
4/9/2014
Updated typo on the fig.19 and fig.20, unit of y-axis from "A" to "nC" on page 6.
12
www.irf.com © 2014 International Rectifier
Submit Datasheet Feedback
April 09, 2014
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