BTS7050-2EPL_技术文档

BTS7050-2EPL

Datasheet

™

PROFET +2 12V

Smart high-side power switch

Features

• High-side switch with diagnosis and embedded protection

™

• Part of PROFET +2 12V family

• Switch ON capability while inverse current condition (InverseON)

• Capacitive load switching mode

• Green product (RoHS compliant)

Potential applications

• Replaces electromechanical relays, fuses and discrete circuits

• Protection of system supply

• Main switch for ECU power supply

• Suitable for driving resistive, inductive and capacitive loads

• Suitable for driving heating elements

Product validation

Qualified for automotive applications.

Product validation according to AEC-Q100, Grade 1.

Description

The BTS7050-2EPL is a Smart High Side Switch, providing protection functions and diagnosis capabilities. The device oﬀers

current limitation and has a capacitive load switching mode implemented to charge capacitors. It is integrated in SMART7

technology.

V_BAT

Z_WIRE

Optional

Logic Supply

C_VS

C_VSGND

T1

R_GND

GND

VS

OUT0

VDD

GPIO

R_IN

IN0

IN1

C_OUT

C_VS2

D_Z2

R_DEN

R_DSEL

DEN

DSEL

Optional

OUT1

ADC

R_ADC

R_{IS_PROT}

IS

C_OUT

VSS

C_SENSE

Optional

Logic GND

Power GND

Chassis GND

Further information in Chapter 9

Datasheet

www.infineon.com

Please read the sections "Important notice" and "Warnings" at the end of this document

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

Description

Parameter

Symbol

V_S(OP)

Values

3 V

Minimum operating voltage

Minimum operating voltage (cranking)

Maximum operating voltage

V_S(UV)

2.7 V

V_S

28 V

Minimum overvoltage protection (T_J≥ 25°C)

Maximum current in sleep mode (T_J≤ 85°C)

Maximum operative current

V_{DS(CLAMP)_25}

I_{VS(SLEEP)_85}

I_GND(ACTIVE)

R_{DS(ON)_25}

R_{DS(ON)_150}

I_L(NOM)

35 V

0.5 µA

4.5 mA

50 mΩ

100 mΩ

3 A

Typical ON-state resistance (T_J= 25°C)

Maximum ON-state resistance (T_J= 150°C)

Nominal load current (T_A= 85°C)

Typical current sense ratio at I_L= I_L(NOM)

Overcurrent limitation

k_ILIS

2030

I_LIM

9.48 A

Diagnostic features

• Proportional load current sense

• Open load in ON and OFF state

• Short circuit to ground and battery

Protection features

• Absolute and dynamic temperature protection with restart control

• Overcurrent limitation

• Overvoltage protection

Type

Package

Marking

BTS7050-2EPL

PG-TSDSO-14

7050-2AL

Datasheet

2

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

Table of contents

Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1

1.1

1.2

Block diagram and terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2

2.1

2.2

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3

3.1

3.2

3.3

3.3.1

3.3.2

General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

PCB setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4

4.1

4.1.1

4.1.2

4.2

I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Digital I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Diagnosis pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Electrical characteristics I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5

5.1

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Operation modes and transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Unsupplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Inactive with diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Active with diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Active without diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Capacitive load switching mode with diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Capacitive load switching mode without diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Electrical characteristics power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.1.1

5.1.1.1

5.1.1.2

5.1.1.3

5.1.1.4

5.1.1.5

5.1.1.6

5.1.1.7

5.1.1.8

5.2

5.3

6

6.1

6.2

6.2.1

6.2.2

6.2.3

6.3

Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output ON-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Switching resistive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Switching inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Switching capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Advanced switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Datasheet

3

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

Table of contents

6.3.1

6.4

Inverse current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Electrical characteristics power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7

7.1

7.1.1

7.2

7.3

Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Overcurrent threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Protection and diagnosis in case of fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Retry strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Additional protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Loss of battery and loss of load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Electrical characteristics protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.3.1

7.4

7.4.1

7.4.2

7.4.3

7.4.4

7.5

8

8.1

Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SENSE signal truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Current sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Fault current (IIS(FAULT)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Diagnosis in OFF State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Open load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

SENSE timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Electrical characteristics diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.1.1

8.2

8.2.1

8.2.2

8.3

8.3.1

8.4

8.5

9

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

10

11

Datasheet

4

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

1 Block diagram and terms

1

Block diagram and terms

1.1

Block diagram

VS

Channel0

Channel1

Supply voltage

monitoring

Voltage sensor

Overvoltage

protection

Voltage sensor

T

Overtemperature

Overvoltage

T

Overtemperature

Gate control

Internal power

supply

clamping

Overvoltage

clamping

+

Gate control

Chargepump

+

Overcurrent

Driver

Chargepump

Idle state

Restart control

SENSE output

limitation

Overcurrent

logic

limitation

Capacitive load

ReverseON

IS

switching

InverseON

OUT0

OUT1

Capacitive load

InverseON

switching

Undervoltage lockout

IN0

IN1

Load current sense

ESD protection

DEN

DSEL

+

I/O

Reverse polarity

protection and

GND circutry

GND

Figure 2

Block diagram of BTS7050-2EPL

Datasheet

5

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

1 Block diagram and terms

1.2

Terms

Figure 3 shows all terms used in this data sheet, with associated convention for positive values.

I_VS

V_DSn

I_INn

V_SIS

VS

INn

DEN

DSEL

IS

I_DEN

V_DEN

V_INn

I_Ln

V_S

I_DSEL

OUTn

I_IS

V_DSEL

GND

V_IS

V_OUTn

I_GND

Figure 3

Voltage and current convention

Datasheet

6

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

2 Pin configuration

2

Pin configuration

2.1

Pin assignment

GND

IN0

1

2

3

4

5

6

7

14

13

12

11

10

9

OUT0

n.c.

DEN

IS

VS

DSEL

IN1

OUT1

exposed pad

(bottom)

n.c.

8

Figure 4

Pin configuration

2.2

Pin definitions and functions

Table 1

Pin definition

Symbol

Function

EP

VS (exposed

pad)

Supply Voltage

Battery voltage

1

GND

Ground

Ground connection for the internal logic

2, 6

INn

Input Channel n

Digital signal to switch ON channel n ("high" active)

If not used: Connect with a 10kΩ resistor either to GND pin or to module ground

3

DEN

Diagnostic Enable

Digital signal to enable device diagnosis ("high" active) and to clear the protection

counter of channel selected with DSEL pin.

If not used: Connect with a 10kΩ resistor either to GND pin or to module ground

4

IS

SENSE current output

Analog/digital signal for diagnosis

If not used: Lef open

5

DSEL

Diagnosis Selection

Digital signal to toggle between the channels.

If not used: Connect with a 10kΩ resistor either to GND pin or to module ground

7, 11

n.c.

Not connected, internally not bonded

8-10,

12-14

OUTn

Output n

Protected high-side power output channel n ¹⁾

1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally

connected together. PCB traces have to be designed to withstand the maximum current which can flow.

Datasheet

7

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

3 General product characteristics

3

General product characteristics

Absolute maximum ratings

3.1

T_J= -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin

(unless otherwise specified)

Table 2

Absolute maximum ratings

Parameter

Symbol

Min.

Values

Typ.

Unit

Note or condition

P-

Number

Max.

Supply pins

2)

Power supply voltage V_S

-0.3

–

28

V

PRQ-34

PRQ-36

-

2)

Load dump voltage

V_BAT(LD)

–

35

suppressed load dump

acc. to ISO16750-2

(2010). R_i= 2 Ω

2)

Supply voltage for

V_BAT(SC)

0

–

24

16

V

PRQ-38

PRQ-40

short circuit protection

Setup acc. to AEC-

Q100-012

2)

Reverse polarity

voltage

-V_BAT(REV)

t ≤ 2min

T_A= +25°C

Setup as described

in Chapter 9

2)

Current through GND

I_GND

-50

–

50

mA

PRQ-44

R_GNDaccording

to Chapter 9

Logic & control pins (Digital Input = DI)

DI = INn, DEN, DSEL

2) 1)

Current through DI pin I_DI

-1

–

2

mA

PRQ-47

PRQ-48

2) 1)

Current through DI

pin - Reverse battery

condition

I_DI(REV)

10

t ≤ 2 min

IS pin

2)

Voltage at IS pin

V_IS

-1.5

-25

–

V_S

V

PRQ-50

PRQ-52

I_IS= 10 μA

2)

Current through IS Pin I_IS

I_IS(SAT),MmA

AX

-

Temperatures

2)

Junction temperature T_J

-40

–

+150

°C

PRQ-53

-

(table continues...)

Datasheet

8

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

3 General product characteristics

Table 2

(continued) Absolute maximum ratings

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

-55

Max.

+150

2)

Storage temperature

T_STG

–

°C

PRQ-54

-

ESD susceptibility

2)

ESD Susceptibility all

pins (HBM)

V_ESD(HBM)

-2

-4

–

2

4

kV

PRQ-55

PRQ-56

HBM³⁾

2)

ESD Susceptibility

OUTn vs GND and VS

connected (HBM)

V_{ESD(HBM)_OUT}

HBM³⁾

2)

ESD Susceptibility all

pins (CDM)

V_ESD(CDM)

-500

-750

–

500

750

V

PRQ-57

PRQ-58

CDM⁴⁾

2)

ESD Susceptibility

corner pins (CDM) -

(pins 1, 7, 8, 14)

V_{ESD(CDM)_CRN}

CDM⁴⁾

Power stage

2)

Maximum energy

dissipation - single

pulse

E_AS

–

12

mJ

PRQ-615

PRQ-616

I_L= 2⋅I_L(NOM)

T_J(0)= 150°C

V_S= 28 V

2)

Maximum energy

dissipation - repetitive

pulse

E_AR

2.5

I_L= I_L(NOM)

T_J(0)= 85°C

V_S= 13.5 V

1M cycles

2)

Load current

|I_L|

–

I_LIM,MAX

A

PRQ-617

–

1)

2)

3)

4)

Maximum V_DIto be considered for Latch-Up tests: 5.5 V

Not subject to production test - specified by design

ESD susceptibility, Human Body Model “HBM”, according to AEC Q100-002

ESD susceptibility, Charged Device Model “CDM”, according to AEC Q100-011

Notes

1.

Stresses above the ones listed here may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods may aﬀect device reliability.

2.

Integrated protection functions are designed to prevent IC destruction under fault conditions described in

the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions

are not designed for continuous repetitive operation.

Datasheet

9

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

3 General product characteristics

3.2

Functional range

Table 3

Parameter

Functional range

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

Max.

20

1)

Supply voltage range

for normal operation

V_S(NOR)

4

13.5

V

PRQ-66

–

1)

2)

3)

Lower extended supply V_S(EXT,LOW)

voltage range for

operation (normal)

2.7

–

4

PRQ-67

(parameter deviations

possible)

1)

Upper extended supply V_S(EXT,UP)

voltage range for

20

–

28

V

PRQ-68

PRQ-69

3)

operation

(parameter deviations

possible)

1)

Junction temperature T_J

-40

+150

°C

–

1)

2)

Not subject to production test - specified by design

In case of V_Svoltage decreasing refer to the maximum voltage of V_S(UV), in case of V_Svoltage increasing refer to the maximum voltage of

V_S(OP)

3)

Protection functions still operative

Note

Within the functional or operating range, the IC operates as described in the circuit description. The electrical

characteristics are specified by the conditions given in the Electrical Characteristics tables.

3.3

Thermal resistance

Symbol

Table 4

Parameter

Values

Typ.

Unit

Note or condition

P-

Number

Min.

Max.

7.5

1)

2)

Thermal

Ψ

–

4.4

K/W

PRQ-623

PRQ-624

JTOP

characterization

parameter junction-top

1)

2)

Thermal resistance

junction-to-case

R_thJC

5.1

8.6

–

K/W

simulated at exposed

pad

1)

Thermal resistance

junction-to-ambient

R_thJA

–

33.5

PRQ-625

2)

1)

Not subject to production test - specified by design

Datasheet

10

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

3 General product characteristics

2)

According to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was simulated on a 76.2 ×

114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed

pad contacted the first inner copper layer. Simulation done at T_A= 105°C, P_DISSIPATION= 1 W

Note

This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to

www.jedec.org.

3.3.1

PCB setup

70 µm modeled (traces, cooling area)

70 µm, 5% metalization*

*: means percentual Cu metalization on each layer

Figure 5

Figure 6

1s0p PCB cross section

70 µm modeled (traces)

35 µm, 90% metalization*

70 µm, 5% metalization*

0.25mm ≤ A ≤ 0.5 mm

*: means percentual Cu metalization on each layer

2s2p PCB cross section

PCB 1s0p + 600 mm² cooling

PCB 2s2p / 1s0p footprint

Figure 7

PCB setup for thermal simulations

Datasheet

11

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

3 General product characteristics

Figure 8

Thermal vias on PCB for 2s2p PCB setup

3.3.2

Thermal impedance

BTS7050-2EPL

100

10

1

2s2p

1s0p - 600 mm²

1s0p - 300 mm²

1s0p - footprint

0.1

0.0001

0.001

0.01

0.1

1

10

100

1000

Time (s)

Figure 9

Typical thermal impedance. PCB setup according to PCB setup

Datasheet

12

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

3 General product characteristics

BTS7050-2EPL

130

120

110

100

90

1s0p - Ta = 105°C

80

70

60

50

40

30

0

100

200

300

400

500

600

Cooling area (mm²)

Figure 10

Thermal resistance on 1s0p PCB with various cooling surfaces

Datasheet

13

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

4 I/O pins

4

I/O pins

The device has four digital pins for direct control.

4.1

Digital I/O pins

Digital input (DI) pins = INn, DEN, DSEL

4.1.1

Input pins

The input pins IN0 and IN1 activate the corresponding output channel. The input circuitry is compatible with 3.3 V

and 5 V microcontroller. The electrical equivalent of the input circuitry is shown in Figure 11. In case a pin is not used,

it must be connected by a 10 kΩ resistor either to GND pin or to module ground.

VS

DI

V_S(CLAMP)

I_DI

ESD

V_DI(CLAMP)

V_DI

GND

I_GND

Figure 11

Input circuitry

The logic thresholds for “low” and “high” states are defined by parameters V_DI(TH)and V_DI(HYS). The

relationship between these two values is shown in Figure 12.

V_DI

V_DI(TH),MAX

V_DI(TH)

V_DI(HYS)

V_DI(TH),MIN

t

Internal channel

activation signal

0

x

1

x

0

Figure 12

Input threshold voltages and hysteresis

Datasheet

14

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

4 I/O pins

4.1.2

Diagnosis pins

The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and the protection circuitry. When DEN pin is set to

“high”, the diagnosis is enabled (see Chapter 8.2 for more details). When it is set to “low”, the diagnosis is disabled

(IS pin is set to high impedance). The Diagnosis Selection (DSEL) pin selects the channel where the diagnosis is

performed (see Table 12). See Figure 12 for more details.

The transition from “high” to “low” of DEN pin clears the protection latch of the channel selected with DSEL pin

depending on the logic state of IN pin and DEN pulse length (see Chapter 7.3 for more details).

4.2

Electrical characteristics I/O pins

V_S= 4 V to 20 V, T_J= -40°C to +150°C

Unless otherwise specified typical values: V_S= 13.5 V, T_J= 25°C

Digital input (DI) pins = INn, DEN, DSEL

Table 5

Electrical characteristics I/O pins

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

Max.

DI pins

Digital input voltage

threshold

V_DI(TH)

0.8

1.3

2

–

V

See Figure 11 and

Figure 12

PRQ-76

PRQ-77

1)

Digital input clamping V_DI(CLAMP1)

voltage

–

7

I_DI= 1 mA

See Figure 11 and

Figure 12

Digital input clamping V_DI(CLAMP2)

6.5

–

7.5

0.25

10

8.5

–

V

I_DI= 2 mA

See Figure

11 and Figure 12

1)

PRQ-78

PRQ-80

PRQ-81

PRQ-82

voltage

Digital input hysteresis V_DI(HYS)

V

See Figure 11 and

Figure 12

Digital input current

("high")

I_DI(H)

2

25

µA

V_DI= 2 V

See Figure 11 and

Figure 12

Digital input current

("low")

I_DI(L)

2

10

V_DI= 0.8 V

See Figure 11 and

Figure 12

1)

Not subject to production test - specified by design

Datasheet

15

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

5 Power Supply

5

Power Supply

The device is supplied by VS, which is used to supply the internal logic as well as to supply the power output stages.

In case of an undervoltage condition, the device has an detection circuit, which prevents the activation of the power

output stage as well as the diagnosis.

5.1

Operation modes and transitions

Operation modes

5.1.1

The device has the following operation modes:

•

Sleep

Inactive with diagnosis

Active with diagnosis

Active without diagnosis

Capacitive load switching mode with diagnosis

Capacitive load switching mode without diagnosis

The transition between operation modes is determined according to these variables:

•

Logic level at INn pins

PWM signal at INn pins

Logic level at DEN pin

The state diagram including the possible transitions is shown in Figure 13. The behavior of the device as well as some

parameters may change independent from the operation mode of the device. Furthermore, due to the undervoltage

detection circuitry which monitors V_Ssupply voltage, some changes within the same operation mode can be seen

accordingly.

Table 6 shows the correlation between operation modes, V_Ssupply voltage, and the state of the most important

functions (channel status).

INn=“low“ & DEN=“low“

INn=“f_VIN(CLS)“ & DEN=“high“

Power-up

Unsupplied

INn=“f_VIN(CLS)“ & DEN=“high“

INn=“low“ & DEN=“high“

INn=“low“ & DEN=“low“

Inactive with Diag

Sleep

INn=“low“ & DEN=“high“

INn=“f_VIN(CLS)“ & DEN=“low“

INn=“high“ & DEN=“high“

INn=“low“ & DEN=“low“

INn=“high“ &

DEN=“high“

INn=“low“ &

DEN=“high“

INn=“low“ &

DEN=“low“

INn=“high“ &

DEN=“low“

INn=“f_VIN(CLS)“ &

INn=“high“ &

INn=“high“ & DEN=“high“

INn=“high“ & DEN=“low“

DEN=“high“

DEN=“low“

Capacitive Load

Switching with Diag

Capacitive Load

Switching without Diag

Active with Diag

Active without Diag

INn=“high“ &

DEN=“high“

INn=“f_VIN(CLS)“ &

DEN=“low“

INn=“f_VIN(CLS)“ & DEN=“high“

INn=“f_VIN(CLS)“ & DEN=“low“

Figure 13

Table 6

Operation mode state diagram

Operation mode, device function and VS voltage

Operation mode

Function

Channels

Diagnosis

V_S> V_S(OP)

V_S< V_S(OP)

OFF

Sleep

OFF

(table continues...)

Datasheet

16

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

5 Power Supply

Table 6

(continued) Operation mode, device function and VS voltage

Operation mode

Function

Channels

Diagnosis

Channels

Diagnosis

Channels

Diagnosis

Channels

Diagnosis

Channels

Diagnosis

V_S> V_S(OP)

V_S< V_S(OP)

OFF

Inactive with diagnosis

OFF

ON

OFF

ON

OFF

Active with diagnosis

OFF

Active without diagnosis

OFF

Capacitive load switching mode with

diagnosis

OFF

Capacitive load switching mode without

diagnosis

OFF

5.1.1.1

Unsupplied

In this state the device supply voltage is below the undervoltage threshold V_S(UV)

.

5.1.1.2

Power-up

The power-up transition is entered when the supply voltage (V_S) is applied to the device. The supply rises until it

exceeds the undervoltage threshold V_S(OP)

.

5.1.1.3

Sleep

The device is in sleep mode when digital input (DI) pins are set to "low". While in sleep mode the current consumption

is at I_VS(SLEEP). Overtemperature, overload protection and undervoltage mechanism are disabled. The device can go

in sleep mode only if the protection is not active (n_RESTART(CR)= 0, T_J< T_J(ABS)and (T_J- T_J(REF)) < T_J(DYN)(including

hysteresis)), see Chapter 7.3.

5.1.1.4

Inactive with diagnosis

The device is in inactive with diagnosis mode while DEN pin is set to “high” and input pins are set to “low”. The

channels are OFF, therefore open load in OFF diagnosis is possible. Depending on the load condition, either a

fault current I_IS(FAULT)or an open load in OFF current I_IS(OLOFF)may be present at IS pin. During such condition, the

current consumption of the device is increased.

5.1.1.5

Active with diagnosis

Active with diagnosis mode is the normal operation mode of of the device. The device enters active with diagnosis

mode for the related channel when INn = "high" and DEN = "high", in this condition one or more outputs are switched

ON with diagnosis. Device current consumption is specified by parameter I_GND(ACTIVE)

.

5.1.1.6

Active without diagnosis

The device is in active without diagnosis mode when INn = "high" and DEN = "low", in this condition, one or more

outputs are switched ON without diagnosis.

5.1.1.7

Capacitive load switching mode with diagnosis

The device has a capacitive load switching mode implemented to drive capacitive loads. The capacitive load

switching mode with diagnosis can be activated with INn = "f_VIN(CLS)" and DEN = "high", in this condition one or

more outputs are switched ON with diagnosis. Device current consumption is specified by parameter I_GND(ACTIVE)

.

Datasheet

17

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

5 Power Supply

5.1.1.8

Capacitive load switching mode without diagnosis

The device is in capacitive load switching mode without diagnosis when INn = "f_VIN(CLS)" and DEN = "low", in this

condition, one or more outputs are switched ON without diagnosis.

5.2

Undervoltage on VS

Between V_S(OP)and V_S(UV)the undervoltage mechanism is triggered.

The power output stage follows the input logic as long as V_S> V_S(OP)

.

If the device is Active or in Capacitive Load Switching Mode, with or without Diagnosis and the supply voltage V_Sdrops

below the undervoltage threshold V_S(UV), the internal logic switches OFF the output channel.

V_S

V_S(OP)

V_S(HYS)

V_S(UV)

t

INn

t

V_OUTn

t

Figure 14

V_Sundervoltage behavior

5.3

Electrical characteristics power supply

V_S= 4 V to 20 V, T_J= -40°C to +150°C

Unless otherwise specified typical values: V_S= 13.5 V, T_J= 25°C

Typical resistive loads connected to the outputs for testing (unless otherwise specified):

BTS7050-2EPL: R_L= 4.7 Ω

Table 7

Electrical characteristics power supply

Parameter

Symbol

Values

Unit

Note or condition

P-

Number

Min.

Typ.

Max.

VS pin

Power supply

undervoltage

shutdown

V_S(UV)

1.8

2.2

2.7

V

V_Sdecreasing

INn = “high”

PRQ-98

From 0 ≤ V_DS≤ 0.5 V to

V_DS∼ V_S

See Figure 14

(table continues...)

Datasheet

18

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

5 Power Supply

Table 7

(continued) Electrical characteristics power supply

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

2.1

Max.

Power supply

minimum operating

voltage

V_S(OP)

2.5

3

–

V

V_Sincreasing

INn = “high”

PRQ-99

From V_DS∼ V_Sto

0 ≤ V_DS≤ 0.5 V

See Figure 14

1)

Power supply

undervoltage

shutdown hysteresis

V_S(HYS)

–

0.3

–

V

PRQ-100

PRQ-101

PRQ-826

V_S(OP)- V_S(UV)

See Figure 14

1)

Breakdown voltage

between GND and VS

pins in reverse battery

-V_S(REV)

16

–

30

V

I_GND(REV)= 7 mA

T_J= 150°C

1)

Power supply current I_{VS(SLEEP)_85}

consumption in sleep

mode with loads at TJ

≤ 85°C

0.03

0.5

μA

V_S= 20 V

V_OUT= 0 V

INn = DEN = DSEL =

“low”

T_J≤ 85°C

Power supply current I_{VS(SLEEP)_150}

consumption in sleep

mode with loads at TJ

= 150°C

–

3.5

14

µA

V_S= 20 V

V_OUT= 0 V

INn = DEN = DSEL =

“low”

PRQ-827

T_J= 150°C

Operating current in

active with diagnosis

mode

I_GND(ACTIVE)

–

3.7

1.8

4.5

2.2

mA

V_S= 20 V

INn = DEN = DSEL =

“high”

PRQ-828

PRQ-829

Operating current in

inactive with diagnosis

mode

I_{GND(INACTIVE)}

V_S= 20 V

INn = "low"

DEN = DSEL = “high”

1)

Not subject to production test - specified by design

Datasheet

19

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

6 Power Stage

6

Power Stage

The high-side power stages are built using a N-channel vertical power MOSFET with charge pump.

6.1

Output ON-state resistance

The ON-state resistance R_DS(ON)depends mainly on junction temperature T_J. Figure 15, shows the variation

of R_DS(ON)across the whole T_Jrange. The value “2” on the y-axis corresponds to the maximum R_DS(ON)measured

at T_J= 150°C.

R_DS(ON)variation over T_J

2.20

2.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

Reference value:

"2" = R_DS(ON),MAX@ 150

Typical

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

160

Junction Temperature (°C)

Figure 15

R_DS(ON)variation factor

The behavior in reverse polarity is described in Chapter 7.4.1.

6.2

Switching loads

6.2.1

Switching resistive loads

When switching resistive loads, the switching times and slew rates shown in Figure 16 can be considered.

The switching energy values E_ONand E_OFFare proportional to load resistance and times t_ONand t_OFF

.

Datasheet

20

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

6 Power Stage

INn

V_IN(TH)

V_IN(HYS)

t

V_OUTn

90% of V_S

t_ON

t_OFF(DELAY)

70% of V_S

30% of V_S

(dV/dt)_OFF

(dV/dt)_ON

30% of V_S

10% of V_S

t_ON(DELAY)

t_OFF

t

P_DMOS

E_ON

E_OFF

Figure 16

Switching a resistive load

6.2.2

Switching inductive loads

When switching OFF inductive loads with high-side switches, the voltage V_OUTdrops below ground potential, because

the inductance intends to continue driving the current. To prevent the destruction of the device due to overvoltage, a

voltage clamp mechanism is implemented. The clamping structure limits the output voltage so that V_DS≤ V_DS(CLAMP)

Chapter 6.2.2 shows a concept drawing of the implementation.

.

The clamping structure is active in all operation modes listed in Chapter 5.1.

VS

V_SIS(CLAMP)

V_DS(CLAMP)

V_DSn

V_S(CLAMP)

V_S

IS

I_Ln

OUTn

GND

V_OUTn

Figure 17

Output clamping concept

During demagnetization of inductive loads, energy has to be dissipated in the device. The energy can be calculated

with:

Datasheet

21

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

6 Power Stage

V − V

R · I

S

DS CLAMP

L

(1)

E = V

·

· ln 1 −

+ I

·

DS CLAMP

L

R

V − V

R

L

S

DS CLAMP

L

The maximum energy the device can sustain is limited by the thermal design. Please refer to Table 2 for the maximum

allowed values of E_AS(single pulse energy) and E_AR(repetitive energy).

6.2.3

Switching capacitive loads

When f_VIN(CLS)is applied the device enters CLS mode afer t_{ON_CLS(DELAY)}as shown in Figure 18. A pumping mode is

applied to charge the capacitor while the overcurrent limitation is active, as shown in Figure 19. During CLS mode,

protection and diagnosis functions are active.

f_VIN(CLS)

INn

V_IN(TH)

V_IN(HYS)

t

n_ACT

0

n_CLS(ACT)x= 1

0

t

V_OUT

90% of V_S

t_ON

t_{OFF_CLS(DELAY)}t_OFF(DELAY)

70% of V_S

30% of V_S

70% of V_S

(dV/dt)_ON

(dV/dt)_OFF

30% of V_S

10% of V_S

t_{ON_CLS(DELAY)}t_ON(DELAY)

t_OFF

t

Figure 18

Switching a capacitive load

When the device is in CLS mode, the dynamic overtemperature protection is reduced to T_{J(DYN)_CLS}with continuous

restart.

A transition from CLS mode to Active mode is performed automatically when V_DS≤ V_DS(OLOFF)

.

On the contrary, when V_DS> V_DS(OLOFF), the CLS mode has to be lef afer a maximum time of t_CLSxby setting input to

"low" or "high".

A transition from capacitive load switching mode to active mode shall be performed only if there is no short circuit at

the output. To distinguish between short circuit and normal load, a current sense measurement must be performed

before leaving. If the current measurement delivers an expected value, the transition from CLS mode to active mode

may be performed. If the current measurement delivers an open load value (no output current), it has to be assumed

that there is either an open load or a short circuit at the output. Additionally, a short circuit condition could be

excluded by an external voltage measurement at the output.

Datasheet

22

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

6 Power Stage

INn

t_CLSx

t

V_OUTn

V_DS(OLOFF)

I_L

I_LIM

I_L

t

n_ACT

0

n_CLS(ACT)x= 1

0

Operation

Mode

SLEEP

Capacitive Load Switching Mode

ACTIVE

Figure 19

6.3

Capacitive load switching activations

Advanced switching characteristics

Inverse current behavior

6.3.1

When V_OUT> V_S, a current I_L(INV)flows into the power output transistor (see Figure 20). This condition is known as

“Inverse Current”.

If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses,

therefore, an increase of overall device temperature. This may lead to a switch OFF of unaﬀected channels due to

overtemperature. If the channel is in ON state, R_DS(INV)can be expected and power dissipation in the output stage is

comparable to normal operation in R_DS(ON)

.

During inverse current condition, the channel remains in ON or OFF state as long as |-I_L| < |-I_L(INV)|.

The feature of InverseON allows to switch ON the channel during Inverse Current condition as long as |-I_L| < |-I_L(INV)|,

see Figure 21.

Datasheet

23

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

6 Power Stage

VS

Power stage

control

INV

Comp.

Device logic

-I_Ln

V_OUT> V_S

OUTn

GND

Figure 20

Inverse current circuitry

CASE 1 : Power stage is on

Power stage control

CASE 2 : Power stage is off

Power stage control

„high“

„low“

I_L

t

I_L

t

NORMAL

INVERSE

ON

INVERSE

OFF

Power stage

t

CASE 3 : Switch on during inverse current

Power stage control

CASE 4 : Switch off during inverse current

Power stage control

„low“

„high“

„low“

I_L

t

NORMAL

INVERSE

Power stage

OFF

ON

OFF

t

Figure 21

InverseON - Channel behavior in case of applied inverse current

6.4

Electrical characteristics power stage

V_S= 4 V to 20 V, T_J= -40°C to +150°C

Unless otherwise specified typical values: V_S= 13.5 V, T_J= 25°C

Datasheet

24

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

6 Power Stage

Typical resistive loads connected to the outputs for testing (unless otherwise specified):

BTS7050-2EPL: R_L= 4.7 Ω

Table 8

Electrical characteristics power stage

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

Max.

Voltages

Drain to source

clamping voltage at TJ

= -40°C

V_{DS(CLAMP)_-40}

33

36.5

38

42

V

I_L= 5 mA

T_J= -40°C

See Chapter 6.2.2

1)

PRQ-110

PRQ-111

Drain to source

clamping voltage at TJ

≥ 25°C

V_{DS(CLAMP)_25}

35

44

I_L= 5 mA

T_J≥ 25°C

See Chapter 6.2.2

Timings

Switch-ON delay

t_ON(DELAY)

t_OFF(DELAY)

t_ON

10

50

30

70

130

160

210

220

µs

V_S= 13.5 V

V_OUT= 10% V_S

See Figure 16

PRQ-834

PRQ-835

PRQ-836

PRQ-837

Switch-OFF delay

Switch-ON time

50

V_S= 13.5 V

V_OUT= 90% V_S

See Figure 16

130

100

V_S= 13.5 V

V_OUT= 90% V_S

See Figure 16

Switch-OFF time

CLS activation delay

t_OFF

V_S= 13.5 V

V_OUT= 10% V_S

See Figure 16

t_{ON_CLS(DELAY)}

t_{OFF_CLS(DELAY)}

Δt_SW

10

70

40

25

200

90

µs

V_S= 13.5 V

See Figure 18

PRQ-838

PRQ-839

PRQ-840

CLS de-activation

delay

20

V_S= 13.5 V

See Figure 18

Switch-ON/OFF

Matching - tON - tOFF

-60

90

V_S= 13.5V

Voltage slope

Switch-ON slew rate

(dV/dt)_ON

(dV/dt)_OFF

Δ(dV/dt)_SW

0.16

0.27

-0.27

0

0.39

-0.16

0.15

V/µs

V_S= 13.5 V

V_OUT= 30% to 70% of V_S

PRQ-841

PRQ-842

PRQ-843

Switch-OFF slew rate

-0.39

-0.15

V_S= 13.5V

V_OUT= 70% to 30% of V_S

Slew rate matching -

(dV/dt)ON + (dV/dt)OFF

V_S= 13.5V

(table continues...)

Datasheet

25

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

6 Power Stage

Table 8

(continued) Electrical characteristics power stage

Parameter

Symbol

Values

Typ.

Unit

kHz

–

Note or condition

P-

Number

Min.

Max.

CLS mode

2)

Input frequency

for capacitive load

switching mode

activation

f_VIN(CLS)

22

30

38

PRQ-353

PRQ-354

DC_VIN(CLS)= 50%

2)

Duty cycle for

capacitive load

switching mode

activation

DC_VIN(CLS)

30%

50%

70%

f_VIN(CLS)= 30 kHz

2)

Maximum time in CLS t_CLS1

–

25

ms

PRQ-355

PRQ-813

PRQ-812

PRQ-814

mode

See Chapter 6.2.3

2)

Maximum time in CLS t_CLS2

mode

90

ms

See Chapter 6.2.3

2)

Maximum number of

CLS mode activations

n_{CLS_ACT1}

n_{CLS_ACT2}

500

50

kcycles

See Chapter 6.2.3

2)

Maximum number of

CLS mode activations

See Chapter 6.2.3

Output characteristics

2)

ON-state resistance at R_{DS(ON)_25}

–

50

–

mΩ

PRQ-542

PRQ-543

PRQ-544

TJ = 25°C

T_J= 25°C

ON-state resistance at R_{DS(ON)_150}

TJ = 150°C

100

110

T_J= 150°C

I_L= 2 A

ON-state resistance in R_{DS(ON)_CRANK_15}

–

T_J= 150°C

V_S= 3.1 V

I_L= 1 A

2)

cranking at TJ = 150°C

0

ON-state resistance in R_{DS(INV)_25}

inverse current at TJ =

25°C

–

50

–

mΩ

PRQ-545

T_J= 25°C

V_S= 13.5 V

I_L= -2 A

See Figure 20

ON-state resistance in R_{DS(INV)_150}

inverse current at TJ =

150°C

–

110

–

mΩ

T_J= 150°C

V_S= 13.5 V

I_L= -2 A

See Figure 20

2)

PRQ-546

PRQ-547

Nominal load current I_{L(NOM)_85}

per channel (all

channels active) at TA

= 85°C

3

A

T_A= 85°C

T_J≤ 150°C

(table continues...)

Datasheet

26

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

6 Power Stage

Table 8

(continued) Electrical characteristics power stage

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

Max.

0.5

2)

Output leakage current I_{L(OFF)_85}

at TJ ≤ 85°C

–

0.01

µA

PRQ-548

V_OUT= 0 V

INn = "low"

T_A≤ 85°C

Output leakage current I_{L(OFF)_150}

–

1.2

3

4

–

µA

A

V_OUT= 0 V

INn = "low"

T_A= 150°C

2)

PRQ-549

PRQ-550

at TJ = 150°C

Inverse current

capability

I_L(INV)

V_S< V_OUT

INn = "high"

See Figure 20

Voltages

Drain source diode

voltage

|V_DS(DIODE)

|

–

550

1.2

700

–

mV

mJ

I_L= -190 mA

T_J= 150°C

1)

PRQ-552

PRQ-553

Switch-ON energy

E_ON

V_S= 20V

See Figure 16

1)

Switch-OFF energy

E_OFF

–

1.25

–

mJ

PRQ-554

V_S= 20V

See Figure 16

1)

2)

Tested at T_J= 150°C

Not subject to production test - specified by design

Datasheet

27

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

7 Protection

7

Protection

The device is protected against overload, overtemperature and overvoltage.

Overtemperature and overload protection are operational in all operation modes, except when in sleep mode.

Overload protection is not active during inverse current condition.

Overtemperature and overload protection during inverse current condition is inactive on the channel which is in

inverse condition.

Overvoltage protection is active in all operation modes.

7.1

Overcurrent protection

Overcurrent threshold

7.1.1

The device is protected in case of overload and short circuit to ground.

The device oﬀers a current limitation, this feature oﬀers protection against overstress for the power output stage. At

first step, the instantaneous power in the switch is maintained at a safe value by limiting the current to the maximum

current allowed in the switch (I_LIM). The current limitation is independent of V_DSand T_J. In case of DMOS temperature

increase exceeding the device safe operation environment, overtemperature and dynamic tempertature protection

mechanism will be triggered as shown in Figure 22 and Figure 23.

7.2

Overtemperature protection

The device incorporates both an absolute (T_J(ABS)) and a dynamic (T_J(DYN)) temperature protection circuitry for each

channel.

An increase in junction temperature T_Jabove either one of the two thresholds (T_J(ABS)or T_J(DYN)) switches OFF

the overheated channel. The aﬀected channel will perform automatic restart attempts. The channel remains

switched OFF until the junction temperature has reached the restart condition described in Table 9 according to

Chapter 7.3.1. If the number of automatic restart attempts exceeds n_{RESTART(CR),TYP}, the aﬀected channel latches OFF

to prevent destruction. The behavior is shown in Figure 22 and Figure 23. T_J(REF)is the reference temperature used for

dynamic temperature protection.

INn

t

DEN

t

I_L

I_LIM

t

T_J

T_J(ABS)

t

t_{IS(FAULT)_D}

I_IS

I_IS(FAULT)

I_IS= I_L/ k_ILIS

I_L/ k_ILIS

I_IS< I_IS(SAT),Min

t

Internal

counter

0

1

t

Figure 22

Overtemperature protection (absolute)

Datasheet

28

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

7 Protection

INn

t

DEN

I_L

I_LIM

t

T_J

T_J(ABS)

T_J(REF)

t_{IS(FAULT)_D}

I_IS

I_IS(FAULT)

I_L/ k_ILIS

t

Internal

counter

0

1

2

Figure 23

Overtemperature protection (dynamic)

When the overtemperature protection circuitry allows the channel to be switched ON again, the retry strategy

described in Chapter 7.3 is followed.

7.3

Protection and diagnosis in case of fault

Any event that triggers overtemperature protection has two consequences:

•

The aﬀected channel switches OFF according to Chapter 7.3.1.

If the diagnosis is active for the aﬀected channel, a current I_IS(FAULT)is provided by IS pin (see Chapter 8.2.2 for

further details).

The channel can be switched ON again if all the protection mechanisms fulfill the “restart” conditions described

in Table 9 and n_RESTART(CR)< n_{RESTART(CR),typ}

.

Table 9

Protection "restart" condition

Switch OFF event

Fault condition

"Restart" condition

Overtemperature T_J≥ T_J(ABS)or (T_J- T_J(REF)) ≥ T_J(DYN)

T_J< T_J(ABS)and (T_J- T_J(REF)) < T_J(DYN)(including hysteresis)

7.3.1

Retry strategy

When INn is set to “high”, the related power output stage is switched ON. If a fault condition is detected the power

output stage is switched OFF. The device will apply the restart strategy and return to normal operation or latches OFF

if the fault remains to be present afer n_{RESTART(CR),TYP}

.

The device has an internal retry counter n_RESTART(CR)(one for each channel) to maximize the robustness in case of

fault.

The channel is allowed to switch ON for n_RESTART(CR)times before switching OFF. Afer n_{RESTART(CR),TYP}consecutive

“restart” cycles, the channel latches OFF. To de-latch the power output stage and reset the internal counter it is

necessary to set the input pin to “low” for a time longer than t_DELAY(CR)

.

If the fault is no longer present and t_DELAY(CR)is observed the device will enter normal operation. In case the fault is

still present, the device will trigger again the retry strategy.

The retry strategy is shown in Figure 24.

Datasheet

29

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

7 Protection

INn

t

Short

circuit to

ground

I_L

I_LIM

t

Internal

temperature

protection

t_DELAY(CR)

Internal

counter

0

1

2

3

4

5

6

n_RESTART(CR)+1

0

DEN

I_IS(FAULT)

I_IS

I_L/ k_ILIS

t

t_sIS(DIAG)

Figure 24

Retry strategy timing diagram

It is possible to “force” a reset of the internal counter without waiting for t_DELAY(CR)by applying a pulse (rising edge

followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have a duration

longer than t_DEN(CR)to ensure a reset of the internal counter. The DSEL pin must select the channel that has to be

de-latched and keep the same logic value while DEN pin toggles twice (rising edge followed by a falling edge).

The timings are shown in Figure 25.

Datasheet

30

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

7 Protection

INn

t

Short

circuit to

ground

I_L

I_LIM

t

Internal

temperature

protection

Internal

counter

0

1

2

3

4

5

6

n_RESTART(CR)+1

0

1

2

3

4

5

6

n_RESTART(CR)+1

0

DEN

t_DEN(CR)

I_IS(FAULT)

t_DEN(CR)

I_IS(FAULT)

t_DEN(CR)

I_IS(FAULT)

I_IS

I_L/ k_ILIS

t

t_sIS(DIAG)

Figure 25

Retry strategy timing diagram with forced reset

7.4

Additional protection

7.4.1

Reverse polarity protection

In reverse polarity condition (also known as reverse battery), power dissipation is caused by the intrinsic body diode

of the DMOS channel. Each ESD diode of the logic contributes to total power dissipation. The reverse current through

the output stages must be limited by the connected loads. The current through digital input pins has to be limited by

an external resistor (please refer to the absolute maximum ratings listed in Table 2 and to Application Information in

Chapter 9).

7.4.2

Overvoltage protection

In the case of supply voltages between V_S(EXT,UP)and V_BAT(LD), the output transistors are still operational and follow the

input pin.

In addition to the output clamp for inductive loads as described in Chapter 6.2.2, there is a clamp mechanism

available for overvoltage protection for the logic and the output channels, monitoring the voltage between V_Sand

GND pins (V_S(CLAMP)).

7.4.3

Loss of battery and loss of load

The loss of connection to the battery or the load does not influence device robustness as long as load and wire

harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be handled.

The device can handle the inductivity of the wire harness up to 10 µH with I_{L(NOM)_85.}

In case of applications where currents and/or the aforementioned inductivity are exceeded, an external suppressor

diode (like diode D_Z2shown in Chapter 9) is recommended to handle the energy and to provide a well-defined path

for the load current.

Datasheet

31

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

7 Protection

7.4.4

Loss of ground

It is recommended to have a resistor connected between any digital input pin and the microcontroller to ensure a

channel switch OFF in case of a loss of device ground event (as described in Chapter 9).

Note

In case any digital input pin is pulled to ground (either by a resistor or active) a parasitic ground path is present, which

could keep the device operational during a loss of device ground.

7.5

Electrical characteristics protection

V_S= 4 V to 20 V, T_J= -40°C to +150°C

Unless otherwise specified typical values: V_S= 13.5 V, T_J= 25°C

Typical resistive loads connected to the outputs for testing (unless otherwise specified):

BTS7050-2EPL: R_L= 4.7 Ω

Table 10

Electrical characteristics protection

Parameter

Symbol

Values

Typ.

175

Unit

Note or condition

P-

Number

Min.

150

Max.

200

1) 2)

Thermal shutdown

temperature (absolute)

T_J(ABS)

°C

K

PRQ-174

PRQ-356

PRQ-357

PRQ-177

See Figure 22

3)

Thermal shutdown

hysteresis (absolute)

T_HYS(ABS)

T_J(DYN)

–

30

80

40

–

See Figure 22

3)

Thermal shutdown

temperature (dynamic)

K

See Figure 22

3)

Thermal shutdown

temperature (dynamic)

in capacitive load

switching mode

T_{J(DYN)_CLS}

K

Power supply clamping V_{S(CLAMP)_-40}

33

35

36.5

38

42

44

V

I_VS= 5 mA

T_J= -40°C

See Chapter 6.2.2

2)

PRQ-179

PRQ-184

voltage at TJ = -40°C

Power supply clamping V_{S(CLAMP)_25}

voltage at TJ ≥ 25°C

I_VS= 5 mA

T_J≥ 25°C

See Chapter 6.2.2

1)

Automatic restarts in

case of fault afer

counter reset

n_RESTART(CR)

t_DELAY(CR)

t_DEN(CR)

–

6

–

PRQ-186

PRQ-188

PRQ-190

See Figure 24

1)

Counter reset delay

time afer fault

condition

40

50

70

100

150

ms

µs

See Figure 24

3)

Minimum DEN pulse

duration for counter

reset

See Figure 25

(table continues...)

Datasheet

32

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

7 Protection

Table 10

(continued) Electrical characteristics protection

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

Max.

Overcurrent limitation

4)

Overcurrent limitation I_LIM

7.45

9.48

11.5

A

PRQ-832

V_DS= 3 V

1)

2)

3)

4)

Functional test only

Tested at T_J= 150°C only

Not subject to production test - specified by design

Tested at T_J= -40°C only

Datasheet

33

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

8

Diagnosis

For the purpose of diagnosis, the device provides a proportional sense current signal (I_IS) at pin IS. In case of

disabled diagnostic (DEN pin set to “low”), IS pin becomes high impedance.

A sense resistor R_SENSEmust be connected between IS pin and module ground if the current sense diagnosis is used.

R_SENSEvalue has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present on the battery

feed) to limit the power losses in the sense circuitry.

A typical value is R_SENSE= 1.2 kΩ.

Due to the internal connection between IS pin and V_Ssupply voltage, it is not recommended to connect the IS pin to

the sense current output of other devices, if they are supplied by a diﬀerent battery feed.

See Figure 26 for details as an overview.

VS

Channel 1

Channel 0

T

Overtemperature

Internal Counters

IS Pin Control

Logic

OUT1

OUT0

INn

DEN

DSEL

I_L/ k_ILIS

+

V_{DS(kILIS_EN)}

MUX

+

I_IS(FAULT)

V_DS(OLOFF)

I_IS(OLOFF)

MUX

IS

Figure 26

Diagnosis block diagram

8.1

Overview

Table 11 gives a quick reference to the state of the IS pin during the device operation.

Table 11

SENSE signal as a function of application condition

Operation mode

Input level

DEN level

V_OUT

Diagnostic output

Normal operation

LOW/OFF

HIGH

~ GND

Z

I_IS(FAULT)if n_RESTART(CR)> 0

Short circuit to GND

(table continues...)

Datasheet

~ GND

Z

I_IS(FAULT)if n_RESTART(CR)> 0

34

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

Table 11

(continued) SENSE signal as a function of application condition

Operation mode

Input level

DEN level

V_OUT

Diagnostic output

Thermal shutdown

temperature (absolute)

Z

I_IS(FAULT)

Thermal shutdown

temperature (dynamic)

Z

I_IS(FAULT)

Short circuit to V_S

= V_S

I_IS(OLOFF)

I_IS(FAULT)if n_RESTART(CR)> 0

Open load

< V_S- V_DS(OLOFF)

Z

1)

> V_S- V_DS(OLOFF)

I_{IS(OLOFF) or IS(FAULT)}

if n_RESTART(CR)> 0 for both cases

I_{S(OLOFF) or IS(FAULT)}if n_RESTART(CR)> 0

I_IS= I_L/ k_ILIS

I_IS(FAULT)

I

Inverse current

~ V_INV= V_OUT> V_S

I

Normal operation

Short circuit to GND

HIGH/ON or

CLS

< V_S- V_{DS(kILIS_EN)}

~ GND

Z

Thermal shutdown

temperature (absolute)

I_IS(FAULT)

Thermal shutdown

temperature (dynamic)

Z

I_IS(FAULT)

Short circuit to V_S

Open load

= V_S

I_IS< I_L/ k_ILIS

I_IS= I_IS(EN)

I_IS(FAULT)

2)

~ V_S

Inverse current

Current limitation

Underload

~ V_INV= V_OUT> V_S

< V_S

3)

~ V_S

I_IS(EN)< I_IS< I_L(NOM)/ k_ILIS

All conditions

n.a.

LOW

n.a.

Z

1) With additional pull up resistor

2) The output current has to be smaller than I_L(OL)

3) The output current has to be higher than I_L(OL)

8.1.1

SENSE signal truth table

Diagnosis can be activated or deactivated using the DEN pin. Channel selection is done with DSEL pin according

to Table 12.

Table 12

Diagnostic truth table

DSEL

DEN

IS

"low"

"high"

not relevant

Z

"low"

SENSE output 0

SENSE output 1

"high"

Datasheet

35

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

8.2

Diagnosis in ON state

A current proportional to the load current (I_IS= I_L/k_ILIS) is provided at pin IS when the following conditions are fulfilled:

•

The power output stage is switched ON with V_DS< V_{DS(kILIS_EN)}

The diagnosis is enabled for that channel

No fault (as described in Chapter 7.3) is present or was present and not cleared yet (see Chapter 8.2.2 for further

details)

As long as a fault is present or was present and not cleared yet a current I_IS(FAULT)is provided at IS pin.

8.2.1

Current sense (kILIS)

I_ISincreases linearly with I_Loutput current until it reaches the saturation current I_IS(SAT). In case of open load at

the output stage (I_Lclose to 0 A), the maximum sense current I_IS(EN)(no load, diagnosis enabled) is specified. This

condition is shown in Figure 27. The center line represents the ideal k_ILIS, while the outer lines show the behavior of

a typical product. An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce

signal ripple and oscillations (a minimum time constant of 1 µs for the RC filter is recommended). The k_ILISfactor is

specified with limits that take into account eﬀects due to temperature, supply voltage, and manufacturing process.

I_IS

I_IS(OL)

I_IS(EN)

I_{L(OL)_4u}

I_L

Figure 27

Current sense ratio in open load at ON condition

8.2.2

Fault current (IIS(FAULT))

In case a fault is present and DEN is set to “high” and the aﬀected channel is selected by DSEL, a current I_IS(FAULT)is

provided.

The following situations may occur:

•

If the channel is ON and the number of restarts is less than “n_{RESTART(CR),TYP}”, the current I_IS(FAULT)is provided for a

time t_{IS(FAULT)_D}afer the channel is allowed to restart, and thereafer I_IS= I_L/k_ILIS(as shown in Figure 28). During a

restart cycle the current I_IS(FAULT)is provided each time the channel diagnosis is checked.

If the channel is ON and the number of restarts is equal to “n_{RESTART(CR),TYP}”, the current I_IS(FAULT)is provided

until the internal counter is reset. The internal counter can be cleared either by INn = "low" for t_DELAY(CR)or by

INn = "low" and DEN pin pulse for t_DEN(CR), as described in Chapter 7.3.1.

While the channel is OFF and the internal counter value is not reset, the current I_IS(FAULT)is provided.

Datasheet

36

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

INn

t

I_L

I_LIM

Internal

counter

0

1

2

0

t

DEN

t_{IS(FAULT)_D}

t_DEN(CR)

I^IS(FAULT)

I_IS

I_IS(FAULT)

I_L/ k_ILIS

t

Figure 28

I_IS(FAULT)at load switching

Figure 29 adds the behavior of SENSE signal to the timing diagram seen in Figure 24, while Figure 30 shows the

relation between I_IS= I_L/k_ILIS, I_IS(SAT)and I_IS(FAULT)

.

INn

t

Short

circuit to

ground

I_L

I_LIM

t

Internal

temperature

protection

t_DELAY(CR)

Internal

counter

0

1

2

3

4

5

6

n_RESTART(CR)+1

0

DEN

I_IS(FAULT)

I_IS

I_L/ k_ILIS

t

t_sIS(DIAG)

Figure 29

SENSE behavior in fault condition

Datasheet

37

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

I_IS

I_IS(SAT),MAX

I_{IS(FAULT),MAX}

I_IS(SAT)

I_IIS(FAULT)

I_IS(SAT),MIN

I_{IS(FAULT),MIN}

I_L/ k_ILIS

I_L

Figure 30

SENSE behavior - overview

8.3

Diagnosis in OFF State

When a power output stage is in OFF state, the device can measure the output voltage and compare it with a

threshold voltage. In this way, using some additional external components (a pull-down resistor and a switchable

pull-up current source), it is possible to detect if the load is missing or if there is a short circuit to battery. If a fault

condition was detected by the device (the internal counter has a value diﬀerent from the reset value, as described in

Chapter 8.2.2 a current I_IS(FAULT)is provided by IS pin each time the channel diagnosis is checked also in OFF state.

Figure 31 shows the relationship between I_IS(OLOFF)and I_IS(FAULT)as functions of V_DS. The two currents do not overlap

making it always possible to diﬀerentiate between open load in OFF and fault condition.

I_IS

I_IS(FAULT)

I_IS(OLOFF)

V_DS(OLOFF)

V_DS

Figure 31

I_ISin OFF state

8.3.1

Open load current

In OFF state, while DEN pin is set to “high” and a channel is selected using DSEL pin, the V_DSvoltage is compared with

a threshold voltage V_DS(OLOFF). When the diagnosis is active and V_DS≤ V_DS(OLOFF), a current I_IS(OLOFF)is provided by IS

pin. If the load is properly connected and there is no short circuit to battery, V_DS~ V_S, therefore, V_DS> V_DS(OLOFF)the IS

pin is set to high impedance.

Datasheet

38

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

It is necessary to wait a time t_{IS(OLOFF)_D}between the falling edge of the input pin and the sensing at pin IS for Open

Load in OFF diagnosis to allow the internal comparator to settle. In Figure 32 the timings for an Open Load detection

are shown - the load is always disconnected.

INn

t

DEN

t

t_{IS(OLOFF)_D}

~ V_S

V_OUT

V_DS(OLOFF)

Load connected

t

I_IS

I_IS(OLOFF)

I_{IS(OL)_4u}

Figure 32

Open load in OFF timings - load disconnection

8.4

SENSE timings

Figure 33 and Figure 34 show the timing during settling t_sIS(ON)and disabling t_sIS(OFF)of the SENSE (including the case

of load change). As a proper signal cannot be established before the load current is stable (therefore before t_ON),

t

= t

+ t

(2)

sIS DIAG

sIS ON

ON

INn

DEN

I_L

OFF

ON

OFF

t

t_OFF

t

t_sIS(OFF)

t_sIS(LC)

t_sIS(ON)

I_IS

t_sIS(DIAG)

Figure 33

SENSE settling/disabling timing

Datasheet

39

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

INn

OFF

ON

OFF

t

DEN

I_L

t_{sIS(LC)_SLC}

t

t_{sIS(ON)_SLC}

t_sIS(ON)

I_IS

Figure 34

SENSE timing with small load current

DEN

DSEL

I_L0

t

I_{L(NOM)_85}

t

I_L1

I_{L(NOM)_85}/ 2

I_L01

t_sIS(CC)

t_{sIS(CC)_SLC}

t_sIS(OFF)

t_sIS(ON)

I_IS

Figure 35

SENSE settling timing - channel change

8.5

Electrical characteristics diagnosis

V_S= 4 V to 20 V, T_J= -40°C to +150°C

Unless otherwise specified typical values: V_S= 13.5 V, T_J= 25°C

Typical resistive loads connected to the outputs for testing (unless otherwise specified):

BTS7050-2EPL: R_L= 4.7 Ω

Datasheet

40

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

Table 13

Electrical characteristics diagnosis

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

4.4

Max.

15

1)

SENSE saturation

current

I_IS(SAT)

–

mA

PRQ-215

V_S= 6 V to 20 V

R_SENSE= 1.2 kΩ

See Figure 30

SENSE leakage current I_IS(OFF)

when disabled

–

0.01

0.2

0.5

2

µA

DEN = "low"

I_L≥ I_L(NOM)

V_IS= 0 V

1)

PRQ-219

PRQ-221

SENSE leakage current I_{IS(EN)_85}

when enabled at TJ ≤

85°C

T_J≤ 85°C

DEN = "high"

I_L= 0 A

See Figure 27

SENSE leakage current I_{IS(EN)_150}

when enabled at TJ =

150°C

–

0.2

2

µA

T_J= 150°C

DEN = "high"

I_L= 0 A

PRQ-223

See Figure 27

1)

Saturation voltage in

kILIS operation (VS-

VIS)

V_{SIS_k}

–

0.5

1

V

PRQ-226

PRQ-682

V_S= 5 V

IN = DEN = “high”

1)

Saturation voltage in

open load at OFF

diagnosis (VS-VIS)

V_{SIS_OL}

V_S= 5 V

IN = "low"

DEN = "high"

1)

Saturation voltage in

fault diagnosis (VS-VIS)

V_{SIS_F}

–

0.5

1

V

PRQ-684

V_S= 5 V

IN = "low"

DEN = "high"

counter > 0

Power supply to IS pin V_{SIS(CLAMP)_-40}

clamping voltage at TJ

=-40°C

33

35

36.5

38

42

44

V

I_IS= 1mA

T_J= -40°C

See Chapter 6.2.2

2)

PRQ-294

PRQ-296

Power supply to IS pin V_{SIS(CLAMP)_25}

clamping voltage at TJ

≥ 25°C

I_IS= 1 mA

T_J≥ 25°C

See Chapter 6.2.2

SENSE fault current

I_IS(FAULT)

4.4

5.5

10

mA

See Chapter 8

PRQ-298

(table continues...)

Datasheet

41

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

Table 13

(continued) Electrical characteristics diagnosis

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

1.9

Max.

3.5

SENSE open load in

OFF current

I_IS(OLOFF)

2.5

mA

µs

See Chapter 8

PRQ-306

PRQ-308

1)

SENSE delay time

at channel switch

ON afer last fault

condition

t_{IS(FAULT)_D}

–

500

185

–

See Figure 28

SENSE open load in

OFF delay time

t_{IS(OLOFF)_D}

70

300

µs

V_DS< V_DS(OLOFF)from

INn falling edge to

I_IS= I_{IS(OLOFF),MIN}⋅ 0.9

PRQ-310

DEN = “high”

n_RESTART(CR)= 0

See Figure 32

1)

VDS threshold for kILIS V_{DS(kILIS_EN)}

0.8

1.3

1.2

1.8

1.4

2.3

V

PRQ-809

PRQ-313

enable

Open load VDS

detection threshold in

OFF state

V_DS(OLOFF)

See Chapter 8.3

SENSE settling time

with nominal load

current stable

t_sIS(ON)

–

5

–

20

60

µs

I_L= I_L(NOM)from DEN

rising edge to I_IS= I_L/

(k_ILIS,MAX@ I_L) ⋅ 0.9

PRQ-315

PRQ-317

See Figure 33

1)

SENSE settling time

with small load current

stable

t_{sIS(ON)_SLC}

I_L= I_L01from DEN rising

edge to I_IS= I_L/(k_ILIS,MAX

@ I_L) ⋅ 0.9

See Figure 34

1)

SENSE disable time

t_sIS(OFF)

–

5

20

µs

PRQ-319

I_L= I_L(NOM)

From DEN falling edge

to I_IS= I_IS(OFF)

See Figure 33

1)

SENSE settling time

t_sIS(LC)

–

5

20

µs

PRQ-321

PRQ-323

afer load change

from I_L= I_L(NOM)/2 to I_L=

I_L(NOM)

See Figure 33

1)

SENSE settling time

afer load change with

small load current

t_{sIS(LC)_SLC}

250

400

DEN = "high" from load

change to I_IS= I_L/(k_ILIS

@ I_L) from I_L(NOM)to I_L01

See Figure 34

(table continues...)

Datasheet

42

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

8 Diagnosis

Table 13

(continued) Electrical characteristics diagnosis

Parameter

Symbol

Values

Typ.

Unit

Note or condition

P-

Number

Min.

Max.

20

1)

SENSE settling time

afer channel change

t_sIS(CC)

–

5

µs

PRQ-326

Start channel:

I_L= I_L(NOM)End channel:

I_L= I_L(NOM)/2

See Figure 35

1)

SENSE settling time

afer channel change

with small load current

t_{sIS(CC)_SLC}

–

60

µs

PRQ-327

DEN = “high” from

DSEL toggling to I_IS= I_L/

(k_ILIS,MIN@ I_L) ⋅ 1.1

Start channel: I_L=

I_L(NOM)

End Channel: I_L= I_L01

See Figure 35

Open load output

current at IIS = 4 µA

I_{L(OL)_4u}

2

9.5

17

mA

–

I_IS= I_IS(OL)= 4 µA

I_L02= 20 mA

I_L04= 50 mA

I_L05= 100 mA

I_L08= 250 mA

I_L11= 1 A

PRQ-580

PRQ-585

PRQ-588

PRQ-590

PRQ-594

PRQ-598

PRQ-601

PRQ-604

Current sense ratio at k_ILIS02

IL =IL02

-26%

2230

+26%

+23.5%

+20%

+10%

+9.5%

+6%

Current sense ratio at k_ILIS04

IL =IL04

-23.5% 2030

–

Current sense ratio at k_ILIS05

IL =IL05

-20%

-10%

2030

–

Current sense ratio at k_ILIS08

IL =IL08

–

Current sense ratio at k_ILIS11

IL =IL11

-9.5% 2030

–

Current sense ratio at k_ILIS13

IL =IL13

-6%

-5%

2030

–

I_L13= 2 A

Current sense ratio at k_ILIS15

IL =IL15

+5%

–

I_L15= 4 A

1)

2)

Not subject to production test - specified by design

Tested at T_J= 150°C

Datasheet

43

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

9 Application information

9

Application information

Note:

The following information is given as a hint for the implementation of the device only and shall not be

regarded as a description or warranty of a certain functionality, condition or quality of the device.

V_BAT

Z_WIRE

Optional

Logic Supply

C_VS

C_VSGND

T1

R_GND

GND

VS

OUT0

VDD

GPIO

R_IN

IN0

IN1

C_OUT

C_VS2

D_Z2

R_DEN

R_DSEL

DEN

DSEL

Optional

OUT1

ADC

R_ADC

R_{IS_PROT}

IS

C_OUT

VSS

C_SENSE

Optional

Logic GND

Power GND

Chassis GND

Figure 36

Table 14

Application diagram

Suggested component values

Value Purpose

Reference

R_IN

4.7 kΩ

47 kΩ

1.5 kΩ

Protection of the microcontroller during overvoltage and reverse polarity.

Necessary to switch OFF the output during loss of ground

R_DEN

R_DSEL

R_PD

Protection of the microcontroller during overvoltage and reverse polarity.

Necessary to switch OFF the output during loss of ground

Protection of the microcontroller during overvoltage and reverse polarity.

Necessary to switch OFF the output during loss of ground

Output polarization (pull-down). Ensures polarization of the outputs to

distinguish between open load and short to VS in OFF diagnosis

R_OL

Output polarization (pull-up). Ensure polarization of the output during open load

in OFF diagnosis

C_OUT

T₁

10 nF

Protection of the output during ESD events and BCI

Switch the battery voltage for open load in OFF diagnosis

Filtering of voltage spikes on the battery line

Buﬀer capacitor for fast transient

BC 807

100 nF

47 nF

C_VS

C_VSGND

(table continues...)

Datasheet

44

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

9 Application information

Table 14

(continued) Suggested component values

Value Purpose

Reference

D_Z2

33V TVS Diode

Transient voltage suppressor diode. Protection during overvoltage and in case of

loss of battery while driving an inductive load

Filtering/buﬀer capacitor located at VBAT connector

SENSE resistor

C_VS2

–

R_SENSE

R_{IS_PROT}

1.2 kΩ

4.7 kΩ

Protection during overvoltage, reverse polarity, loss of ground. Value to be tuned

according to microcontroller specifications

D_Z1

7V Z-Diode

Protection of microcontroller during overvoltage

R_ADC

4.7 kΩ

Protection of microcontroller ADC input during overvoltage, reverse polarity, loss

of ground. Value to be tuned according to microcontroller specifications

C_SENSE

R_GND

220 pF

Sense signal filtering. A time constant (R_ADC⋅ C_SENSE) longer than 1 µs is

recommended

47 Ω

Protection in case of overvoltage and loss of battery while driving inductive

loads

•

Please contact us for information regarding the pin behavior assessment

For further information you may contact http://www.infineon.com

Datasheet

45

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

10 Package outlines

10

Package outlines

Figure 37

PG-TSDSO-14 dual small outline package dimensions

Figure 38

PG-TSDSO-14 dual small outline footprint dimensions

Note:

To meet the world-wide customer requirements for environmentally friendly products and to be

compliant with government regulations the device is available as a green product. Green products are

RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC

J-STD-020).

Further information on packages https://www.infineon.com/packages

Datasheet

46

Rev.1.00

2022-09-20

BTS7050-2EPL

Datasheet

11 Revision history

11

Revision history

Table 15

Revision history

Date of release

Document

version

Description of changes

Rev.1.00

2022-09-20

Initial Datasheet

Datasheet

47

Rev.1.00

2022-09-20

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

Edition 2022-09-20

Published by

Infineon Technologies AG

81726 Munich, Germany

Important notice

Warnings

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaﬀenheitsgarantie”).

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer’s compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer’s products and any use of the product of

Infineon Technologies in customer’s applications.

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies oﬀice.

Except as otherwise explicitly approved by Infineon

Technologies in

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or

any consequences of the use thereof can reasonably

be expected to result in personal injury.

a written document signed by

©

2022 Infineon Technologies AG

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Document reference

IFX-idw1639675778625

The data contained in this document is exclusively

intended for technically trained staﬀ. It is the

responsibility of customer’s technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to such

application.


型号：	BTS7050-2EPL
厂家：	Infineon
描述：	The product has a Capacitive Load Switching mode implemented to charge capacitive loads and to reduce current peaks during switch on of capacitors.
文件：	总48页 (文件大小：878K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BTS7050-2EPL [INFINEON]

相关型号：

BTS707

BTS7080-2EPA

BTS71033-6ESA

BTS71033-6ESP

BTS71040-4ESA

BTS71040-4ESE

BTS71040-4ESP

BTS710404ESEXUMA1

BTS710L1

BTS711-L1

BTS711L1

BTS711L1Q67060-S7000-A2