CHL8316CRT [INFINEON]

Digital Multi-Phase Buck Controller Programmable 1-phase to 6-phase operation; 数字多相降压控制器可编程单相到6相工作
CHL8316CRT
型号: CHL8316CRT
厂家: Infineon    Infineon
描述:

Digital Multi-Phase Buck Controller Programmable 1-phase to 6-phase operation
数字多相降压控制器可编程单相到6相工作

多相元件 控制器
文件: 总2页 (文件大小:294K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Digital Multi-Phase Buck Controller  
CHL8316  
FEATURES  
DESCRIPTION  
Intel VR11.x compliant Digital PWM Controller  
The CHL8316 is a 6-phase digital synchronous buck  
controller for core regulation of high-performance Intel®  
VR11.1 and VR11.0 platforms. The CHL8316 is fully  
compliant with VR11.1 including Power Status Indicator  
(PSI) and for improved light load efficiency and accurate  
current output (IMON).  
Programmable 1-phase to 6-phase operation  
Customized Digital Over-Clocking features an  
easy-to-use SMBus Gamer command and a Gamer  
VID control up to 2.3V, Gamer Vmax, VID Override  
or Track, Digital Load-Line Adjust, Gamer OC/OVP,  
Gamer OFF pin and Gamer OTP  
The CHL8316 includes a customized set of digital over-  
clocking features which require no external components.  
Gaming applications can use the SMBus interface to place  
the VRD into “Gamer Mode” to extend VID up to 2.3V with  
6.25 mV resolution.  
IR Efficiency Shaping features a Variable Gate Drive  
and Dynamic Phase Control  
1-phase to 2-phase PSI for Light Loads  
Adaptive Transient Algorithm minimizes capacitors  
Enables Thermal Phase Balancing  
The CHL8316 deploys a number of efficiency shaping  
features such as variable MOSFET gate drive versus load,  
programmable PSI modes for optimum light-load along  
with programmable phase shedding to autonomously  
add/drop phases versus load.  
SMBus Fault Indicators: OVP, UVP, OCP, OTP  
SMBus interface for configuring and monitoring;  
SMBus commands include monitoring input  
current and power  
CHL8316 supports NTC temperature sense to report  
temperature and trigger VR HOT and OTP faults. Digital  
thermal balancing allows proportional current imbalance  
between phases.  
Compatible with IR ATL Drivers and tri-state Drivers  
9 bytes of NVM storage available for customer use  
+3.3V supply voltage; 0ºC to 85ºC Ambient  
operation  
The CHL8316 provides extensive OVP, UVP, OCP, and  
OTP fault protection. Device and fault configuration  
parameters are easily defined using the IR Power Designer  
GUI and stored in on-chip non-volatile memory (NVM).  
RoHS Compliant, MSL level 1 package  
APPLICATIONS  
Intel® VR11.x CPU VRD and VRM; DDR Memory  
The 3-pin SMBus interface can be used to monitor a variety  
of operating parameters on up to seven CHL8316 based  
VRs. The controller includes a unique sensorless and  
lossless input current monitoring capability.  
High Performance Desktops, Servers and  
Graphics Cards  
Over-clocking and High-Efficiency Application  
BASIC APPLICATION  
PIN DIAGRAM  
CHL8316  
48 47 46 45 44 43 42 41 40 39 38 37  
RCSP  
RCSM  
VCC  
1
2
VCC  
36  
35  
34  
PWM6  
PWM5  
PWM4  
PWM3  
3
VCPU  
4
33  
32  
CHL8316  
VRTN  
SADDR/  
GAMER_OFF  
IMON  
5
48 Pin  
7mmx 7mm  
QFN  
6
31  
30  
29  
28  
27  
26  
25  
PWM2  
PWM1  
NC  
7
TOP VIEW  
8
RRES  
VINSEN  
TSEN  
EN  
9
VCC  
GND  
10  
11  
12  
VAR_GATE  
VR_HOT  
V18A  
VR_READY  
13 14 15 16 17 18 19 20 21 22 23 24  
Figure 1: CHL8316 Basic Application Circuit  
October 12, 2011 | FINAL | V1.02  
Figure 2: CHL8316 Package Top View  
1
Digital Multi-Phase Buck Controller  
CHL8316  
ORDERING INFORMATION  
CHL8316 -  
Package  
QFN  
Tape & Reel Qty  
3000  
Part Number  
CHL8316CRT  
CHL8316-XXCRT1  
T Tape and Reel  
QFN  
3000  
R Package Type (DFN)  
Notes:  
1. “xx” indicates customer specific configuration file.  
C Operating Temperature  
(Commercial Standard)  
XX-Configuration File ID  
48 47 46 45 44 43 42 41 40 39 38 37  
RCSP  
RCSM  
VCC  
1
2
VCC  
36  
35  
34  
PWM6  
PWM5  
PWM4  
PWM3  
3
VCPU  
33  
32  
4
CHL8316  
VRTN  
SADDR/  
GAMER_OFF  
IMON  
5
48 Pin  
7mmx 7mm  
QFN  
6
31  
30  
29  
28  
27  
26  
25  
PWM2  
PWM1  
NC  
7
TOP VIEW  
8
RRES  
VINSEN  
TSEN  
EN  
9
VCC  
GND  
10  
11  
12  
VAR_GATE  
VR_HOT  
V18A  
VR_READY  
13 14 15 16 17 18 19 20 21 22 23 24  
Figure 3: CHL8316 Top View Enlarged  
2
October 12, 2011 | FINAL | V1.02  

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