CY15B108QN-50BKXQ [INFINEON]
8Mb 3.3V Industrial(Q) 50MHz SPI EXCELON™ F-RAM in 24-ball FBGA;
| 型号： | CY15B108QN-50BKXQ |
| 厂家： | 
Infineon |
| 描述： | 8Mb 3.3V Industrial(Q) 50MHz SPI EXCELON™ F-RAM in 24-ball FBGA |
| 文件： | 总36页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY15B108QN, CY15V108QN
8Mb EXCELON™ LP Ferroelectric RAM
(F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Features
• 8-Mbit ferroelectric random access memory (F-RAM) logically organized as 1024K × 8
- Virtually unlimited endurance 100 trillion (1014) read/writes
- 151-year data retention (see “Data retention and endurance” on page 24)
- Infineon instant non-volatile write technology
- Advanced high-reliability ferroelectric process
• Fast SPI (FSPI)
- Up to 50 MHz frequency
- Supports SPI Mode 0 (0, 0) and Mode 3 (1, 1)
• Sophisticated write protection scheme
- Hardware protection using the write protect (WP) pin
- Software protection using write disable (WRDI) instruction
- Software block protection for 1/4, 1/2, or entire array
• Device ID and serial number
- Manufacturer ID and product ID
- Unique device ID
- Serial number
• Dedicated 256-byte special sector F-RAM
- Dedicated special sector write and read
- Stored content can survive up to three standard reflow soldering cycles
• Low-power consumption
- 5.5 mA (typ) active current at 50 MHz
- 9 µA (typ) standby current
- 1.10 µA (typ) Deep Power-down mode current
- 0.1 µA (typ) Hibernate mode current
• Low-voltage operation
- CY15V108QN: VDD = 1.71 V to 1.89 V
- CY15B108QN: VDD = 1.8 V to 3.6 V
• Operating temperature
- Extended industrial (Q): -40°C to +105°C
• Package
- 24-ball fine pitch ball grid array (24-ball FBGA)
• Restriction of hazardous substances (RoHS) compliant
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page1
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
Functional description
The EXCELON™ LP CY15X108QN is a low power, 8-Mbit non-volatile memory employing an advanced ferroelectric
process. A ferroelectric random access memory or F-RAM is non-volatile and performs reads and writes similar
to a RAM. It provides reliable data retention for 119 years while eliminating the complexities, overhead, and
system-level reliability problems caused by serial flash, EEPROM, and other non-volatile memories.
Unlike serial flash and EEPROM, the CY15X108QN performs write operations at bus speed. No write delays are
incurred. Data is written to the memory array immediately after each byte is successfully transferred to the
device. The next bus cycle can commence without the need for data polling. In addition, the product offers
substantial write endurance compared to other non-volatile memories. The CY15X108QN is capable of
supporting 1014 read/write cycles, or 100 million times more write cycles than EEPROM.
These capabilities make the CY15X108QN ideal for non-volatile memory applications, requiring frequent or rapid
writes. Examples range from data collection, where the number of write cycles may be critical, to demanding
industrial controls where the long write time of serial flash or EEPROM can cause data loss.
The CY15X108QN provides substantial benefits to users of serial EEPROM or flash as a hardware drop-in
replacement. The CY15X108QN uses the high-speed SPI bus, which enhances the high-speed write capability of
F-RAM technology. The device incorporates a read-only device ID and unique ID features, which allow the host to
determine the manufacturer, product density, product revision, and unique ID for each part. The device also
provides a writable, 8-byte serial number registers, which can be used to identify a specific board or a system.
For a complete list of related resources, click here.
Logic block diagram
WP
256-Byte
Special Sector
F-RAM
CS
Instruction Decoder
F-RAM Control
Control Logic
Write Protect
SCK
SI
1024K x 8
F-RAM Array
Data I/O Register
SO
Non-volatile
Status Register
Device ID and Serial
Number Registers
Datasheet
2
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Table of contents
Table of contents
Features ...........................................................................................................................................1
Functional description.......................................................................................................................2
Logic block diagram ..........................................................................................................................2
Table of contents...............................................................................................................................3
1 Pinout............................................................................................................................................4
2 Pin definitions ................................................................................................................................5
3 Functional overview .......................................................................................................................6
3.1 Memory architecture ..............................................................................................................................................6
3.2 SPI bus.....................................................................................................................................................................6
3.3 SPI overview............................................................................................................................................................6
3.4 Terms used in SPI protocol ....................................................................................................................................7
3.5 SPI modes................................................................................................................................................................9
3.6 Power-up to first access .........................................................................................................................................9
4 Functional description ..................................................................................................................10
4.1 Command structure..............................................................................................................................................10
5 Maximum ratings..........................................................................................................................21
6 Operating range ...........................................................................................................................22
7 DC electrical characteristics...........................................................................................................23
8 Data retention and endurance .......................................................................................................24
8.1 Example of EXCELON™ F-RAM life time in an industrial application..................................................................24
9 Capacitance .................................................................................................................................25
10 Thermal resistance......................................................................................................................26
11 AC test conditions .......................................................................................................................27
13 Power cycle timing......................................................................................................................30
14 Ordering information ..................................................................................................................31
14.1 Ordering code definitions...................................................................................................................................31
15 Package diagram ........................................................................................................................32
16 Acronyms ...................................................................................................................................33
17 Document conventions................................................................................................................34
17.1 Units of measure .................................................................................................................................................34
Revision history ..............................................................................................................................35
Datasheet
3
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Pinout
1
Pinout
5
1
2
3
4
NC
NC
NC
NC
NC
A
B
NC
SCK
VSS
VDD
NC
NC
CS
SO
NC
SI
WP
NC
NC
C
D
DNU
NC
NC
NC
NC
NC
E
Figure 1
24-ball FBGA pinout
Datasheet
4
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Pin definitions
2
Pin definitions
Table 1
Pin definitions
Pin name I/O type
Description
ChipSelect.ThisactiveLOWinputactivatesthedevice.WhenHIGH,thedeviceenters
low-power standby mode, ignores other inputs, and the output is tristated. When
LOW, the device internally activates the SCK signal. A falling edge on CS must occur
before every opcode.
CS
Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched
on the rising edge and outputs occur on the falling edge of the serial clock. The clock
frequency may be any value between 0 and 50 MHz and may be interrupted at any
time due to its synchronous behavior.
Input
SCK
Serial Input. All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet the power (IDD) specifications.
SI[1]
Serial Output. This is the data output pin. It is driven during a read and remains
tristated at all other times. Data transitions are driven on the falling edge of the
serial clock SCK.
Write Protect. This Active LOW pin prevents write operation to the Status Register
when WPEN bit in the Status Register is setto ‘1’. This is critical because other write
protection features are controlled through the Status Register. A complete
explanation of write protection is provided in “Status Register” on page 12 and
“Write protection” on page 13. This pin must be tied to VDD if not used.
SO[1]
WP
Output
Input
DNU
VSS
VDD
NC
Do Not Use Do Not Use. Either leave this pin floating (not connected on the board) or tie to VDD
.
Ground for the device. Must be connected to the ground of the system.
Power supply input to the device.
Power Supply
NC
No Connect. Die pads are not connected to the package pin.
Note
1. SI may be connected to SO for a single pin data interface.
Datasheet
5
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional overview
3
Functional overview
The CY15X108QN is a serial F-RAM memory. The memory array is logically organized as 1,048,576 × 8 bits and is
accessed using an industry-standard serial peripheral interface (SPI) bus. The functional operation of the F-RAM
is similar to serial flash and serial EEPROMs. The major difference between the CY15X108QN and a serial flash or
EEPROM with the same pinout is the F-RAM’s superior write performance, high endurance, and low power
consumption.
3.1
Memory architecture
When accessing CY15X108QN, the user addresses 1,024K locations of eight data bits each. These eight data bits
are shifted in or out serially. The addresses are accessed using the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an opcode, and a three-byte address. The upper four bits of the address
range are ‘don’t care’ values. The complete address of 20 bits specifies each byte address uniquely.
Most functions of the CY15X108QN are either controlled by the SPI interface or handled by on-board circuitry. The
access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. That is,
the memory is read or written at the speed of the SPI bus. Unlike a serial flash or EEPROM, it is not necessary to
poll the device for a ready condition because writes occur at bus speed. By the time a new bus transaction can
be shifted into the device, a write operation is complete. This is explained in more detail in the interface section.
3.2
SPI bus
The CY15X108QN is an SPI slave device and operates at speeds of up to 50 MHz. This high-speed serial bus
provides high-performance serial communication to an SPI master. Many common microcontrollers have
hardware SPI ports allowing a direct interface. It is simple to emulate the port using ordinary port pins for micro-
controllers that do not have this feature. The CY15X108QN operates in SPI Modes 0 and 3.
3.3
SPI overview
The SPI is a four-pin interface with chip select (CS), serial input (SI), serial output (SO), and serial clock (SCK) pins.
The SPI is a synchronous serial interface, which uses clock and data pins for memory access and supports
multiple devices on the data bus. A device on the SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes
0 and 3. In both of these modes, data is clocked into the F-RAM on the rising edge of SCK starting from the first
rising edge after CS goes active.
The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave
device. After CS is activated, the first byte transferred from the bus master is the opcode. Following the opcode,
any addresses and data are then transferred. The CS must go inactive after an operation is complete and before
a new opcode can be issued.
Datasheet
6
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional overview
3.4
Terms used in SPI protocol
The commonly used terms in the SPI protocol are as follows.
3.4.1
SPI master
The SPI master device controls the operations on the SPI bus. An SPI bus may have only one master with one or
more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices
using the CS pin. All of the operations must be initiated by the master activating a slave device by pulling the CS
pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are
synchronized with this clock.
3.4.2
SPI slave
The SPI slave device is activated by the master through the chip select line. A slave device gets the SCK as an input
from the SPI master and all the communication is synchronized with this clock. An SPI slave never initiates a
communication on the SPI bus and acts only on the instruction from the master.
The CY15X108QN operates as an SPI slave and may share the SPI bus with other SPI slave devices.
3.4.3
Chip Select (CS)
To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued
to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored
and the serial output pin (SO) remains in a high-impedance state.
Note A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each
active chip select cycle.
3.4.4
Serial Clock (SCK)
The serial clock is generated by the SPI master and the communication is synchronized with this clock after CS
goes LOW.
The CY15X108QN supports SPI modes 0 and 3 for data communication. In both of these modes, the inputs are
latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the
first rising edge of SCK signifies the arrival of the first most significant bit (MSb) of an SPI instruction on the SI pin.
Further, all data inputs and outputs are synchronized with SCK.
3.4.5
Data transmission (SI/SO)
The SPI data bus consists of two lines, SI and SO, for serial data communication. SI is also referred to as master
out slave In (MOSI) and SO is referred to as master in slave Out (MISO). The master issues instructions to the slave
through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO
lines as described earlier.
The CY15X108QN has two separate pins for SI and SO, which can be connected with the master as shown in
Figure 2. For a microcontroller that has no dedicated SPI bus, a general-purpose port may be used. To reduce
hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off
(HIGH) the WP pin. Figure 3 shows such a configuration, which uses only three pins.
Datasheet
7
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional overview
SCK
MOSI
MISO
SCK
SI
SO
SCK
SI
SO
SPI Hostcontroller
or
SPI Master
CY15x108QN
CY15x108QN
CS
WP
CS
WP
CS1
WP1
CS2
WP2
Figure 2
System configuration with SPI port
P1.0
P1.1
SCK
SI
SO
SPI Hostcontroller
or
CY15x108QN
SPI Master
CS
WP
P1.2
Figure 3
System configuration without SPI port
3.4.6
Most significant bit (MSb)
The SPI protocol requires that the first bit to be transmitted is the MSb. This is valid for both address and data
transmission.
The 8-Mbit serial F-RAM requires a 3-byte address for any read or write operation. Because the address is only 20
bits, the first four bits, which are fed in are ignored by the device. Although these four bits are ‘don’t care’, Infineon
recommends that these bits be set to 0s to enable seamless transition to higher memory densities.
3.4.7
Serial opcode
After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the
intended operation. CY15X108QN uses the standard opcodes for memory accesses.
3.4.8
Invalid opcode
If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI
pin until the next falling edge of CS, and the SO pin remains tristated.
3.4.9
Status register
CY15X108QN has an 8-bit Status Register. The bits in the Status Register are used to configure the device. These
bits are described in Table 4.
Datasheet
8
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional overview
3.5
SPI modes
CY15X108QN may be driven by a microcontroller with its SPI peripheral running in either of the following two
modes:
• SPI Mode 0 (CPOL = 0, CPHA = 0)
• SPI Mode 3 (CPOL = 1, CPHA = 1)
For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after
CS goes active. If the clock starts from a HIGH state (in Mode 3), the first rising edge after the clock toggles is
considered. The output data is available on the falling edge of SCK. The two SPI modes are shown in Figure 4 and
Figure 5. The status of the clock when the bus master is not transferring data is:
• SCK remains at 0 for Mode 0
• SCK remains at 1 for Mode 3
The device detects the SPI mode from the status of the SCK pin when the device is selected by bringing the CS
pin LOW. If the SCK pin is LOW when the device is selected, SPI Mode 0 is assumed and if the SCK pin is HIGH, it
works in SPI Mode 3.
CS
0
1
2
3
4
5
6
7
SCK
SI
7
6
5
4
3
2
1
0
Figure 4
SPI Mode 0
CS
0
1
2
3
4
5
6
7
SCK
7
6
5
4
3
2
1
0
SI
Figure 5
SPI Mode 3
3.6
Power-up to first access
The CY15X108QN is not accessible for a tPU time after power-up. Users must comply with the timing parameter,
t
PU, which is the minimum time from VDD (min) to the first CS LOW. Refer to “Power cycle timing” on page 30 for
details.
Datasheet
9
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4
Functional description
4.1
Command structure
There are 15 commands, called opcodes, that can be issued by the bus master to the CY15X108QN (see Table 2).
These opcodes control the functions performed by the memory.
Table 2
Name
Opcode commands
Description
Opcode
Max. frequency
(MHz)
Hex
Binary
Write enable control
WREN
Set write enable latch
06h
04h
0000 0110b
0000 0100b
50
50
WRDI
Reset write enable latch
Register access
RDSR
WRSR
Read Status register
Write Status register
05h
01h
0000 0101b
0000 0001b
50
50
Memory write
WRITE
Write memory data
02h
0000 0010b
50
Memory read
READ
FSTRD
Read memory data
Fast read memory data
03h
0Bh
0000 0011b
0000 1011b
35
50
Special sector memory access
SSWR
SSRD
Special sector write
Special sector read
42h
4Bh
0100 0010b
0100 1011b
50
35
Identification and serial number
RDID
RUID
WRSN
RDSN
Read device ID
Read unique ID
Write serial number
Read serial number
9Fh
4Ch
C2h
C3h
1001 1111b
0100 1100b
1100 0010b
11000 011b
50
50
50
50
Low power modes
DPD
HBN
Enter Deep Power-down
Enter Hibernate mode
BAh
B9h
1011 1010b
1011 1001b
50
50
Unused opcodes are reserved for
future use.
Reserved
Reserved
–
Datasheet
10
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4.1.1
Write Enable Control commands
Set Write Enable Latch (WREN, 06h)
4.1.1.1
The CY15X108QN will power up with writes disabled. The WREN command must be issued before any write
operation. Sending the WREN opcode allows the user to issue subsequent opcodes for write operations. These
include writing to the Status Register (WRSR), the memory (WRITE), Special Sector (SSWR), and Write Serial
Number (WRSN).
Sending the WREN opcode causes the internal write enable latch to be set. A flag bit in the Status Register, called
WEL, indicates the state of the latch. WEL = 1 indicates that writes are permitted. Attempting to write the WEL bit
in the Status Register has no effect on the state of this bit - only the WREN opcode can set this bit. The WEL bit
will be automatically cleared on the rising edge of CS following a WRDI, a WRSR, a WRITE, a SSWR, or a WRSN
operation. This prevents further writes to the Status Register or the F-RAM array without another WREN
command. Figure 6 illustrates the WREN command bus configuration.
CS
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
SI
SI
0
0
0
0
0
1
1
0
Hi-Z
Opcode (06h)
Figure 6
WREN bus configuration
4.1.1.2
Reset Write Enable Latch (WRDI, 04h)
The WRDI command disables all write activity by clearing the Write Enable Latch. Verify that the writes are
disabled by reading the WEL bit in the Status Register and verify that WEL is equal to ‘0’. Figure 7 illustrates the
WRDI command bus configuration.
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
Hi-Z
SI
Opcode (04h)
Figure 7
WRDI bus configuration
Datasheet
11
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4.1.2
Register Access commands
4.1.2.1
Status Register and Write Protection
The write protection features of the CY15X108QN are multi-tiered and are enabled through the Status Register.
The Status Register is organized as follows (The default value shipped from the factory for WEL, BP0, BP1, bits 4–
5, and WPEN is ‘0’, and for bit 6 is ‘1’).
Table 3
Bit 7
WPEN (0)
Status Register
Bit 6
X (1)
Bit 5
X (0)
Bit 4
X (0)
Bit 3
BP1 (0)
Bit 2
BP0 (0)
Bit 1
WEL (0)
Bit 0
X (0)
Table 4
Status Register bit definition
Bit
Bit 0
Definition
Don’t care
Description
This bit is non-writable and always returns ‘0’ upon read.
WEL indicates if the device is write enabled. This bit defaults to ‘0’
(disabled) on power-up.
Bit 1 (WEL)
Write enable
WEL = 1 --> Writeenabled
WEL = 0 --> Write disabled
Bit 2 (BP0)
Bit 3 (BP1)
Bit 4–5
Block protect bit ‘0’
Block protect bit ‘1’
Don’t care
Used for block protection. For details, see Table 5.
Used for block protection. For details, see Table 5.
These bits are non-writable and always return ‘0’ upon read.
This bit is non-writable and always returns ‘1’ upon read.
Bit 6
Don’t care
Used to enable the function of Write Protect Pin (WP).
For details, see Table 6.
Bit 7 (WPEN) Writeprotectenablebit
Bits 0 and 4–5 are fixed at ‘0’ and bit 6 is fixed at ‘1’; none of these bits can be modified. Note that bit 0 (“Ready or
Write in progress” bit in serial flash and EEPROM) is unnecessary, as the F-RAM writes in real-time and is never
busy, so it reads out as a '0'. An exception to this is when the device is waking up either from Deep Power-down
Mode (DPD, BAh) or “Hibernate Mode (HBN, B9h)” on page 19. The BP1 and BP0 control the software
write-protection features and are non-volatile bits. The WEL flag indicates the state of the write enable latch.
Attempting to directly write the WEL bit in the Status Register has no effect on its state. This bit is internally set
and cleared via the WREN and WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write-protected
as shown in Table 5.
Table 5
Block memory write protection
BP1
BP0
Protected address range
None
0x0C0000h to 0x0FFFFF (upper 1/4)
0x080000h to 0x0FFFFF (upper 1/2)
0x000000h to 0x0FFFFFh (all)
0
0
1
1
0
1
0
1
The BP1 and BP0 bits and the write enable latch are the only mechanisms that protect the memory fromwrites.
Theremaining writeprotectionfeaturesprotectinadvertentchangestotheblock protect bits.
The write protect enable bit (WPEN) in the Status Register controls the effect of the hardware write protect (WP)
pin. Refer to Figure 23 for the WP pin timing diagram. When the WPEN bit is set to ‘0’, the status of the WP pin is
ignored. When the WPEN bit is set to ‘1’, a LOW on the WP pin inhibits a write to the Status Register. Thus the Status
Register is write-protected only when WPEN = 1 and WP = 0. Table 6 summarizes the write protection conditions.
Datasheet
12
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
Table 6
Write protection
Protected blocks
WEL WPEN WP
Unprotected blocks
Protected
Status register
Protected
0
1
1
1
X
0
1
1
X
X
0
1
Protected
Protected
Protected
Protected
Unprotected
Unprotected
Unprotected
Unprotected
Protected
Unprotected
4.1.2.2
Read Status Register (RDSR, 05h)
The RDSR command allows the bus master to verify the contents of the Status Register. Reading the Status
Register provides information about the current state of the write-protection features. Following the RDSR
opcode, the CY15X108QN will return one byte with the contents of the Status Register.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
Hi-Z
0
0
0
0
0
1
0
1
Hi-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Opcode (05h)
Read Data
Figure 8
RDSR bus configuration
4.1.2.3
Write Status Register (WRSR, 01h)
The WRSR command allows the SPI bus master to write into the Status Register and change the write protect
configuration by setting the WPEN, BP0, and BP1 bits as required. Before issuing a WRSR command, the WP pin
must be HIGH or inactive. Note that on the CY15X108QN, WP only prevents writing to the Status Register, not the
memory array. Before sending the WRSR command, the user must send a WREN command to enable writes.
Executing a WRSR command is a write operation and therefore, clears the write enable latch.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Hi-Z
SO
Opcode (01h)
Write Data
Figure 9
WRSR bus configuration (WREN not shown)
Datasheet
13
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4.1.3
Memory operation
The SPI interface, which is capable of a high clock frequency, highlights the fast write capability of the F-RAM
technology. Unlike serial flash and EEPROMs, the CY15X108QN can perform sequential writes at bus speed. No
page register is needed and any number of sequential writes may be performed.
4.1.4
Memory Write Operation commands
Write Operation (WRITE, 02h)
4.1.4.1
All writes to the memory begin with a WREN opcode with CS being asserted and deasserted. The next opcode is
WRITE. The WRITE opcode is followed by a three-byte address containing the 20-bit address (A19–A0) of the first
data byte to be written into the memory. The upper four bits of the three-byte address are ignored. Subsequent
bytes are data bytes, which are written sequentially. Addresses are incremented internally as long as the bus
master continues to issue clocks and keeps CS LOW. If the last address of FFFFFh is reached, the internal address
counter will roll over to 00000h. Every data byte to be written is transmitted on SI in 8-clock cycles with MSb first
and the LSb last. The rising edge of CS terminates a write operation. The CY15X108QN write operation is shown
in Figure 10.
Notes
• When a burst write reaches a protected block address, the automatic address increment stops and all the subse-
quent data bytes received for write will be ignored by the device. EEPROMs use page buffers to increase their
write throughput. This compensates for the technology’s inherently slow write operations. F-RAM memories do
not have page buffers because each byte is written to the F-RAM array immediately after it is clocked in (after
the eighth clock). This allows any number of bytes to be written without page buffer delays.
• If power is lost in the middle of the write operation, only the last completed byte will be written.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
SCK
SI
A23 A22 A21 A20
A3
A2
A1 A0
0
0
0
0
0
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSb
LSb
Hi-Z
Hi-Z
SO
Opcode (02h)
Address
Write Data
Figure 10
Memory write (WREN not shown) operation
Datasheet
14
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4.1.5
Memory Read commands
4.1.5.1
Read Operation (READ, 03h)
After the falling edge of CS, the bus master can issue a READ opcode. Following the READ command is a three-byte
address containing the 20-bit address (A19–A0) of the first byte of the read operation. The upper four bits of the
address are ignored. After the opcode and address are issued, the device drives out the read data on the next
eight clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes, which are read out
sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and CS is
LOW. If the last address of FFFFFh is reached, the internal address counter will roll over to 00000h. Every read data
byte on SO is driven in 8-clock cycles with MSb first and the LSb last. The rising edge of CS terminates a read
operation and tristates the SO pin. The CY15X108QN read operation is shown in Figure 11.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
SCK
SI
Hi-Z
A23 A22 A21 A20
A3
A2
A1 A0
0
0
0
0
0
0
1
1
Hi-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Opcode (03h)
Address
Read Data
Figure 11
Memory read operation
4.1.5.2
Fast Read Operation (FAST_READ, 0Bh)
The CY15X108QN supports a FAST_READ opcode (0Bh) that is provided for opcode compatibility with serial flash
devices. The FAST_READ opcode is followed by a three-byte address containing the 20-bit address (A19–A0) of
the first byte of the read operation and then a dummy byte. The dummy byte inserts a read latency of 8-clock
cycle. The fast read operation is otherwise the same as an ordinary read operation except that it requires an
additional dummy byte. After receiving the opcode, address, and a dummy byte, the CY15X108QN starts driving
its SO line with data bytes, with MSb first, and continues transmitting as long as the device is selected and the
clock is available. In case of bulk read, the internal address counter is incremented automatically, and after the
last address FFFFFh is reached, the internal address counter rolls over to 00000h. When the device is driving data
on its SO line, any transition on its SI line is ignored. The rising edge of CS terminates a fast read operation and
tristates the SO pin. The CY15X108QN fast read operation is shown in Figure 12.
Note The dummy byte can be any 8-bit value but Axh (8’b1010xxxx). The lower 4 bits of Axh are don’t care bits.
Hence, Axh essentially represents 16 different 8-bit values which shouldn’t be transmitted as the dummy byte.
00h is typically used as the dummy byte in most use cases.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
Hi-Z
A23 A22 A21 A20
MSb
A3
A2
A1 A0
0
0
0
0
1
0
1
x
x
x
x
x
x
x
x
1
LSb
Hi-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSb
LSb
Opcode (0Bh)
Address
Dummy Byte
Read Data
Figure 12
Fast read operation
Datasheet
15
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4.1.6
Special Sector Memory Access commands
Special Sector Write (SSWR, 42h)
4.1.6.1
All writes to the 256-byte special begin with a WREN opcode with CS being asserted and deasserted. The next
opcode is SSWR. The SSWR opcode is followed by a three-byte address containing the 8-bit sector address (A7–
A0) of the first data byte to be written into the special sector memory. The upper 16 bits of the three-byte address
are ignored. Subsequent bytes are data bytes, which are written sequentially. Addresses are incremented inter-
nally as long as the bus master continues to issue clocks and keeps CS LOW. Once the internal address counter
auto increments to XXXFFh, CS should toggle HIGH to terminate the ongoing SSWR operation. Every data byte to
be written is transmitted on SI in 8-clock cycles with MSb first and the LSb last. The rising edge of CS terminates
a write operation. The CY15X108QN special sector write operation is shown in Figure 13.
Notes
• If power is lost in the middle of the write operation, only the last completed byte will be written.
• The special sector F-RAM memory guarantees to retain data integrity up to three cycles of standard reflow
soldering.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
SCK
SI
A23 A22 A21 A20
A3
A2
A1 A0
0
1
0
0
0
0
1
D7 D6
MSb
D5
D4 D3
D2
D1
D0
0
LSb
Hi-Z
Hi-Z
SO
Opcode (42h)
Address
Write Data
Figure 13
Special sector write (WREN not shown) operation
4.1.6.2
Special Sector Read (SSRD, 4Bh)
After the falling edge of CS, the bus master can issue an SSRD opcode. Following the SSRD command is a
three-byte address containing the 8-bit address (A7–A0) of the first byte of the special sector read operation. The
upper 16 bits of the address are ignored. After the opcode and address are issued, the device drives out the read
data on the next eight clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes,
which are read out sequentially. Addresses are incremented internally as long as the bus master continues to
issue clocks and CS is LOW. Once the internal address counter auto increments to XXXFFh, CS should toggle HIGH
to terminate the ongoing SSRD operation. Every read data byte on SO is driven in 8-clock cycles with MSb first
and the LSb last. The rising edge of CS terminates a special sector read operation and tristates the SO pin. The
CY15X108QN special sector read operation is shown in Figure 14.
Note The special sector F-RAM memory guarantees to retain data integrity up to three cycles of standard reflow
soldering.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
SCK
SI
Hi-Z
A23 A22 A21 A20
A3
A2
A1 A0
0
1
0
0
1
0
1
1
Hi-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Opcode (4Bh)
Address
Read Data
Figure 14
Special sector read operation
Datasheet
16
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4.1.7
Identification and Serial Number commands
Read Device ID (RDID, 9Fh)
4.1.7.1
The CY15X108QN device can be interrogated for its manufacturer, product identification, and die revision. The
RDID opcode 9Fh allows the user to read the 9-byte manufacturer ID and product ID, both of which are read-only
bytes. The JEDEC-assigned manufacturer ID places the Ramtron identifier in bank 7; therefore, there are six bytes
of the continuation code 7Fh followed by the single byte C2h. There are two bytes of product ID, which includes
a family code, a density code, a sub code, and the product revision code. Table 7 shows 9-Byte Device ID field
description. Refer to “Ordering information” on page 31 for 9-Byte device ID of an individual part. The
CY15X108QN read device ID operation is shown in Figure 15.
Note The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 8) shifts out
last.
Table 7
9-byte device ID
Device ID field description
Manufacturer ID
[71:16]
Family
[15:13]
Density
[12:9]
Inrush
[8]
Sub type
[7:5]
Revision
[4:3]
Voltage
[2]
Frequency
[1:0]
56-bit
3-bit
4-bit
1-bit
3-bit
2-bit
1-bit
2-bit
Refer to “Ordering information” on page 31 for 9-Byte device ID of an individual part.
CS
0
1
2
3
4
5
6
7
0
1
2
3
60 61 62 63 64 65 66 67 68 69 70 71
SCK
SI
Hi-Z
D4
1
0
0
1
1
1
1
1
MSb
D7
LSb
D0
Hi-Z
D6
D5
D4
D3
D2
D1 D0
SO
D7 D6
D5
D3
D2
D1
Byte 0
Byte 8
Opcode (9Fh)
9-Byte Device ID
Figure 15
Read device ID
4.1.7.2
Read Unique ID (RUID, 4Ch)
The CY15X102QN device can be interrogated for unique ID which is a factory programmed, 64-bit number unique
to each device. The RUID opcode, 4Ch allows to read the 8-byte, read only unique ID. The CY15X102QN read
unique ID operation is shown in Figure 16.
Notes
• The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 7) shifts out last.
• The unique ID registers are guaranteed to retain data integrity of up to three cycles of the standard reflow
soldering.
CS
0
1
2
3
4
5
6
7
0
1
2
3
52 53 54 55 56 57 58 59 60 61 62 63
SCK
SI
Hi-Z
0
1
0
0
1
1
0
0
MSb
D7
LSb
Hi-Z
D6
D5
D4
D3
D2
D1 D0
SO
D7 D6
D5
D4
D3
D2
D1
D0
Byte 0
Byte 7
Opcode (4Ch)
8-Byte Unique ID
Figure 16
Read unique ID
Datasheet
17
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4.1.7.3
Write Serial Number (WRSN, C2h)
The serial number is an 8-byte one-time programmable memory space provided to the user to uniquely identify
a PC board or a system. A serial number typically consists of a two-byte customer ID, followed by five bytes of a
unique serial number and one byte of CRC check. However, the end application can define its own format for the
8-byte serial number. All writes to the serial number register begin with a WREN opcode with CS being asserted
and deasserted. The next opcode is WRSN. The WRSN instruction can be used in burst mode to write all the
8 bytes of serial number. After the last byte of the serial number is shifted in, CS must be driven high to complete
the WRSN operation. The CY15X108QN write serial number operation is shown in Figure 17.
Note The CRC checksum is not calculated by the device. The system firmware must calculate the CRC checksum
on the 7-byte content and append the checksum to the 7-byte user-defined serial number before programming
the 8-byte serial number into the serial number register. The factory default value for the 8-byte Serial Number
is ‘0000000000000000h’.
Table 8
8-byte serial number
16-bit customer identifier
40-bit unique number
SN[39:32] SN[31:24] SN[23:16]
8-bit CRC
SN[7:0]
SN[63:56]
SN[55:48]
SN[47:40]
SN[15:8]
CS
0
1
2
3
4
5
6
7
0
1
2
3
52 53 54 55 56 57 58 59 60 61 62 63
SCK
D7
D6
D5
D4
D3
D2
D1
D0
SI
1
1
0
0
0
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
LSb
MSb
Hi-Z
Hi-Z
SO
Opcode (C2h)
Write 8-Byte Serial Number
Figure 17
Write serial number (WREN not shown) operation
4.1.7.4
Read Serial Number (RDSN, C3h)
The CY15X108QN device incorporates an 8-byte serial space provided to the user to uniquely identify the device.
The serial number is read using the RDSN instruction. A serial number read may be performed in burst mode to
read all the eight bytes at once. After the last byte of the serial number is read, the device loops back to the first
byte of the serial number. An RDSN instruction can be issued by shifting the opcode for RDSN after CS goes LOW.
The CY15X108QN read serial number operation is shown in Figure 18.
Note The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 7) shifts out
last.
CS
0
1
2
3
4
5
6
7
0
1
2
3
52 53 54 55 56 57 58 59 60 61 62 63
SCK
SI
Hi-Z
1
1
0
0
0
0
1
1
MSb
D7
LSb
Hi-Z
D6
D5
D4
D3
D2
D1 D0
SO
D7 D6
D5
D4
D3
D2
D1
D0
Byte 0
Byte 7
Opcode (C3h)
8-Byte Serial Number
Figure 18
Read serial number operation
Datasheet
18
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4.1.8
Low Power Mode commands
4.1.8.1
Deep Power-down Mode (DPD, BAh)
A power-saving Deep Power-down mode is implemented on the CY15X108QN device. The device enters the Deep
Power-down mode after tENTDPD time after the DPD opcode BAh is clocked in and a rising edge of CS is applied.
When in Deep Power-down mode, the SCK and SI pins are ignored and SO will be Hi-Z, but the device continues
to monitor the CS pin.
A CS pulse-width of tCSDPD exits the DPD mode after tEXTDPD time. The CS pulse-width can be generated either by
sending a dummy command cycle or toggling CS alone while SCK and I/Os are don’t care. The I/Os remain in hi-Z
state during the wakeup from deep power down. Refer to Figure 19 for DPD entry and Figure 20 for DPD exit
timing.
Enters DPD
tENTDPD
CS
0
1
2
3
4
5
6
7
SCK
SI
1
0
1
1
1
0
1
0
hi-Z
SO
Opcode (BAh)
Figure 19
DPD entry timing
tEXTDPD
tCSDPD
CS
0
1
2
SCK
tSU
X
I/Os
Figure 20
DPD exit timing
4.1.8.2
Hibernate Mode (HBN, B9h)
A lowest power Hibernate mode is implemented on the CY15X108QN device. The device enters Hibernate mode
after tENTHIB time after the HBN opcode B9h is clocked in and a rising edge of CS is applied. When in Hibernate
mode, the SCK and SI pins are ignored and SO will be Hi-Z, but the device continues to monitor the CS pin. On the
next falling edge of CS, the device will return to normal operation within tEXTHIB time. The SO pin remains in a Hi-Z
state during the wakeup from hibernate period. The device does not necessarily respond to an opcode within the
wakeup period. To exit the Hibernate mode, the controller may send a “dummy” read, for example, and wait for
the remaining tEXTHIB time.
Enters
Hibernate Mode
Recovers from
Hibernate Mode
tENTHIB
tEXTHIB
CS
0
1
2
3
4
5
6
7
0
1
2
SCK
tSU
SI
1
0
1
1
1
0
0
1
hi-Z
SO
Opcode (B9h)
Figure 21
Hibernate mode operation
Datasheet
19
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Functional description
4.1.8.3
Endurance
The CY15X108QN devices are capable of being accessed at least 1014 times, reads or writes.
An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a
row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows
and columns of 128K rows of 64-bit each. The entire row is internally accessed once, whether a single byte or all
eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. Table 9
shows endurance calculations for a 64-byte repeating loop, which includes an opcode, a starting address, and a
sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually unlimited at a 50-MHz clock rate.
Table 9
Time to reach endurance limit for repeating 64-byte loop
SCK freq. (MHz)
Endurance cycles/sec
Endurance cycles/year
2.9 × 1012
Years to reach 1014 limit
50
20
10
5
91,900
36,520
18,380
9,190
34.5
86.4
172.7
345.4
1.16 × 1012
5.79 × 1011
2.90 × 1011
Datasheet
20
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Maximum ratings
5
Maximum ratings
Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested.
Storage temperature
–65°C to +125°C
Maximum accumulated storage time:
At 125°C ambient temperature
At 105°C ambient temperature
1000 h
1 Year
Maximum junction temperature
125°C
Supply voltage on VDD relative to VSS
CY15V108QN
:
–0.5 V to +2.4 V
–0.5 V to +4.1 V
CY15B108QN
Input voltage
VIN VDD + 0.5 V
DC voltage applied to outputs in High-Z state
–0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns) on any pin to ground potential –2.0 V to VDD + 2.0 V
Package power dissipation capability (TA = 25°C)
Surface mount lead soldering temperature (3 seconds)
DC output current (1 output at a time, 1s duration)
1.0 W
+260°C
15 mA
Electrostatic discharge voltage human body model
(JEDEC Std JESD22-A114-B)
2 kV
Charged device model (JEDEC Std JESD22-C101-A)
Latch-up current
500 V
>140 mA
Datasheet
21
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Operating range
6
Operating range
Device
Range
Ambient temperature
VDD
CY15V108QN
CY15B108QN
1.71 V to 1.89 V
1.8 V to 3.6 V
Extended Industrial
–40°C to +105°C
Datasheet
22
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
DC electrical characteristics
7
DC electrical characteristics
Over the Operating range
[2, 3]
Parameter
Description
Test conditions
Min
1.71
1.80
Max
1.89
3.60
1.5
Unit
Typ
1.80
CY15V108QN
CY15B108QN
V
Power supply
V
DD
3.30
1.0
V
= 1.71 V to 1.89 V;
f
f
f
f
= 1 MHz
= 50 MHz
= 1 MHz
= 50 MHz
DD
SCK
SCK
SCK
SCK
SCK toggling between
– 0.2 V and V ,
V
DD
SS
5.5
1.0
6.0
7.5
2.0
8.0
other inputs V or
SS
V
– 0.2 V. SO = Open
DD
I
V
supply current
mA
DD
DD
V
= 1.8 V to 3.6 V;
DD
SCK toggling between
– 0.2 V and V , other
V
DD
SS
inputs V or V – 0.2 V.
SS
DD
SO = Open
V
= 1.71 V to 1.89 V; CS = V
.
.
.
DD
DD
9
300
305
68.8
76.4
6
–
All other inputs V or V
.
SS
DD
I
I
I
V
standby current
SB
DD
V
= 1.8 V to 3.6 V; CS = V
.
DD
DD
.
10
All other inputs V or V
SS
DD
V
= 1.71 V to 1.89 V; CS = V
DD
DD
1.10
1.4
All other inputs V or V
.
Deep power-down
current
SS
DD
DPD
HBN
V
= 1.8 V to 3.6 V; CS = V
.
DD
DD
.
All other inputs V or V
SS
DD
V
= 1.71 V to 1.89 V; CS = V
DD
DD
0.10
0.10
All other inputs V or V
.
µA
Hibernate mode
current
SS
DD
V
= 1.8 V to 3.6 V; CS = V
.
DD
DD
.
10
All other inputs V or V
SS
DD
Input leakage
current on I/O pins
except WP pin
–1
1
I
I
V
< V < V
IN DD
LI
SS
SS
Input leakage
current on WP pin
–100
–1
1
1
Output leakage
current
V
< V
< V
DD
LO
OUT
–
V
V
V
V
V
V
Input HIGH voltage
Input LOW voltage
0.7 × V
–0.3
2.4
V
+ 0.3
DD
IH
DD
–
I
0.3 × V
IL
DD
= –1 mA, V = 2.7 V
OH1
OH2
OL1
OL2
DD
OH
OH
OL
OL
Output HIGH voltage
Output LOW voltage
–
V
I
I
I
= –100 µA
V
– 0.2
DD
= 2 mA, V = 2.7 V
0.4
0.2
DD
–
= 150 µA
Notes
2. Typical values are at 25°C, V = V (typ).
DD
DD
3. This parameter is guaranteed by characterization; not tested in production.
Datasheet
23
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Data retention and endurance
8
Data retention and endurance
Parameter
Description
Data retention
Endurance
Test conditions
TA = 105°C
TA = 85°C
TA = 65°C
Over operating temperature
Min
1
10
160
1014
Max
Unit
Years
Cycles
TDR
–
NVC
8.1
Example of EXCELON™ F-RAM life time in an industrial application
An application does not operate under steady temperature for the entire lifespan and is often expected to
operate in multiple temperature environments throughout the application’s lifespan. Therefore, the
retention-specification for F-RAM in applications must be calculated cumulatively. An example calculation for a
multi-temperature thermal profile is provided in Table 10.
Table 10
Temp
(T)
Example of EXCELON™ F-RAM life time in an industrial application
Acceleration factor (A)[4]
System life time
for the profile
Time factor
Profile factor
(P)
with respect to TMAX
(A)
(t)
L(P)
T1 =
t1 = 0.02
A1 = 1
105ºC
1
LP = P LTMAX
------------------------------------------------------------------------------
P =
t1
t2
t3
t4
t5
t6
T2 = 95ºC
T3 = 85ºC
T4 = 75ºC
T5 = 55ºC
T6 = 25ºC
Note
t2 = 0.08
t3 = 0.10
t4 = 0.15
t5 = 0.30
t6 = 0.35
A2 = 3.22
A3 = 11.04
A4 = 40.66
------- ------- ------- ------- ------- -------
+
+
+
+
+
A1 A2 A3 A4 A6 A6
or
= 17.223
LP = 17.22 1year
or
A5 = 700.67
A6 = 102601.94
LP 17years
4. TMAX = Maximum operating temperature
Ea 1
1
------ --- -------------
–
T
TMAX
LT
-----------------------
A =
= e k
LTMAX
Where,
A = Acceleration factor due to changes in temperature
Ea = Data retention activation energy (eV)
k = Boltzmann's constant (8.617 × 10-5eV/K)
T = Product temperature in kelvin (K) within the F-RAM product specification
TMAX = Maximum operating temperature in kelvin (K)
Refer to AN232889 - EXCELON™ F-RAM system life expectancy calculation for more details.
Datasheet
24
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Capacitance
9
Capacitance
For all packages.
Parameter[5]
Description
Output pin capacitance (SO)
Input pin capacitance
Test conditions
Max
Unit
CO
CI
8
6
TA = 25 °C, f = 1 MHz, VDD = VDD (typ)
pF
Note
5. This parameter is guaranteed by characterization; not tested in production.
Datasheet
25
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Thermal resistance
10
Thermal resistance
24-ball FBGA
package
Parameter[6]
Description
Test conditions
Unit
Thermal resistance
JA
JC
46.4
31.7
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
(junction to ambient)
°C/W
Thermal resistance
(junction to case)
Note
6. This parameter is guaranteed by characterization; not tested in production.
Datasheet
26
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
AC test conditions
11
AC test conditions
Input pulse levels
10% and 90% of VDD
Input rise and fall times
3 ns
Input and output timing reference levels
Output load capacitance
0.5 × VDD
30 pF
Datasheet
27
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
AC test conditions
12
AC switching characteristics
Over the Operating range
Parameters[7]
Parameter
35 MHz
Min Max
50 MHz
Description
Unit
Alt. parameter
Min
Max
fSCK
tCH
tCL
SCK clock frequency
Clock HIGH time
0
13
13
0
5
5
35
0
9
50
MHz
–
Clock LOW time
Clock LOW to Output low-Z
Chip select setup
Chip select hold - SPI Mode 0
Chip select hold - SPI Mode 3
Output disable time
Output data valid time
Output hold time
9
0
5
5
8]
[
tCLZ
tCSS
tCSH
–
–
tCSU
tCSH
–
tCSH1
tHZCS
tCO
10
10
9 10]
[ ,
12
9
10
8
tOD
tODV
–
tD
tSU
tH
–
–
ns
tOH
1
40
5
1
40
5
tCS
tSD
Deselect time
Data setup time
Data hold time
–
–
tHD
5
5
tWPS
tWPH
tWHSL
tSHWL
WP setup time (w.r.t CS)
WP hold time (w.r.t CS)
20
20
20
20
Notes
7. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse
levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30-pF load capacitance shown in
“AC test conditions” on page 27.
8. Guaranteed by design.
9. tHZCS is specified with a load capacitance of 5 pF. Transition is measured when the output enters a
high-impedance state.
10.This parameter is guaranteed by characterization; not tested in production.
Datasheet
28
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
AC test conditions
tCS
CS
tCSS
tCH
tCL
tCSH1
tCSH
Mode 3
Mode 0
SCK
SI
tSD
tHD
X
X
VALID DATA IN
tCO
tOH
tHZCS
tCLZ
Hi-Z
Hi-Z
SO
X
DATA OUT
X
Figure 22
Synchronous data timing (Mode 0 and Mode 3)
tWPS
tWPH
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Hi-Z
SO
Opcode (01h)
Write Data
Figure 23
Write protect timing during write status register (WRSR) operation
Datasheet
29
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Power cycle timing
13
Power cycle timing
Over the Operating range
Parameters[11]
Description
Min
Max
Unit
Alt.
Parameter
parameter
tPU
Power-up VDD(min) to first access (CS LOW)
VDD power-up ramp rate
VDD power-down ramp rate
CS high to enter Deep Power-down
(CS high to Hibernate mode current)
CS pulse width to wake up from Deep Power-down
mode
450
30
20
µs
12
[
]
–
–
3
tVR
µs/V
12 13
,
[
]
tVF
14
[
]
–
tENTDPD
tDP
–
tCSDPD
0.015 4 1/fSCK
Recovery time from Deep Power-down mode
(CS low to ready for access)
Time to enter hibernate
(CS high to enter Hibernate mode current)
13
µs
tEXTDPD
tRDP
–
15
]
[
–
3
tENTHIB
Recovery time from Hibernate mode
(CS low to ready for access)
Low VDD where initialization must occur
VDD(low) time when VDD(low) at 0.6 V
15
[
]
450
tEXTHIB
VDD(low)[
tREC
13
]
0.6
130
70
V
–
–
13
[
]
tPD
µs
VDD(low) time when VDD(low) at VSS
VDD
VDD
VDD (max)
No Device Access
Allowed
VDD (max)
VDD (min)
Device Access
Allowed
tVF tVR
VDD (min)
tVR
tPU
Device Access
Allowed
tPU
VDD (low)
tPD
Time
Time
Figure 24
Power cycle timing
Notes
11.Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse
levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30-pF load capacitance shown in
“AC test conditions” on page 27.
12.Slope measured at any point on the VDD waveform.
13.This parameter is guaranteed by characterization; not tested in production.
14.Guaranteed by design. Refer to Figure 19 for Deep Power Down mode timing.
15.Guaranteed by design. Refer to Figure 21 for Hibernate mode timing.
Datasheet
30
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Ordering information
14
Ordering information
Ordering code
Device ID
Package diagram
Package type
Operating range
CY15B108QN-50BKXQ
CY15B108QN-50BKXQT
CY15V108QN-50BKXQ
CY15V108QN-50BKXQT
7F7F7F7F7F7FC22E20
Extended industrial
(Q)
001-97209
24-ball FBGA
7F7F7F7F7F7FC22E24
All these parts are Pb-free. Contact your local Infineon sales representative for availability of these parts.
14.1
Ordering code definitions
CY 15 B 108 Q
- 50 BK
X
Q
T
N
Options:
Blank = Standard; T = Tape and reel
Temperature range:
Q = Extended Industrial (-40°C to +105°C)
X = Pb-free
Package type:
BK = 24-ball FBGA
Frequency:
50 = 50 MHz
N = No Inrush current control
Interface: Q = SPI F-RAM
Density: 108 = 8-Mbit
Voltage:
B = 1.8 V to 3.6 V
V = 1.71 V to 1.89 V
15 = F-RAM
CY = CYPRESS (An Infineon company)
Datasheet
31
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Package diagram
15
Package diagram
TOP VIEW
BOTTOM VIEW
4.00 BSC
SIDE VIEW
8.00 BSC
4.00 BSC
6.00 BSC
1.00 BSC
Ø0.40 0.0ꢀ
0.20 MIN
PIN A1
CORNER
PIN A1
CORNER
1.20 MAX
0.10
C
NOTES:
1. REFERENCE JEDEC # MO-216
2. ALL DIMENSIONS ARE IN MILLIMETERS
001-97209 *A
Figure 25
24L FBGA 8 6 1.2 mm BK24A package outline, 001-97209
Datasheet
32
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Acronyms
16
Acronyms
Table 11
Acronym
CPHA
CPOL
EEPROM
EIA
Acronyms used in this document
Description
Clock phase
Clock polarity
Electrically erasable programmable read-only memory
Electronic Industries Alliance
Fine-pitch ball grid array
Ferroelectric random access memory
Fast SPI
FBGA
F-RAM
FSPI
I/O
Input/output
JEDEC
JESD
LSb
Joint Electron Devices Engineering Council
JEDEC standards
Least significant bit
MSb
Most significant bit
RoHS
SPI
Restriction of hazardous substances
Serial peripheral interface
Datasheet
33
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Document conventions
17
Document conventions
17.1
Table 12
Symbol
°C
Units of measure
Units of measure
Unit of measure
degree Celsius
hertz
Hz
kHz
k
kilohertz
kilohm
Mbit
MHz
µA
µF
µs
mA
ms
ns
megabit
megahertz
microampere
microfarad
microsecond
milliampere
millisecond
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Datasheet
34
002-32520 Rev. *B
2022-09-01
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
Serial (SPI), 1024K × 8, 50 MHz, extended industrial
Revision history
Revision history
Document
Date
Description of changes
revision
*B
2022-09-01
Publish to web.
Datasheet
35
002-32520 Rev. *B
2022-09-01
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-09-01
Published by
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
Technologies in
authorized
a written document signed by
Do you have a question about this
document?
Go to www.infineon.com/support
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of the
product or any consequences of the use thereof can
reasonably be expected to result in personal injury.
Document reference
002-32520 Rev. *B
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
相关型号：
©2020 ICPDF网 联系我们和版权申明