CY7C65214D-32LTXI [INFINEON]
USB-SPI dual channel bridge with 6 GPIOs,;
| 型号： | CY7C65214D-32LTXI |
| 厂家： | 
Infineon |
| 描述： | USB-SPI dual channel bridge with 6 GPIOs, |
| 文件： | 总36页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CY7C65214D
USB-Serial Dual Channel SPI Bridge
CY7C65214D, USB-Serial Dual Channel (SPI) Bridge with BCD
■ Clocking: Integrated 48-MHz clock oscillator
■ Supports bus-/self-powered configurations
Features
■ USB 2.0 compliant, Full-Speed (12 Mbps)
■ USB suspend mode for low power
■ Operating voltage: 1.71 to 5.5 V
❐ Support for communication driver class (CDC), personal
health care device class (PHDC), and vendor device class
❐ Battery charger detection (BCD) compliant with USB Battery
Charging Specification Rev 1.2 (Peripheral Detect only)
❐ Integrated USB termination resistors
■ Two-channel configurable SPI interfaces
❐ Data rate up to 3 MHz for SPI master and 1 MHz for SPI slave
❐ Data width: 4 bits to 16 bits
■ Operating temperature
❐ Commercial: 0 °C to 70 °C
❐ Industrial: -40 °C to 85 °C
■ ESD protection: 2.2 kV HBM
❐ 256 bytes for each transmit and receive buffer per channel
❐ Supports Motorola, TI, and National SPI modes
■ Two-channel configurable SPI interfaces
❐ Data rate up to 3 MHz for SPI master and 1 MHz for SPI slave
❐ Data width: 4 bits to 16 bits
■ RoHS compliant package
❐ 32-pin QFN (5 × 5 × 1 mm. 0.5 mm pitch)
■ Ordering part number
❐ CY7C65214D
❐ 256 bytes for each transmit and receive buffer per channel
❐ Supports Motorola, TI, and National SPI modes
Applications
■ General-purpose input/output (GPIO) pins: 8
■ Configuration utility (Windows) to configure the following:
❐ Vendor ID (VID), Product ID (PID), and Product and
Manufacturer descriptors
❐ SPI
❐ Charger detection
❐ GPIO
■ Medical/healthcare devices
■ Point-of-Sale (POS) terminals
■ Test and measurement system
■ Gaming systems
■ Set-top box PC-USB interface
■ Industrial
■ Driver support for VCOM and DLL
❐ Windows 10: 32- and 64-bit versions
❐ Windows 8.1: 32- and 64-bit versions
❐ Windows 8: 32- and 64-bit versions
❐ Windows 7: 32- and 64-bit versions
❐ Windows Vista: 32- and 64-bit versions
❐ Windows XP: 32- and 64-bit versions
❐ Mac OS-X: 10.6, and later versions
❐ Linux: Kernel version 2.6.35 onwards
■ Networking
■ Enabling USB connectivity in legacy peripherals
USB Compliant
The USB Dual-Channel SPI Bridge Controller is fully compliant with USB2.0 specification and Battery
Charging Specification v1.2.
Cypress Semiconductor Corporation
Document Number: 002-31604 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 1, 2020
CY7C65214D
USB Serial Bridge Controller Family
USB Serial bridge Controllers are a family of configurable products for most common applications requiring no firmware changes.
Configuration utility is provided to Configure USB-VID, USB-PID, USB Product and Manufacturer Descriptors. The same configuration
utility can be used to configure UART, I2C, SPI, Battery Charger Detection, GPIOs, Power mode, and so on.
Figure 1. USB Serial Bridge Controller Family
CY7C65211
24-QFN 10 GPIO
Configurable as:
USB-SPI
CY7C65223
24-QFN 4 GPIO
RS485 Support
S/W and H/W Flow
Control
USB-I2C
USB-UART
H/W Flow Control
CY7C65213A
32-QFN 8 GPIO
RS485 Support
S/W and H/W Flow
Control
CY7C652148
24-QFN
6 GPIO
CY7C65216
24-QFN
8 GPIO
Single Channel
CY7C65211A
24-QFN 10 GPIO
Configurable as:
USB-SPI
CY7C65213
32-QFN 8 GPIO
RS485 Support
H/W Flow Control
USB-I2C
USB-UART
H/W Flow Control
CY7C65215
32-QFN 17 GPIO*
Configurable as:
USB-SPI
USB-I2C
USB-UART
H/W Flow Control
CY7C65223D
32-QFN 4 GPIOs
RS485 Support
S/W and H/W Flow
Control
CY7C65214D
32-QFN
8 GPIO
CY7C65216D
32-QFN
12 GPIO
Dual Channel
CY7C65215A
32-QFN 17 GPIO*
Configurable as:
USB-SPI
USB-I2C
USB-UART
RS485 Support
H/W Flow Control
USB-I2C
Bridge Controller
USB-Serial Configurable
Bridge Controller
USB-UART
Bridge Controller
USB-SPI
Bridge Controller
Document Number: 002-31604 Rev. **
Page 2 of 35
CY7C65214D
Table 1. USB Serial Family Feature Comparison
# of
USB-UART
USB-SPI
USB-I2C
Software Hardware
SPI Serial
Data
MPN
GPIO
RS485
UART
Pins**
SPI Master/ I2C Master/
Channels
Flow
Control
Flow
Control
Support
Slave
Slave
Width (bit)
CY7C65213
CY7C65213A
CY7C65223
CY7C65223D
CY7C652148
CY7C65214D
CY7C65216
CY7C65216D
CY7C65211
CY7C65211A
CY7C65215
1
1
1
2
1
2
1
2
1
1
2
2
8
8
N
Y
Y
Y
–
N
N
Y
Y
–
Y
Y
Y
Y
–
8
–
–
–
–
–
–
–
–
–
8
–
4
2 / 4 / 6
–
4
2 / 4 / 6 / 8
–
6
–
4-16 bits Master/Slave
–
8
–
–
–
–
4-16 bits Master/Slave
–
8
–
–
–
–
–
–
–
–
Master/Slave
Master/Slave
12
10*
10*
17*
17*
–
–
–
–
N
Y
N
Y
N
N
N
N
Y
Y
Y
Y
2 / 4 / 6
2 / 4 / 6
2 / 4 / 6
4-16 bits Master/Slave Master/Slave
4-16 bits Master/Slave Master/Slave
4-16 bits Master/Slave Master/Slave
CY7C65215A
2 / 4 / 6 / 8 4-16 bits Master/Slave Master/Slave
Legend
2
* Represents the total GPIO count offered by the part. This count can dynamically change based on UART / SPI / I C pin configuration.
** UART Pins
**UART Pins
UART Signal
2
4
6
8
RxD and TxD
RxD, TxD, RTS#, CTS#
RxD, TxD, RTS#, CTS#, DTR#, DSR#
RxD, TxD, RTS#, CTS#, DTR#, DSR#, DCD#, RI#
Document Number: 002-31604 Rev. **
Page 3 of 35
CY7C65214D
Table 2. Default Serial Channel Configuration
# of
USB- UART
USB-SPI
USB-I2C
USB
Protocol
SPI Master/ I2C Master/
MPN
GPIO
Is RS485
Channels
UART Pins
Enabled
Slave
Slave
CY7C65213
CY7C65213A
CY7C65223
CY7C65223D
CY7C652148
CY7C65214D
CY7C65216
CY7C65216D
CY7C65211
CY7C65211A
CY7C65215
CY7C65215A
1
1
1
2
1
2
1
2
1
1
2
2
4
4
CDC**
CDC**
N
N
Y
Y
8
8
4
4
–
–
–
–
6
6
6
6
–
–
–
–
–
–
–
–
4
CDC**
4
CDC**
6
Vendor***
Vendor***
Vendor***
Vendor***
CDC**
–
–
Master
–
8
Master
–
8
–
–
–
–
–
–
–
Slave
12
3
–
Master
N
N
N
N
–
–
–
–
3
CDC**
4
CDC**
4
CDC**
** USB CDC Protocol allows the USB host Operating System to detect the device as Virtual COM Port Device.
*** USB Vendor Protocol allows the USB host operating system to detect the device as general USB device. This device is accessible using Cypress Application Library.
Document Number: 002-31604 Rev. **
Page 4 of 35
CY7C65214D
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly
and effectively integrate the device into your design. For a comprehensive list of resources, see the document USB-Serial Bridge
Controller Product Overview.
■ Overview: USB Portfolio, USB Roadmap
■ Code Examples: USB Full-Speed
■ USB2.0 ProductSelectors:USB-SerialBridge Controller, USB
■ Development Kits:
to UART Controller (Gen I)
❐ CYUSBS232, Cypress USB-UART LP Reference Design Kit
❐ CYUSBS234, Cypress USB-Serial (Single Channel)
■ Knowledge Base Articles: Cypress offers a large number of
USB knowledge base articles covering a broad range of topics,
from basic to advanced level. Recommended knowledge base
articles for getting started with USB-Serial Bridge Controller
are:
Development Kit
❐ CYUSBS236, Cypress USB-Serial (Dual Channel)
Development Kit
■ Models: IBIS
❐ KBA85909 – Key Features of the Cypress® USB-Serial
Bridge Controller
❐ KBA85920 – USB-UART and USB-Serial
❐ KBA85921 – Replacing FT232R with CY7C65213
USB-UART LP Bridge Controller
❐ KBA85913 – Voltage supply range for USB-Serial
❐ KBA89355 – USB-Serial: Cypress Default VID and PID
❐ KBA92641 – USB-Serial Bridge Controller Managing I/Os
using API
❐ KBA92442– Non-Standard Baud Rates inUSB-Serial Bridge
Controllers
❐ KBA91366 – Binding a USB-Serial Device to a
Microsoft® CDC Driver
❐ KBA92551 – Testing a USB-Serial Bridge Controller
Configured as USB-UART with Linux®
❐ KBA91299 – Interfacing an External I2C Device with the
CYUSBS234/236 DVK
For a complete list of knowledge base articles, click here.
Document Number: 002-31604 Rev. **
Page 5 of 35
CY7C65214D
Block Diagram
nXRES
Reset
SCB0
8 Bytes
Tx FIFO
Internal
48 MHz OSC
VDDD
VCCD
Voltage
Regulator
Channel 0 SPI
SPI
SPI
Internal
32 KHz OSC
8 Bytes
RX FIFO
USB
VBUS Regulator
VBUS
SCB1
8 Bytes
Tx FIFO
Memory
SIE
Battery Charger
Detection
USBDP
Channel 1 SPI
GPIO
8 Bytes
RX FIFO
USBDM
GND
32 KB
Flash
USB Transceiver
with Integrated
Resistor
512
Bytes
Memory
GPIO
Document Number: 002-31604 Rev. **
Page 6 of 35
CY7C65214D
Contents
Functional Overview ........................................................8
USB and Charger Detect .............................................8
Serial Communication .................................................8
GPIO Interface ............................................................8
Default Configuration ...................................................8
Memory .......................................................................8
System Resources ......................................................8
Suspend and Resume .................................................9
WAKEUP .....................................................................9
Software ......................................................................9
Internal Flash Configuration ......................................10
Electrical Specifications ................................................11
Absolute Maximum Ratings .......................................11
Operating Conditions .................................................11
Device Level Specifications .......................................11
GPIO .........................................................................12
nXRES .......................................................................13
SPI Specifications .....................................................14
Flash Memory Specifications ....................................16
Pin Description ...............................................................17
USB Power Configurations ............................................21
USB Bus-Powered Configuration ..............................21
Self-Powered Configuration ......................................22
USB Bus Powered with Variable I/O Voltage ............23
Application Examples ....................................................24
USB-to-Dual SPI Bridge with Battery-Charge
Detection ...................................................................24
USB to Dual Channel (SPI) Bridge ............................26
Ordering Information ......................................................31
Ordering Code Definitions .........................................31
Package Information ......................................................32
Acronyms ........................................................................33
Document Conventions .................................................33
Units of Measure .......................................................33
Document History Page .................................................34
Sales, Solutions, and Legal Information ......................35
Worldwide Sales and Design Support .......................35
Products ....................................................................35
PSoC® Solutions ......................................................35
Cypress Developer Community .................................35
Technical Support .....................................................35
Document Number: 002-31604 Rev. **
Page 7 of 35
CY7C65214D
Charger Detection
Functional Overview
CY7C65214D supports BCD for Peripheral Detect only and
complies with the USB Battery Charging Specification Rev. 1.2.
It supports the following charging ports:
The CY7C65214D is a Full-Speed USB controller that enables
seamless PC connectivity for peripherals with dual-channel SPI
serial interface. CY7C65214D also integrates BCD, which is
compliant with the USB Battery Charging Specification Rev. 1.2.
It integrates a voltage regulator, oscillator, and flash memory for
storing configuration parameters, offering a cost-effective
■ Standard Downstream Port (SDP): allows the system to draw
up to 500 mA current from the host
■ Charging Downstream Port (CDP): allows the system to draw
up to 1.5 A current from the host
solution.
CY7C65214D
supports
bus-powered
and
self-powered modes, and enables efficient system power
management with suspend and remote wake-up signals. It is
available in a 32-pin QFN package.
■ Dedicated Charging Port (DCP): allows the system to draw up
to 1.5 A of current from the wall charger
Serial Communication
USB and Charger Detect
CY7C65214D has two serial communication blocks (SCBs).
Each SCB can implement an SPI interface. A 256-byte buffer is
available in both the TX and RX lines.
USB
CY7C65214D has a built-in USB 2.0 Full-Speedtransceiver. The
transceiver incorporates the internal USB series termination
resistors on the USB data lines and a 1.5-k pull-up resistor on
USBDP.
Table 3 shows maximum speed supported on both SCBs when
they are configured as SPI.
Table 3. Maximum Speed supported on both SCBs
No.
1
Configuration
SCB0 Maximum Speed
3M (Both TX and RX)
1M (Both TX and RX)
1M (Both TX and RX)
SCB1 Maximum Speed
SCB0 = SPI Master, SCB1 = Disabled
SCB0 = SPI Slave, SCB1 = Disabled
SCB0 = SPI, SCB1 = SPI
NA
NA
2
3
1M (Both TX and RX)
SPI Interface
Memory
The SPI interface supports SPI Master and SPI Slave. This
interface supports the Motorola, TI, and National Microwire
protocols. The maximum frequency of operation is 3 MHz in SPI
master mode and 1 MHz in SPI slave mode. It can support
transaction sizes ranging from 4 bits to 16 bits in length, SPI
slave supports 4 bits to 8 bits and 12 bits to 16 bits data width at
1 MHz operation. Whereas, it supports 9 bits,10 bits and 11 bits
data width operation at 500 kHz operation (for more details, refer
to USB to Dual Channel (SPI) Bridge on page 26).
CY7C65214D has a 512-byte flash. The flash is used to store
the USB parameters such as VID/PID, serial number, Product,
and Manufacturer Descriptors, which can be programmed by the
configuration utility.
System Resources
Power System
CY7C65214D supports theUSB Suspend mode to control power
usage. CY7C65214D operates in bus-powered or self-powered
modes over a range of 3.15 to 5.5 V.
GPIO Interface
CY7C65214D has eight GPIOs. The configuration utility allows
configuration of the GPIO pins. The configurable options are as
follows:
Clock System
CY7C65214D has a fully integrated clock and does not require
any external components. The clock system is responsible for
providing clocks to all subsystems.
■ TRISTATE: GPIO tristated through Config utility
■ DRIVE 1: Output static 1
Internal 48-MHz Oscillator
■ DRIVE 0: Output static 0
The internal 48-MHz oscillator is the primary source of internal
clocking in CY7C65214D.
■ POWER#: Power control for bus power designs
■ TXLED#: Drives LED during USB transmit
■ RXLED#: Drives LED during USB receive
■ TX or RX LED#: Drives LED during USB transmit or receive
GPIO can be configured to drive LED at 8-mA drive strength.
Internal 32-kHz Oscillator
The internal 32-kHz oscillator is primarily used to generate
clocks for peripheral operation in the USB Suspend mode.
Reset
■ BCD0/BCD1: Two-pin output to indicate the type of USB
charger
The reset block ensures reliable power-on reset and brings the
device back to the default known state. The nXRES (active low)
pin can be used by external devices to reset the CY7C65214D.
■ BUSDETECT: Connects VBUS pin for USB host detection
Default Configuration
CY7C65214D is configured as Dual SPI Master device.
Document Number: 002-31604 Rev. **
Page 8 of 35
CY7C65214D
Drivers for Windows Operating Systems
Suspend and Resume
For Windows operating systems (XP, Vista, Win7, Win8, Win8.1,
and Win10), Cypress delivers a User Mode dynamically linked
library–CyUSBSerial DLL–that abstracts vendor-specific
interface of CY7C65214D devices and provides convenientAPIs
to the user. It provides interface APIs for vendor-specific SPI and
class-specific APIs for PHDC.
The CY7C65214D device asserts the SUSPEND pin when the
USB bus enters the suspend state. This helps in meeting the
stringent suspend current requirement of the USB 2.0 specifi-
cation, while using the device in bus-powered mode. The device
will resume from the suspend state under any of the following
conditions:
1. Any activity is detected on the USB bus
USB-SPI Bridge Controller works with Cypress provided USB
vendor class driver. The Cypress Windows drivers are MS logo
certified drivers.
2. The WAKEUP pin is asserted to generate remote wakeup to
the host
These drivers will bind to device through WU (Windows Update)
services.
WAKEUP
The WAKEUP pin is used to generate a remote wakeup signal
on the USB bus. The remote wakeup signal is sent only if the
host enables this feature through the SET_FEATURE request.
The device communicates support for the remote wakeup to the
host through the configuration descriptor during the USB
enumeration process. The CY7C65214D device allows
enabling/disabling and polarity of the remote wakeup feature
through the configuration utility.
Cypress drivers also support Windows plug-and-play and power
management and USB Remote Wake-up.
Device Configuration Utility (Windows Only)
A Windows-based configuration utility is available to configure
various device initialization parameters. This graphical user
application provides an interactive interface to define the various
boot parameters stored in the device flash.
This utility allows the user to save a user-selected configuration
to text or xml formats. It also allows users to load a selected
configuration from text or xml formats. The configuration utility
allows the following operations:
Software
Cypress delivers a complete set of software drivers and the
configuration utility to enable product configuration during
system development.
■ View current device configuration
Drivers for Linux Operating Systems
■ Select and configure SPI, battery charging, and GPIOs
■ Configure USB VID, PID, and string descriptors
■ Save or Load configuration
Cypress provides a User Mode USB driver library (libcyusb-
serial.so) that abstracts vendor commands for the SPI interface
and provides a simplified API interface to the user applications.
This library makes use of the standard open source libUSB
library to enable the USB communication. The Cypress serial
library supports the USB plug-and-play feature using the Linux
‘udev’ mechanism.
You can download the free configuration utility and drivers from
www.cypress.com.
CY7C65214D USB device will bind to the native Linux Kernel
driver. User can use cypress provided application library for
accessing the USB-SPI device and thereby perform SPI
transactions.
Drivers for Mac OSx
Cypress delivers
a
dynamically linked shared library
(CyUSBSerial.dylib) based on libUSB, which enables
communication to the CY7C65214D device.
CY7C65214D USB device binds to native MAC OSx driver.
There is no special driver is required.
Document Number: 002-31604 Rev. **
Page 9 of 35
CY7C65214D
Internal Flash Configuration
The internal flash memory can be used to store the configuration parameters shown in the following table. A free configuration utility
is provided to configure the parameters listed in the table to meet application specific requirements over USB interface. The configu-
ration utility can be downloaded from www.cypress.com/usbserial.
Table 4. Internal Flash Configuration for both CY7C65214D
Parameter
USB Configuration
USB Vendor ID (VID)
USB Product ID (PID)
Manufacturer string
Product string
Default Value
Description
0x04B4
0x0005
Cypress
Default Cypress VID. Can be configured to customer VID
Default Cypress PID. Can be configured to customer PID
Can be configured with any string up to 64 characters
USB-Serial (Dual Channel) Can be configured with any string up to 64 characters
Can be configured with any string up to 64 characters
Serial string
Power mode
Bus powered
Can be configured to bus-powered or self-powered mode
Can be configured to any value from 0 to 500 mA. Based on this, the
configuration descriptor will be updated.
Max current draw
100 mA
Remote wakeup
Enabled
Vendor
Can be disabled. Remote wakeup is initiated by asserting WAKEUP pin
Can be configured to function in CDC, PHDC, or Cypress vendor class
USB interface protocol
Charger detect is disabled by default. When BCD is enabled, three of the
GPIOs must be configured for BCD
BCD
Disabled
Document Number: 002-31604 Rev. **
Page 10 of 35
CY7C65214D
Electrical Specifications
Static discharge voltage ESD protection levels:
Absolute Maximum Ratings
Exceeding maximum ratings [1] may shorten the useful life of the
device.
■ 2.2-kV HBM per JESD22-A114
Latch-up current ...................................................... 140 mA
Current per GPIO ...................................................... 25 mA
Storage temperature ......................... ...... –55 °C to +100 °C
Ambient temperature with
Operating Conditions
power supplied (Industrial) ................. ...... –40 °C to +85 °C
Supply voltage to ground potential
VDDD ............................................................................. 6.0 V
TA (ambient temperature under bias)
Industrial ................................................... –40 °C to +85 °C
VBUS ............................................................................. 6.0 V
VCCD ...........................................................................1.95 V
VGPIO .......................................................... .....VDDD + 0.5 V
V
BUS supply voltage ................................... 3.15 V to 5.25 V
VDDD supply voltage ................................... 1.71 V to 5.50 V
CCD supply voltage ................................... 1.71 V to 1.89 V
V
Device Level Specifications
All specifications are valid for –40 °C TA 85 °C, TJ 100 °C, and 1.71 V to 5.50 V, except where noted.
Table 5. DC Specifications
Parameter
Description
VBUS supply voltage
Min
Typ
Max
Units
Details/Conditions
3.15
3.30
3.45
V
Set and configure correct voltage
range using the configuration
VBUS
4.35
1.71
5.00
1.80
5.25
1.89
V
V
utility for VBUS
.
Used to set I/O and core voltage.
Set and configure correct voltage
range using the configuration
VDDD
VDDD supply voltage
2.0
3.3
5.5
V
utility for VDDD
.
Do not use this supply to drive
external device.
• 1.71 V VDDD 1.89 V: Short
the VCCD pin with the VDDD pin
VCCD
Output voltage (for core logic)
–
1.80
–
V
• VDDD > 2 V – connect a 1-µF
capacitor (Cefc) between the
VCCD pin and ground.
Cefc
IDD1
External regulator voltage bypass
Operating supply current
1.00
–
1.30
13
1.60
18
µF
X5R ceramic or better
USB 2.0 FS,
no GPIO switching at
VBUS = 5 V, VDDD = 5 V
mA
Does not include current through
a pull-up resistor on USBDP.
In USB suspend mode, the D+
voltage can go up to a maximum
of 3.8 V.
IDD2
USB Suspend supply current
–
5
–
µA
Table 6. AC Specifications
Parameter
Description
Min
28
–
Typ
–
Max
44
–
Units
Details/Conditions
Zout
USB driver output impedance
–
–
Twakeup
Wakeup from USB Suspend mode
25
µs
Note
1. Usage above the absolute maximum conditions may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of
time may affect device reliability. When used below Absolute Maximum conditions but above normal operating conditions the device may not operate to specification.
Document Number: 002-31604 Rev. **
Page 11 of 35
CY7C65214D
GPIO
Table 7. GPIO DC Specification
Parameter
Description
Min
Typ
–
Max
Units
Details/Conditions
[2]
VIH
Input voltage high threshold
Input voltage low threshold
LVTTL input, VDDD< 2.7 V
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD > 2.7 V
LVTTL input, VDDD > 2.7 V
0.7 × VDDD
–
V
V
V
V
V
V
CMOS Input
VIL
VIH
VIL
VIH
VIL
–
–
0.3 × VDDD
CMOS Input
[2]
[2]
0.7 × VDDD
–
–
–
–
–
–
–
2
–
–
0.3 × VDDD
–
–
–
0.8
IOH = 4 mA,
VDDD = 5 V ± 10%
VOH
VOH
VOH
VOL
VOL
VOL
CMOS output voltage high level
CMOS output voltage high level
CMOS output voltage high level
CMOS output voltage low level
CMOS output voltage low level
CMOS output voltage low level
VDDD – 0.4
–
–
–
–
–
–
–
–
V
V
V
V
V
V
IOH = 4 mA,
VDDD = 3.3 V ± 10%
VDDD – 0.6
IOH = 1 mA,
VDDD = 1.8 V ± 5%
VDDD – 0.5
–
IOL = 8 mA,
VDDD = 5 V ± 10%
–
–
–
0.4
0.6
0.6
IOL = 8 mA,
VDDD = 3.3 V ± 10%
IOL = 4 mA,
VDDD = 1.8 V ± 5%
Rpullup
Rpulldown
IIL
Pull-up resistor
3.5
5.6
5.6
–
8.5
8.5
2
kΩ
kΩ
nA
pF
–
Pull-down resistor
3.5
–
Input leakage current (absolute value)
Input capacitance
–
25 °C, VDDD = 3.0 V
CIN
–
25
–
7
–
–
–
Vhysttl
Vhyscmos
Input hysteresis LVTTL; VDDD > 2.7 V
Input hysteresis CMOS
40
–
–
mV
mV
0.05 × VDDD
–
Table 8. GPIO AC Specifications
Parameter Description
TRiseFast1
Min
Typ
Max
Units
Details/Conditions
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
–
12
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TFallFast1
TRiseSlow1
TFallSlow1
2
–
–
–
12
60
60
ns
ns
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
10
10
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TRiseFast2
TFallFast2
TRiseSlow2
TFallSlow2
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
20
2
–
–
–
–
20
100
20
ns
ns
ns
ns
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
20
100
Note
2.
V
must not exceed V
+ 0.2 V.
IH
DDD
Document Number: 002-31604 Rev. **
Page 12 of 35
CY7C65214D
nXRES
Table 9. nXRES DC Specifications
Parameter
VIH
Description
Min
Typ
–
Max
Units
V
Details/Conditions
Input voltage high threshold
Input voltage low threshold
Pull-up resistor
0.7 × VDDD
–
–
–
–
–
–
VIL
–
3.5
–
–
0.3 × VDDD
V
Rpullup
CIN
5.6
5
8.5
–
kΩ
pF
Input capacitance
Vhysxres
Input voltage hysteresis
–
100
–
mV
Table 10. nXRES AC Specifications
Parameter
Description
Reset pulse width
Min
Typ
Max
Units
Details/Conditions
Tresetwidth
1
–
–
µs
–
Document Number: 002-31604 Rev. **
Page 13 of 35
CY7C65214D
SPI Specifications
Figure 2. SPI Master Timing
FSPI
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
TDSI
MISO
(input)
MSB
THMO
LSB
TDMO
MOSI
(output)
MSB
LSB
SPI Master Timing for CPHA = 0 (Refer to Table 11 and Table 12)
FSPI
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
TDSI
MISO
(input)
LSB
THMO
MSB
TDMO
MOSI
(output)
MSB
LSB
SPI Master Timing for CPHA = 1 (Refer to Table 11 and Table 12)
Document Number: 002-31604 Rev. **
Page 14 of 35
CY7C65214D
Figure 3. SPI Slave Timing
SSN
(Input)
FSPI
SCK
(CPOL=0,
Input)
TSSELSCK
SCK
(CPOL=1,
Input)
TDSO
THSO
MISO
(Output)
MSB
MSB
LSB
LSB
TDMI
MOSI
(Input)
SPI Slave Timing for CPHA = 0 (Refer to Table 11 and Table 12)
SSN
(Input)
FSPI
SCK
(CPOL=0,
Input)
TSSELSCK
SCK
(CPOL=1,
Input)
THSO
TDSO
MISO
(Ouput)
LSB
LSB
MSB
MSB
TDMI
MOSI
(Input)
SPI Slave Timing for CPHA = 1 (Refer to Table 11 and Table 12)
Document Number: 002-31604 Rev. **
Page 15 of 35
CY7C65214D
Table 11. SPI AC Specifications
Parameter Description
FSPI
Min
–
Typ
–
Max
3
Units
MHz
bits
Details/Conditions
SPI operating frequency
(Master/Slave)
Single SCB: TX + RX
Dual SCB: TX or RX
WLSPI
SPI word length
4
–
16
–
SPI Master Mode
TDMO
MOSI valid after SClock driving edge
–
–
–
15
–
ns
ns
–
–
MISO valid before SClock capturing
edge
TDSI
20
Previous MOSI data hold time with
respect to capturing edge at slave
THMO
0
–
–
ns
–
SPI Slave Mode
TDMI
MOSI valid before SClock Capturing
edge
40
–
–
ns
–
TDSO
MISO valid after SClock driving edge
Previous MISO data hold time
–
0
–
–
–
104.4
ns
ns
ns
–
–
–
THSO
–
–
TSSELSCK
SSEL valid to first SCK valid edge
100
Flash Memory Specifications
Table 12. Flash Memory Specifications
Parameter
Fend
Description
Flash endurance
Min
Typ
Max
Units
Details/Conditions
100 K
–
–
cycles
–
–
Flash retention.
TA 85 °C, 10 K program/erase
cycles.
Fret
10
–
–
years
Document Number: 002-31604 Rev. **
Page 16 of 35
CY7C65214D
Pin Description
Pin[3]
Type
Power
Name
Description
1
2
VDDD
VDDD Core
GPIO
GPIO_8
GPIO_9
GPIO IN
GPIO Input Pin (see Table 15)
3
GPIO
GPIO OUT GPIO Out Pin (see Table 15)
Digital Ground
4
Power
VSSD
5
SCB/GPIO
SCB/GPIO
SCB/GPIO
SCB/GPIO
GPIO
MISO_1
MOSI_1
SCB1 SPI MISO (Master IN Slave OUT)
SCB1 SPI MOSI (Master Out Slave IN)
SCB1 SPI Slave Select
6
7
SSEL_1
8
SCLK_1
SCB1 SPI Clock
9
TX/RX LED_1
TX/RX LED_0
Suspend
Notification LED for SPI SCB1 Tx/RX
Notification LED for SPI SCB0 Tx/RX
Asserted when the part enters Low Power mode
10
11
GPIO
Output
Wakeup device from suspend mode. Can be configured as active high/low
using configuration utility.
12
13
14
15
16
17
18
Input
GPIO
Wakeup
GPIO_16
GPIO OUT GPIO Out Pin. Refer table 15.
USB Data Signal Plus, integrates termination resistor and a 1.5-k pull-up
resistor
USBIO
USBIO
Power
Power
Reset
USBDP
USBDM
VCCD
USB Data Signal Minus, integrates termination resistor
This pin should be decoupled to ground using a 1-µF capacitor or by
connecting a 1.8-V supply (Internal LDO Output).
VSSD
Digital Ground
Chip Reset active, low. Can be left unconnected or have a pull up resistor
connected when not in use.
nXRES
19
20
21
22
23
24
25
26
27
Power
Power
GPIO
VBUS
VBUS Supply, 3.15 V to 5.25 V
Digital Ground
VSSD (VBUS)
GPIO_17
GPIO_18
VDDD_IO
VSSA
GPIO OUT GPIO Out Pin (see Table 15)
GPIO
GPIO OUT GPIO Out Pin (see Table 15)
Power
Power
GPIO
VDDD for IO pins
Analog Ground
GPIO_0
GPIO_1
GPIO IN
GPIO IN
GPIO Out Pin (see Table 15)
GPIO Out Pin (see Table 15)
Slave Select Enable SCB0 SPI
GPIO
SCB/GPIO
SSEL_0
28
SCB/GPIO
MISO_0
SCB0 SPI MISO
29
30
SCB/GPIO
SCB/GPIO
MOSI_0
SCLK_0
SCB0 SPI MOSI
SCB0 SPI Clock
Signal to external logic to indicate USB Unconfigured state and USB
Suspend
31
Output
GPIO
POWER#
32
GPIO_7
GPIO IN
GPIO Out Pin (see Table 15)
Note
3. Any pin acting as an input pin should not be left unconnected.
Document Number: 002-31604 Rev. **
Page 17 of 35
CY7C65214D
Figure 4. 32-Pin QFN Pinout
VDDD
1
2
3
4
5
6
7
8
VSSA
24
23
22
21
20
19
18
17
GPIO_8
VDDD_IO
GPIO_18
GPIO_17
GPIO_9
VSSD
CY7C65214D-32QFN
Top View
VSSD
VBUS
MISO_1
MOSI_1
nXRES
VSSD
SSEL_1
SCLK_1
Document Number: 002-31604 Rev. **
Page 18 of 35
CY7C65214D
Table 13. Serial Communication Block (SCB0) Configuration
Mode 0[4]
SPI Master
GPIO_8
Mode 1
SPI Slave
GPIO_8
Pin
Serial Port 0
2
SCB0_0
SCB0_1
SCB0_2
SCB0_3
SCB0_4
SCB0_5
SSEL_OUT_0
MISO_IN_0
MOSI_OUT_0
SCLK_OUT_0
GPIO_9
SSEL_IN_0
MISO_OUT_0
MOSI_IN_0
SCLK_IN_0
GPIO_9
27
28
29
30
3
Table 14. Serial Communication Block (SCB1) Configuration
Mode 0[4]
SPI Master
GPIO_8
Mode 1
SPI Slave
GPIO_8
Pin
Serial Port 1
5
6
SCB1_0
SCB1_1
SCB1_2
SCB1_3
SCB1_4
SCB1_5
SSEL_OUT_0
MISO_IN_0
MOSI_OUT_0
SCLK_OUT_0
GPIO_9
SSEL_IN_0
MI-SO_OUT_0
MOSI_IN_0
SCLK_IN_0
GPIO_9
7
8
9
10
Legend:
GPIO
SCB0
SCB1
Note
4. Device configured in Mode 0 as default. Other modes can be configured through Cypress-supplied configuration utility.
Document Number: 002-31604 Rev. **
Page 19 of 35
CY7C65214D
Table 15. GPIO Configuration[5]
GPIO Configuration Option
Description
TRISTATE
DRIVE 1
DRIVE 0
I/O tristated
Output static 1
Output static 0
This output is used to control power to an external logic via switch to cut power off during unconfigured
USB device and USB suspend.
0 - USB device in Configured state
POWER#
1 - USB device in Unconfigured state or during USB suspend mode
TXLED#
Drives LED during USB transmit
RXLED#
Drives LED during USB receive
TX or RX LED#
Drives LED during USB transmit or receive
Configurable battery charger detect pins to indicate type of USB charger (SDP, CDP, or DCP)
Configuration example:
00 - Draw up to 100 mA (Unconfigured state)
01 - SDP (up to 500 mA)
10 - CDP/DCP (up to 1.5 A)
BCD0
BCD1
11 - Suspend (up to 2.5 mA)
This truth table can be configured using the configuration utility
VBUS detection. Connect VBUS to this pin via resistor network for VBUS detection when using BCD
feature (see Figure 9).
BUSDETECT
Note
5. These signal options can be configured on any of the available GPIO pins using Cypress-supplied configuration utility.
Document Number: 002-31604 Rev. **
Page 20 of 35
CY7C65214D
The USB bus-powered system must comply with the following
requirements:
USB Power Configurations
The following section describes possible USB power configura-
tions for the CY7C65214D. Refer to the Pin Description on page
17 for signal details.
1. The system should not draw more than 100 mA prior to USB
enumeration (Unconfigured state).
2. The system should not draw more than 2.5 mA during USB
Suspend mode.
USB Bus-Powered Configuration
3. A high-power bus-powered system (can draw more than
100 mA when operational) must use POWER# (configured
over GPIO) to keep the current consumption below 100 mA
prior to USB enumeration, and 2.5 mA during USB Suspend
state.
Figure 5 shows an example of the CY7C65214D in a
bus-powered design. VBUS is connected directly to the
CY7C65214D because it has an internal regulator.
4. The system should not draw more than 500 mAfrom the USB
host.
The configuration descriptor in the CY7C65214D flash should be
updated to indicate bus power and the maximum current
required by the system using the configuration utility.
Figure 5. Bus-Powered Configuration
CY7C65214D
25 GPIO_0
26 GPIO_1
27 SSEL_0
28 MISO_0
29 MOSI_0
30 SCLK_0
31 POWER#
32 GPIO_7
2
3
GPIO_8
GPIO_9
1
USB
VDDD
CONNECTOR
19
14
15
5
6
7
8
9
MISO_1
MOSI_1
SSEL_1
SCLK_1
VBUS
USBDP
USBDM
VBUS
D+
D-
GND
4.7 uF
0.1 uF
TX/RX LED_1
10 TX/RX LED_0
13 GPIO_16
21 GPIO_17
22 GPIO_18
18
nXRES
VCCD
16
11 SUSPEND
12 WAKEUP
1 uF
24 20 17
4
Document Number: 002-31604 Rev. **
Page 21 of 35
CY7C65214D
When VBUS is present, CY7C65214D enables an internal,
1.5-k pull-up resistor on USBDP. When VBUS is absent (USB
host is powered down), CY7C65214D removes the 1.5-k
pull-up resistor on USBDP, and this ensures no current flows
from the USBDP to the USB host via a 1.5-k pull-up resistor, to
comply with USB 2.0 specification.
Self-Powered Configuration
Figure 6 shows an example of CY7C65214D in a self-powered
design.
In this configuration:
■ VBUS is powered from USB VBUS. VBUS pin is also used to
detect USB connection.
When reset is asserted to CY7C65214D, all the I/O pins are
tristated.
■ VDDD is powered from an external power supply.
Using the configuration utility, the configuration descriptor in the
CY7C65214D flash should be updated to indicate that it is
self-powered.
Figure 6. Self-Powered Configuration
CY7C65214D
3.3 V
3.3 V
25 GPIO_0
26 GPIO_1
27 SSEL_0
28 MISO_0
29 MOSI_0
30 SCLK_0
31 POWER#
32 GPIO_7
1
VDDD
VBUS
19
2
3
GPIO_8
GPIO_9
USB
CONNECTOR
5
6
7
8
9
MISO_1
MOSI_1
SSEL_1
SCLK_1
VBUS
D+
D-
14
USBDP
USBDM
15
GND
TX/RX LED_1
4.7 uF
4.7 KΩ
0.1 uF
10 TX/RX LED_0
13 GPIO_16
21 GPIO_17
22 GPIO_18
18
nXRES
VCCD
10 KΩ
16
11 SUSPEND
12 WAKEUP
1 uF
24 20 17
4
Document Number: 002-31604 Rev. **
Page 22 of 35
CY7C65214D
The USB bus-powered system must comply with the following:
USB Bus Powered with Variable I/O Voltage
Figure 7 shows CY7C65214D in a bus-powered system with
variable I/O voltage. A low dropout (LDO) regulator is used to
supply 1.8 V or 3.3 V (using a jumper switch) the input of which
is 5 V from VBUS. Another jumper switch is used to select 1.8/3.3
V or 5 V from VBUS for the VDDD pin of CY7C65214D. This
allows I/O voltage and supply to external logic to be selected
among 1.8 V, 3.3 V, or 5 V.
■ The system should not draw more than 100 mA prior to USB
enumeration (Unconfigured state).
■ The system should not draw more than 2.5 mA during USB
Suspend mode.
■ A high-power bus-powered system (can draw more than 100
mA when operational) must use POWER# (configured over
GPIO) to keep the current consumption below 100 mA prior to
USB enumeration and 2.5 mA during USB Suspend state.
Figure 7. USB Bus-Powered with 1.8 V, 3.3 V, or 5 V Variable I/O Voltage[6]
CY7C65214D
25 GPIO_0
26 GPIO_1
27 SSEL_0
28 MISO_0
29 MOSI_0
30 SCLK_0
31 POWER#
32 GPIO_7
Power
Switch
1.8v or 3.3v or 5v
Supply to External Logic
1.8/3.3 V
2
3
GPIO_8
GPIO_9
1
2
3
1
Jumper to select
1.8 V/3.3 V or 5 V
VDDD
5
6
7
8
9
MISO_1
MOSI_1
SSEL_1
SCLK_1
19
VBUS
USBDP
USBDM
VBUS
D+
D-
14
15
USB
CONNECTOR
GND
TX/RX LED_1
0.1uF
10 TX/RX LED_0
13 GPIO_16
21 GPIO_17
22 GPIO_18
18
nXRES
VCCD
VBUS
16
11 SUSPEND
12 WAKEUP
TC 1070
Vout Vin
SHDn
Vadj GND
1.8/3.3 V
1 uF
0.1 uF
24 20 17
4
1uF
1M
1 2 3
VBUS
VDDD
3.3 V
562K
1.8 V
2M
4.7 uF
0.1 uF
4.7 uF
0.1 uF
Jumper to select
1.8 V or 3.3 V
Note
6. 1.71 V VDDD 1.89 V - Short VCCD pin with VDDD pin; VDDD > 2 V - connect a 1-µF decoupling capacitor to the VCCD pin.
Document Number: 002-31604 Rev. **
Page 23 of 35
CY7C65214D
Battery-operated bus power systems must comply with the
following conditions:
Application Examples
The following section provides CY7C65214D application
examples.
■ The system can be powered from the battery (if not discharged)
and be operational if VBUS is not connected or powered down.
■ The system should not draw more than 100 mAfrom the VBUS
prior to USB enumeration and USB Suspend mode.
USB-to-Dual SPI Bridge with Battery-Charge
Detection
■ The system should not draw more than 500 mA for SDP and
1.5 A for CDP/DCP
CY7C65214D can connect any embedded system, with a serial
port, to a host PC through USB. CY7C65214D enumerates as a
dual COM port on the host PC.
SUSPEND is connected to the MCU to indicate USB suspend or
USB Unconfigured and the WAKEUP pin is used to wake up
CY7C65214D, which in turn issues a remote wakeup to the USB
host. GPIO1 and GPIO0 are configured as RXLED# and
TXLED# to drive two LEDs indicating data receive and transmit
respectively.
To comply with the first requirement, VBUS from the USB host is
connected to the battery charger as well as CY7C65214D as
shown in Figure 8. When VBUS is connected, CY7C65214D
initiates battery charger detection and indicates the type of USB
charger over BCD0 and BCD1. If the USB charger is SDP or
CDP, CY7C65214D enables a 1.5-K pull-up resistor on the
USBDP for Full-Speed enumeration. When VBUS is
disconnected CY7C65214D indicates absence of the USB
charger over BCD0 and BCD1, and removes the 1.5-K pull-up
resistor on USBDP. Removing this resistor ensures no current
flows from the supply to the USB host through the USBDP, to
comply with the USB 2.0 specification.
CY7C65214D implements the battery charger detection
functionality based on the USB Battery Charging Specification
Rev 1.2.
To comply with the second and third requirements, two signals
(BCD0 and BCD1) are configured over GPIO to communicate
the type of USB host charger and the amount of current it can
draw from the battery charger. The BCD0 and BCD1 signals can
be configured using the configuration utility.
Figure 8. USB to Dual SPI Bridge with Battery Charge Detection[7, 8]
CY7C65214D
VCC
27
SSEL_0
SSEL
MISO
28
29
30
MISO_0
MOSI_0
1
MOSI
SCLK
VDDD
MCU
SCLK_0
EN1
EN2
22
21
BCD0
BCD1
SYS
BAT
GPIO_18
GPIO_17
Battery
Charger
(MAX8856)
12
11
I/O
I/O
WAKEUP
SUSPEND
GND
IN
4.7K
4.7K
2
GPIO_8
VCC
BUSDETECT
VCC
VCC
7
8
6
5
19
SSEL
SSEL_1
VBUS
USBDP
USBDM
OVP
VBUS
D+
D-
GND
1K
1K
14
15
SPI
EEPROM
MISO
MOSI
SCLK
MISO_1
MOSI_1
SCLK_1
0.1 uF
USB
CONNECTOR
GND
18
nXRES
VCCD
10
9
TX/RX LED_0
TX/RX LED_1
16
1 uF
24 20 17
4
Notes
7. Add a 100-k pull-down resistor on the V
pin for quick discharge.
BUS
8. Refer Figure 9, Figure 10, Figure 11 and the corresponding descriptions for handling VBUS Over Voltage Protection (OVP).
Document Number: 002-31604 Rev. **
Page 24 of 35
CY7C65214D
In a battery charger system.a 9-V spike on the VBUS is possible. The CY7C65214D VBUS pin is intolerant to voltage above 6 V. In
the absence of over-voltage protection (OVP) on the VBUS line, VBUS should be connected to BUSDETECT (GPIO configured) using
the resistive network and the output of battery charger to the VBUS pin of CY7C65214D, as shown in Figure 9.
Figure 9. GPIO VBUS Detect (BUSDETECT)
B
A
Rs
Rs = 10 K
VBUS
VBUS = VDDD
SYS
BAT
Battery Charger
B
CY7C65214D
B
+
-
A
R1
R2
R1 ≥ 10 kΩ
R2/(R1+R2) = VDDD/VBUS
BUSDETECT
A
GPIO
VBUS > VDDD
VBUS
When VBUS and VDDD are at the same voltage potential, VBUS
can be connected to GPIO using a series resistor (Rs). This is
shown in Figure 10. If there is a charger failure and VBUS
becomes 9 V, then the 10-k resistor plays two roles. It reduces
the amount of current flowing into the forward biased diodes in
the GPIO, and it reduces the voltage seen on the pad.
When VBUS > VDDD, a resistor voltage divider is necessary to
reduce the voltage from VBUS down to VDDD for the GPIO
sensing the VBUS voltage (see Figure 11). The resistors should
be sized as follows:
R1 > 10 K
R2 / (R1 + R2) = VDDD / VBUS
The first condition limits the voltage and current for the charger
failure situation, as described in the previous paragraph, while
the second condition allows for normal-operation VBUS
detection.
Figure 10. GPIO VBUS Detection, VBUS = VDDD
VDDD
BUSDETECT
CY7C65214D
VBUS
Rs
Figure 11. GPIO VBUS Detection, VBUS > VDDD
VDDD
BUSDETECT
CY7C65214D
VBUS
R1
R2
Document Number: 002-31604 Rev. **
Page 25 of 35
CY7C65214D
USB to Dual Channel (SPI) Bridge
In Figure 12, CY7C65214D is a USB-to-Dual Channel SPI Bridge. GPIO1 and GPIO0 are configured as RXLED# and TXLED# to
drive two LEDs indicating data USB receive and transmit respectively.
Figure 12. USB-to-SPI Bridge
CY7C65214D
VCC
27
28
29
30
SSEL_0
SSEL
MISO
MISO_0
MOSI_0
SCLK_0
1.8/3.3 V
Jumper to select
1.8 V/3.3 V or 5 V
MOSI
SCLK
MCU
1
2
3
VDDD
12
11
I/O
I/O
5 V
WAKEUP
SUSPEND
GND
VCC
VCC
VCC
19
14
VBUS
VBUS
D+
7
8
SSEL
SSEL_1
MISO_1
1K
1K
USBDP
SPI
EEPROM
MISO
MOSI
SCLK
15
6
5
USBDM
D-
MOSI_1
SCLK_1
GND
0.1 uF
USB
CONNECTOR
GND
18
nXRES
10
9
TX/RX LED_0
TX/RX LED_1
16
VCCD
4
1 uF
24 20 17
Document Number: 002-31604 Rev. **
Page 26 of 35
CY7C65214D
SPI
Motorola
The CY7C65214D SPI can be configured as a Master or Slave
using the configuration utility. CY7C65214D supports SPI master
frequency up to 3 MHz and SPI slave frequency up to 1 MHz. It
can support transaction sizes ranging from 4 bits to 16 bits,
which can be configured using the configuration utility.
In the master mode, SCLK, MOSI and SSEL lines act as output
and MISO acts as an input. In the slave mode, SCLSCLK, MOSI,
and SSEL lines act as input and MISO acts as an output.
The original SPI protocol is defined by Motorola. It is a full-duplex
protocol: transmission and reception occur at the same time.
A single (full-duplex) data transfer follows these steps: The
master selects a slave by driving its SSEL line to ‘0’. Next, it
drives data on its MOSI line and it drives a clock on its SCLK line.
The slave uses the edges of the transmitted clock to capture the
data on the MOSI line. The slave drives data on its MISO line.
The master captures the data on the MISO line. The process is
repeated for all the bits in the data transfer.
CY7C65214D supports three versions of the SPI protocol:
Multiple data transfers may happen without the SSEL line
changing from ‘0’ to ‘1’ and back from ‘1’ to ‘0’ in between the
individual transfers. As a result, slaves must keep track of the
progress of data transfers to separate individual transfers.
When not transmitting data, the SSEL line is ‘1’ and SCLK is
typically off.
■ Motorola - This is the original SPI protocol.
■ Texas Instruments - A variation of the original SPI protocol in
which data frames are identified by a pulse on the SSEL line.
■ National Semiconductors - A half-duplex variation of the
original SPI protocol.
The Motorola SPI protocol has four different modes that
determine how data is driven and captured on the MOSI and
MISO lines. These modes are determined by clock polarity
(CPOL) and clock phase (CPHA). Clock polarity determines the
value of the SCLK line when not transmitting data:
■ CPOL is ‘0’: SCLK is ‘0’ when not transmitting data.
■ CPOL is ‘1’: SCLK is ‘1’ when not transmitting data.
Clock phase determines when data is driven and captured. It is
dependent on the value of CPOL.
Table 16. SPI Protocol Modes
Mode
CPOL
CPHA
Description
0
1
2
3
0
0
1
1
0
1
0
1
Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK.
Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK.
Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK.
Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK.
Document Number: 002-31604 Rev. **
Page 27 of 35
CY7C65214D
Figure 13. Driving and Capturing of MOSI/MISO Data as a Function of CPOL and CPHA
CPOL: ‘0’, CPHA: ‘0’
SCLK
MOSI/MISO
MSB
LSB
CPOL: ‘0’, CPHA: ‘1’
CPOL: ‘1’, CPHA: ‘0’
SCLK
MOSI/MISO
MSB
LSB
SCLK
MOSI/MISO
MSB
LSB
CPOL: ‘1’, CPHA: ‘0’
SCLK
MOSI/MISO
MSB
LSB
LEGEND:
CPOL:
CPHA:
SCLK:
MOSI:
MISO:
Clock Polarity
Clock Phase
SPI interface clock
SPI Master Out / Slave In
SPI Master In / Slave Out
Figure 14. Single 8-bit Data Transfer and Two Successive 8-bit Data Transfers in Mode 0 (CPOL is ‘0’, CPHA is ‘0’)
CPOL: ‘0’, CPHA: ‘0’, single data transfer
SCLK
SSEL
MOSI
MISO
MSB
MSB
LSB
LSB
CPOL: ‘0’, CPHA: ‘0’, two successive data transfers
SCLK
SSEL
MOSI
MISO
MSB
MSB
LSB
LSB
MSB
MSB
LSB
LSB
LEGEND:
CPOL:
CPHA:
SCLK:
SSEL:
Clock Polarity
Clock Phase
SPI interface clock
SPI slave select
MOSI:
MISO:
SPI Master Out / Slave In
SPI Master In / Slave Out
Document Number: 002-31604 Rev. **
Page 28 of 35
CY7C65214D
Texas Instruments
The Texas Instruments' SPI protocol redefines the use of the SSEL signal. It uses the signal to indicate the start of a data transfer,
rather than a low, active slave-select signal. The start of a transfer is indicated by a high, active pulse of a single-bit transfer period.
This pulse may occur one cycle before the transmission of the first data bit, or may coincide with the transmission of the first data bit.
The transmitted clock SCLK is a free-running clock.
The TI SPI protocol only supports mode 1 (CPOL is '0' and CPHA is '1'): data is driven on a rising edge of SCLK and data is captured
on a falling edge of SCLK.
The following figure illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SSEL pulse precedes the first
data bit. Note how the SSEL pulse of the second data transfer coincides with the last data bit of the first data transfer.
Single data transfer
SCLK
SSEL
MOSI
MISO
MSB
MSB
LSB
LSB
Two successive data transfers
SCLK
SSEL
MOSI
MSB
MSB
LSB
LSB
MSB
MSB
LSB
LSB
MISO
LEGEND:
SCLK:
SSEL:
MOSI:
MISO:
SPI interface clock
SPI slave select pulse
SPI Master Out / Slave In
SPI Master In / Slave Out
The following figure illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SSEL pulse coincides with the
first data bit.
Single data transfer
SCLK
SSEL
MOSI
MISO
MSB
MSB
LSB
LSB
Two successive data transfers
SCLK
SSEL
MOSI
MISO
MSB
MSB
LSB
LSB
MSB
MSB
LSB
LSB
LEGEND:
SCLK:
SPI interface clock
SSEL:
SPI slave select pulse
MOSI:
MISO:
SPI Master Out / Slave In
SPI Master In / Slave Out
Document Number: 002-31604 Rev. **
Page 29 of 35
CY7C65214D
National Semiconductors
The National Semiconductors' SPI protocol is a half-duplex protocol. Rather than transmission and reception occurring at the same
time, transmission and reception take turns (transmission happens before reception). A single “idle” bit transfer period separates
transmission from reception.
Note Successive data transfers are NOT separated by an “idle” bit transfer period.
The transmission data transfer size and reception data transfer size may differ. The National Semiconductors' SPI protocol only
supports mode 0: data is driven on a falling edge of SCLK and data is captured on a rising edge of SCLK.
The following figure illustrates a single data transfer and two successive data transfers. In both cases, the transmission data transfer
size is 8 bits and the reception transfer size is 4 bits.
Single data transfer
SCLK
SSEL
MOSI
MISO
MSB
LSB
MSB
LSB
“idle” ‘0’ cycle
Two successive data transfers
SCLK
SSEL
MOSI
MISO
MSB
LSB
MSB
MSB
“idle” ‘0’ cycle
LSB
no “idle” cycle
LEGEND:
SCLK:
SSEL:
MOSI:
MISO:
SPI interface clock
SPI slave select
SPI Master Out / Slave In
SPI Master In / Slave Out
The above figure defines MISO and MOSI as undefined when the lines are considered idle (not carrying valid information). It will drive
the outgoing line values to '0' during idle time (to satisfy the requirements of specific master devices (NXP LPC17xx) and specific
slave devices (MicroChip EEPROM)).
Document Number: 002-31604 Rev. **
Page 30 of 35
CY7C65214D
Ordering Information
Table 17 lists the CY7C65214D key package features and ordering codes. For more information, contact your local sales
representative.
Table 17. Key Features and Ordering Information
Package
Ordering Code
Operating Range
Industrial
32-pin QFN (5 × 5 × 1 mm, 0.5 mm pitch) (Pb-free)
32-pin QFN (5 × 5 × 1 mm, 0.5 mm pitch) (Pb-free) – Tape and Reel
CY7C65214D-32LTXI
CY7C65214D-32LTXIT
Industrial
Ordering Code Definitions
CY 7C65
- 32 LTX
I
X
XXXX
X: Blank or T
Blank = Tray; T= Tape and Reel
Temperature Range: I = Industrial; C = Commercial
Package Type: LT = QFN; X = Pb-free
Number of Pins: 32
Part Number XXXX:
2148 / 214D: Single/Dual Channel USB-SPI Master Bridge Controller
Technology Code: C = CMOS; Family Code: 65 = Full Speed USB-Serial
Company ID: CY = Cypress (An Infineon Technologies Company)
Document Number: 002-31604 Rev. **
Page 31 of 35
CY7C65214D
Package Information
The package currently planned to be supported is the 32-pin QFN.
Figure 15. 32-pin QFN 5 × 5 × 1.0 mm LT32B 3.5 × 3.5 EPAD (Sawn)
001-30999 *D
Table 18. Package Characteristics
Parameter Description
Min
–40
–
Typ
25
Max
85
–
Units
°C
T
Operating ambient temperature
A
THJ
Package
19
°C/W
JA
Table 19. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
32-pin QFN
260 °C
30 seconds
Table 20. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
32-pin QFN
MSL 3
Document Number: 002-31604 Rev. **
Page 32 of 35
CY7C65214D
Acronyms
Document Conventions
Table 21. Acronyms Used in this Document
Units of Measure
Acronym
BCD
CDC
CDP
DCP
DLL
Description
battery charger detection
Table 22. Units of Measure
Symbol
Unit of Measure
communication driver class
charging downstream port
dedicated charging port
dynamic link library
C
degree Celsius
DMIPS
dhrystone million instructions per second
k
kilo-ohm
KB
kilobyte
ESD
GPIO
HBM
MCU
OSC
PHDC
PID
electrostatic discharge
general purpose input/output
human-body model
kHz
kV
kilohertz
kilovolt
Mbps
MHz
mm
V
megabits per second
megahertz
millimeter
volt
Microcontroller Unit
oscillator
personal health care device class
Product Identification
SCB
SDP
SIE
serial communication block
Standard Downstream Port
serial interface engine
serial peripheral interface
virtual communication port
Universal Serial Bus
SPI
VCOM
USB
VID
Vendor Identification
Document Number: 002-31604 Rev. **
Page 33 of 35
CY7C65214D
Document History Page
Document Title: CY7C65214D, USB-Serial Dual Channel SPI Bridge
Document Number: 002-31604
Submission
Revision
ECN
Description of Change
Date
**
6993251
12/01/2020 Final datasheet to NSO.
Document Number: 002-31604 Rev. **
Page 34 of 35
CY7C65214D
Sales, Solutions, and Legal Information
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a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
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use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-31604 Rev. **
Revised December 1, 2020
Page 35 of 35
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