CY7C65216-24LTXIT [INFINEON]
USB single I2C bridge controller with 12 GPIOs, 32-pin QFN;
| 型号： | CY7C65216-24LTXIT |
| 厂家： | 
Infineon |
| 描述： | USB single I2C bridge controller with 12 GPIOs, 32-pin QFN |
| 文件： | 总28页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY7C65216
USB-I2C Single Channel Bridge Controller
CY7C65216, USB-I2
C Single Channel Bridge Controller
■ RoHS-compliant package
❐ 24-pin QFN (4.0 mm 4.0 mm, 0.55 mm, 0.5 mm pitch)
Features
■ USB 2.0-compliant, Full-Speed (12 Mbps)
❐ Supportscommunicationdriverclass(CDC), personalhealth
care device class (PHDC), and vendor-device class
❐ Battery charger detection (BCD) compliant with USB Battery
Charging Specification, Rev. 1.2 (Peripheral Detect only)
❐ Integrated USB termination resistors
■ Single-channel configurable I2C interface
■ Ordering part number
❐ CY7C65216-24LTXI
❐ CY7C65216-24LTXIT
Applications
■ Medical/healthcare devices
■ Point-of-Sale (POS) terminals
■ Test and measurement system
■ Gaming systems
❐ Master/Slave up to 400 kHz and by default the part is
configured as I2C Slave
❐ 256 bytes each transmit and receive buffer
❐ Supports multi-master I2C
■ General-purpose input/output (GPIO) pins: 8
■ Set-top box PC-USB interface
■ Industrial
■ 512-byte flash for storing configuration parameters
■ Configuration utility (Windows) to configure the following:
■ Networking
❐ Vendor ID (VID), Product ID (PID), and Product and
■ Enabling USB connectivity in legacy peripherals
Functional Description
Manufacturer descriptors
❐ I2C
❐ Charger detection
❐ GPIO
For a complete list of related resources, click here.
■ Driver support for VCOM and DLL
❐ Windows 10: 32- and 64-bit versions
❐ Windows 8.1: 32- and 64-bit versions
❐ Windows 8: 32- and 64-bit versions
❐ Windows 7: 32- and 64-bit versions
❐ Windows Vista: 32- and 64-bit versions
❐ Windows XP: 32- and 64-bit versions
❐ Mac OS-X: 10.6, 10.7
❐ Linux: Kernel version 2.6.35 onwards.
■ Clocking: Integrated 48-MHz clock oscillator
■ Supports bus-/self-powered configurations
■ USB Suspend mode for low power
■ Operating voltage: 1.71 to 5.5 V
■ Operating temperature
❐ Commercial: 0 °C to 70 °C
❐ Industrial: -40 °C to 85 °C
■ ESD protection: 2.2-kV HBM
USB-Compliant
USB-I2C Single Channel Bridge Controller is fully compliant with the USB 2.0 Specification and Battery Charger
Specification v1.2.
Errata: For information on silicon errata, see “Errata” on page 25. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 002-31602 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 26, 2020
CY7C65216
USB Serial Bridge Controller Family
USB Serial bridge Controllers are a family of configurable products for most common applications requiring no firmware changes.
Configuration utility is provided to Configure USB-VID, USB-PID, USB Product and Manufacturer Descriptors. The same configuration
utility can be used to configure UART, I2C, SPI, Battery Charger Detection, GPIOs, Power mode, and so on.
Figure 1. USB Serial Bridge Controller Family
CY7C65211
24-QFN 10 GPIO
Configurable as:
USB-SPI
CY7C65223
24-QFN 4 GPIO
RS485 Support
S/W and H/W Flow
Control
USB-I2C
USB-UART
H/W Flow Control
CY7C65213A
32-QFN 8 GPIO
RS485 Support
S/W and H/W Flow
Control
CY7C652148
24-QFN
6 GPIO
CY7C65216
24-QFN
8 GPIO
Single Channel
CY7C65211A
24-QFN 10 GPIO
Configurable as:
USB-SPI
CY7C65213
32-QFN 8 GPIO
RS485 Support
H/W Flow Control
USB-I2C
USB-UART
H/W Flow Control
CY7C65215
32-QFN 17 GPIO*
Configurable as:
USB-SPI
USB-I2C
USB-UART
H/W Flow Control
CY7C65223D
32-QFN 4 GPIOs
RS485 Support
S/W and H/W Flow
Control
CY7C65214D
32-QFN
8 GPIO
CY7C65216D
32-QFN
12 GPIO
Dual Channel
CY7C65215A
32-QFN 17 GPIO*
Configurable as:
USB-SPI
USB-I2C
USB-UART
RS485 Support
H/W Flow Control
USB-I2C
Bridge Controller
USB-Serial Configurable
Bridge Controller
USB-UART
Bridge Controller
USB-SPI
Bridge Controller
Errata: For information on silicon errata, see “Errata” on page 25. Details include trigger conditions, devices affected, and proposed workaround.
Document Number: 002-31602 Rev. **
Page 2 of 27
CY7C65216
Table 1. USB Serial Family Feature Comparison
# of
USB-UART
USB-SPI
USB-I2C
Software Hardware
SPI Serial
Data
MPN
GPIO
RS485
UART
Pins**
SPI Master/ I2C Master/
Channels
Flow
Control
Flow
Control
Support
Slave
Slave
Width (bit)
CY7C65213
CY7C65213A
CY7C65223
CY7C65223D
CY7C652148
CY7C65214D
CY7C65216
CY7C65216D
CY7C65211
CY7C65211A
CY7C65215
1
1
1
2
1
2
1
2
1
1
2
2
8
8
N
Y
Y
Y
–
N
N
Y
Y
–
Y
Y
Y
Y
–
8
–
–
–
–
–
–
–
–
–
8
–
4
2 / 4 / 6
–
4
2 / 4 / 6 / 8
–
6
–
4-16 bits Master/Slave
4-16 bits Master/Slave
–
8
–
–
–
–
–
8
–
–
–
–
–
–
Master/Slave
Master/Slave
12
10*
10*
17*
17*
–
–
–
–
–
–
N
Y
N
Y
N
N
N
N
Y
Y
Y
Y
2 / 4 / 6
2 / 4 / 6
2 / 4 / 6
4-16 bits Master/Slave Master/Slave
4-16 bits Master/Slave Master/Slave
4-16 bits Master/Slave Master/Slave
CY7C65215A
2 / 4 / 6 / 8 4-16 bits Master/Slave Master/Slave
Legend
2
* Represents the total GPIO count offered by the part. This count can dynamically change based on UART / SPI / I C pin configuration.
** UART Pins
**UART Pins
UART Signal
2
4
6
8
RxD and TxD
RxD, TxD, RTS#, CTS#
RxD, TxD, RTS#, CTS#, DTR#, DSR#
RxD, TxD, RTS#, CTS#, DTR#, DSR#, DCD#, RI#
Document Number: 002-31602 Rev. **
Page 3 of 27
CY7C65216
Table 2. Default Serial Channel Configuration
# of
USB- UART
USB-SPI
USB-I2C
USB
Protocol
SPI Master/ I2C Master/
MPN
GPIO
Is RS485
Channels
UART Pins
Enabled
Slave
Slave
CY7C65213
CY7C65213A
CY7C65223
CY7C65223D
CY7C652148
CY7C65214D
CY7C65216
CY7C65216D
CY7C65211
CY7C65211A
CY7C65215
CY7C65215A
1
1
1
2
1
2
1
2
1
1
2
2
4
4
CDC**
CDC**
N
N
Y
Y
8
8
4
4
–
–
–
–
6
6
6
6
–
–
–
–
–
–
–
–
4
CDC**
4
CDC**
6
Vendor***
Vendor***
Vendor***
Vendor***
CDC**
–
–
Master
–
8
Master
–
8
–
–
–
–
–
–
–
Slave
12
3
–
Master
N
N
N
N
–
–
–
–
3
CDC**
4
CDC**
4
CDC**
** USB CDC Protocol allows the USB host Operating System to detect the device as Virtual COM Port Device.
*** USB Vendor Protocol allows the USB host operating system to detect the device as general USB device. This device is accessible using Cypress Application Library.
Document Number: 002-31602 Rev. **
Page 4 of 27
CY7C65216
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly
and effectively integrate the device into your design. For a comprehensive list of resources, see the document USB-Serial Bridge
Controller Product Overview.
■ Overview: USB Portfolio, USB Roadmap
For complete list of knowledge base articles, click here.
■ USB 2.0 Product Selectors: USB-Serial Bridge Controller, USB
■ Code Examples: USB Full-Speed
to UART Controller (Gen I)
■ Development Kits:
■ Knowledge Base Articles: Cypress offers a large number of
USB knowledge base articles covering a broad range of topics,
from basic to advanced level. Recommended knowledge base
articles for getting started with USB-Serial Bridge Controller
are:
❐ CYUSBS232, Cypress USB-UART LP Reference Design Kit
❐ CYUSBS234, Cypress USB-Serial (Single Channel) Devel-
opment Kit
❐ CYUSBS236, Cypress USB-Serial (Dual Channel) Develop-
ment Kit
❐ KBA85909 – Key Features of the Cypress® USB-Serial
■ Models: IBIS
Bridge Controller
❐ KBA85920 – USB-UART and USB-Serial
❐ KBA85921
–
Replacing FT232R with CY7C65213
USB-UART LP Bridge Controller
❐ KBA85913 – Voltage supply range for USB-Serial
❐ KBA89355 – USB Serial Cypress Default VID and PID
❐ KBA92641 – USB-Serial Bridge Controller Managing I/Os
using API
❐ KBA92442– Non-Standard Baud Rates inUSB-Serial Bridge
Controllers
❐ KBA91366
–
Binding
a
USB-Serial Device to
a
Microsoft® CDC Driver
❐ KBA92551 – Testing a USB-Serial Bridge Controller
Configured as USB-UART with Linux®
❐ KBA91299 – Interfacing an External I2C Device with the
CYUSBS234/236 DVK
Document Number: 002-31602 Rev. **
Page 5 of 27
CY7C65216
Block Diagram
nXRES
Reset
Internal
48 MHz OSC
VDDD
VCCD
Voltage
Regulator
Serial Communication Block
Internal
32 KHz OSC
USB
256 Bytes TX
FIFO
VBUS
BCD
I2C
I2C
VBUS Regulator
256 Bytes RX
FIFO
Battery Charger
Detection
512 Bytes
Flash
Memory
SIE
USB
Transceiver with
Integrated
USBDP
USBDM
GPIO
GPIO
Resistor
Document Number: 002-31602 Rev. **
Page 6 of 27
CY7C65216
Contents
Functional Overview ........................................................8
USB and Charger Detect .............................................8
Serial Communication .................................................8
Default Configuration ...................................................8
Memory .......................................................................8
System Resources ......................................................8
Suspend and Resume .................................................8
WAKEUP .....................................................................8
Software ......................................................................8
Internal Flash Configuration ........................................9
Electrical Specifications ................................................10
Absolute Maximum Ratings .......................................10
Operating Conditions .................................................10
Device-Level Specifications ......................................10
GPIO .........................................................................11
nXRES .......................................................................12
I2C Specifications ......................................................12
Flash Memory Specifications ....................................12
Pin Description ...............................................................13
USB Power Configurations ............................................16
USB Bus-Powered Configuration ..............................16
Self-Powered Configuration ......................................17
USB Bus-Powered with Variable I/O Voltage ............18
Application Examples ....................................................19
USB to I2C Bridge .....................................................19
Battery-Operated, Bus-Powered USB to MCU
with Battery Charge Detection ..................................20
Ordering Information ......................................................22
Ordering Code Definitions .........................................22
Package Information ......................................................23
Acronyms ........................................................................24
Document Conventions .................................................24
Units of Measure .......................................................24
Errata ...............................................................................25
Document History Page .................................................26
Sales, Solutions, and Legal Information ......................27
Worldwide Sales and Design Support .......................27
Products ....................................................................27
PSoC® Solutions .......................................................27
Cypress Developer Community .................................27
Technical Support .....................................................27
Document Number: 002-31602 Rev. **
Page 7 of 27
CY7C65216
System Resources
Functional Overview
The CY7C65216 is a Full-Speed USB controller that enables
seamless PC connectivity for peripherals with I2C interface.
CY7C65216 is complaint to BCD specification rev 1.2. It
integrates a voltage regulator, an oscillator, and flash memory
for storing configuration parameters, offering a cost-effective
solution. CY7C65216 supports bus-powered and self-powered
modes and enables efficient system power management with
suspend and remote wake-up signals. It is available in a 24-pin
QFN package.
Power System
CY7C65216 supports the USB Suspend mode to control power
usage. CY7C65216 operates in bus-powered or self-powered
modes over a range of 3.15 to 5.5 V.
Clock System
CY7C65216 has a fully integrated clock with no external
components required. The clock system is responsible for
providing clocks to all subsystems.
USB and Charger Detect
Internal 48-MHz Oscillator
USB
The internal 48-MHz oscillator is the primary source of internal
clocking in CY7C65216.
CY7C65216 has a built-in USB 2.0 Full-Speed transceiver. The
transceiver incorporates the internal USB series termination
resistors on the USB data lines and a 1.5-k pull-up resistor on
USBDP.
Internal 32-kHz Oscillator
The internal 32-kHz oscillator is primarily used to generate
clocks for peripheral operation in the USB Suspend mode.
Charger Detection
CY7C65216 supports BCD for Peripheral Detect only and
complies with the USB Battery Charging Specification, Rev. 1.2.
It supports the following charging ports:
■ Standard Downstream Port (SDP): Allows the system to draw
up to 500 mA current from the host
Reset
The reset block ensures reliable power-on reset and brings the
device back to the default known state. The nXRES (active low)
pin can be used by the external devices to reset the CY7C65216.
Suspend and Resume
■ Charging Downstream Port (CDP): Allows the system to draw
up to 1.5 A current from the host
The CY7C65216 device asserts the SUSPEND pin when the
USB bus enters the suspend state. This helps in meeting the
stringent suspend current requirement of the USB 2.0
specification, while using the device in bus-powered mode. The
device resumes from the suspend state under either of the two
following conditions:
■ Dedicated Charging Port (DCP): Allows the system to draw up
to 1.5 A of current from the wall charger
Serial Communication
CY7C65216 has a serial communication block (SCB). Each SCB
can implement I2C interface. A 256-byte buffer is available in
both the TX and RX lines.
I2C Interface
1. Any activity is detected on the USB bus
2. The WAKEUP pin is asserted to generate remote wakeup to
the host
The I2C interface implements full multi-master/slave modes and
supports up to 400 kHz. The configuration utility tool is used to
set the I2C address in the slave mode. The tool enables only
even slave addresses. For further details on the protocol, refer
to the NXP I2C specification, Rev. 5.
WAKEUP
The WAKEUP pin is used to generate the remote wakeup signal
on the USB bus. The remote wakeup signal is sent only if the
host enables this feature through the SET_FEATURE request.
The device communicates support for the remote wakeup to the
host through the configuration descriptor during the USB
enumeration process. The CY7C65216 device allows
enabling/disabling and polarity of the remote wakeup feature
through the configuration utility.
Notes
■ I2C ports are not tolerant of higher voltages. Therefore, they
cannot be hot-swapped or powered up independently when
chip is not powered.
■ The minimum fall time of the SCL is met (as per NXP I2C
specification Rev. 5) when VDDD is between 1.71 V and 3.0 V.
When VDDD is within the range of 3.0 V to 3.6 V, it is
Software
Cypress delivers a complete set of software drivers and a
configuration utility to enable configuration of the product during
system development.
recommended to add a 50 pF capacitor on the SCL signal.
Default Configuration
CY7C65216 is configured as I2C slave device with default I2C
slave 7-bit address as 0x30.
Drivers for Linux Operating Systems
Cypress provides
a
User Mode USB driver library
(libcyusbserial.so) that abstracts vendor commands for the I2C
interface and provides a simplified API interface for user
applications. This library uses the standard open-source libUSB
library to enable USB communication. The Cypress serial library
supports the USB plug-and-play feature using the Linux 'udev'
mechanism.
Memory
CY7C65216 has a 512-byte flash. Flash is used to store USB
parameters, such as VID/PID, serial number, product and
manufacturer descriptors, which can be programmed by the
configuration utility.
Document Number: 002-31602 Rev. **
Page 8 of 27
CY7C65216
CY7C65216 binds to Linux USB Inbox driver, which is part of
Linux Kernel distribution.
Device Configuration Utility (Windows only)
A Windows-based configuration utility is available to configure
device initialization parameters. This graphical user application
provides an interactive interface to define the boot parameters
stored in the device flash.
Drivers for Mac OSx
Cypress delivers a dynamically linked shared library (CyUSB-
Serial.dylib) based on libUSB, which enables communication to
the CY7C65216 device.
This utility allows the user to save a user-selected configuration
to text or xml formats. It also allows users to load a selected
configuration from text or xml formats. The configuration utility
allows the following operations:
In addition, CY7C65216 binds to Mac OSx native driver.
Drivers for Windows Operating Systems
■ View current device configuration
For Windows operating systems (XP, Vista, Win7, Win 8, Win
8.1, and Windows 10), Cypress delivers a user-mode dynami-
■ Select and configure I2C, battery charging, and GPIOs
■ Configure USB VID, PID, and string descriptors
■ Save or Load configuration
cally linked library-CyUSBSerial DLL-that abstracts
a
vendor-specific interface of the CY7C65216 devices and
provides convenient APIs to the user. It provides interface APIs
for vendor-specific I2C and class-specific APIs for PHDC.
USB-I2C Bridge Controller works with Cypress provided USB
vendor class driver. The Cypress Windows drivers are MS logo
certified drivers.
You can download the free configuration utility and drivers at
www.cypress.com.
Internal Flash Configuration
These drivers are bound to device through WU (Windows
Update) services.
The internal flash memory can be used to store the configuration
parameters shown in the following table. A free configuration
utility is provided to configure the parameters listed in the table
to meet application-specific requirements over the USB
interface. The configuration utility can be downloaded at
www.cypress.com/usbserial.
Cypress drivers also support Windows plug-and-play and power
management and USB Remote Wake-up.
Table 3. Internal Flash Configuration for CY7C65216
Parameter
USB Configuration
USB Vendor ID (VID)
USB Product ID (PID)
Manufacturer string
Product string
Default Value
Description
0x04B4
0x0004
Cypress
Default Cypress VID. Can be configured to customer VID.
Default Cypress PID. Can be configured to customer PID.
Can be configured with any string up-to 64 characters
USB-Serial (Single Channel) Can be configured with any string up-to 64 characters
Serial string
–
Can be configured with any string up-to 64 characters
Can be configured to bus-powered or self-powered mode
Power mode
Bus powered
Can be configured to any value from 0 to 500 mA. The configuration
descriptor will be updated based on this.
Max current draw
100 mA
Remote wakeup
Enabled
Vendor
Can be disabled. Remote wakeup is initiated by asserting the WAKEUP pin.
Can be configured to function in CDC, PHDC, or Cypress vendor class
USB interface protocol
Charger detect is disabled by default. When BCD is enabled, three of the
GPIOs must be configured for BCD.
BCD
Disabled
Document Number: 002-31602 Rev. **
Page 9 of 27
CY7C65216
Electrical Specifications
Latch-up current ....................................................................
140 mA
Absolute Maximum Ratings
Exceeding maximum ratings[1] may shorten the useful life of the
device.
Current per GPIO ..................................................................
25 mA
Storage temperature ............................... –55 °C to +100 °C
Operating Conditions
Ambient temperature with
power supplied (Industrial) ....................... –40 °C to +85 °C
TA (ambient temperature under bias)
Supply voltage to ground potential
Industrial .......................................................... –40 °C to +85 °C
VDDD ............................................................................ 6.0 V
VBUS supply voltage .... .......................................... 3.15 V to
5.25 V
VBUS ............................................................................ 6.0 V
VCCD .......................................................................... 1.95 V
VGPIO .............................................................. VDDD + 0.5 V
Static discharge voltage ESD protection levels:
VDDD supply voltage .... .......................................... 1.71 V to
5.50 V
VCCD supply voltage .... .......................................... 1.71 V to
1.89 V
■ 2.2-KV HBM per JESD22-A114
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C, TJ 100 °C, and 1.71 V to 5.50 V, except where noted.
Table 4. DC Specifications
Parameter
VBUS
Description
Min
Typ
Max
Units
Details/Conditions
3.15
3.30
3.45
V
Set and configure the correct voltage
range using a configuration utility for
BUS. Default 5 V.
VBUS supply voltage
4.35
1.71
5.00
1.80
5.25
1.89
V
V
V
Used to set I/O and core voltage. Set
and configure the correct voltage
range using a configuration utility for
VDDD
VDDD supply voltage
2.0
3.3
5.5
V
V
DDD. Default 3.3 V.
Do not use this supply to drive the
external device.
•
1.71 V VDDD 1.89 V: Short
the VCCD pin with the VDDD pin
VCCD
Output voltage (for core logic)
–
1.80
–
V
•
V
DDD > 2 V – connect a 1-µF
capacitor (Cefc) between the
VCCD pin and ground
Cefc
IDD1
External regulator voltage bypass
Operating supply current
1.00
–
1.30
20
1.60
–
µF
X5R ceramic or better
mA
USB 2.0 FS, no GPIO switching
Does not include current through a
pull-up resistor on USBDP.
In USB suspend mode, the D+
voltage can go up to a maximum of
3.8 V.
IDD2
USB Suspend supply current
–
5
–
µA
Table 5. AC Specifications
Parameter
Description
Min
28
–
Typ
–
Max
Units
Details/Conditions
Zout
USB driver output impedance
44
–
–
–
Twakeup
Wakeup from USB Suspend mode
25
µs
Note
1. Usage above the Absolute Maximum conditions may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of
time may affect device reliability. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-31602 Rev. **
Page 10 of 27
CY7C65216
GPIO
Table 6. GPIO DC Specifications
Parameter
Description
Min
Typ
–
Max
Units
Details/Conditions
[2]
VIH
Input voltage high threshold
Input voltage low threshold
LVTTL input, VDDD< 2.7 V
LVTTL input, VDDD < 2.7V
LVTTL input, VDDD > 2.7V
LVTTL input, VDDD > 2.7V
0.7 × VDDD
–
V
V
V
V
V
V
CMOS Input
VIL
VIH
VIL
VIH
VIL
–
–
0.3 × VDDD
CMOS Input
[2]
[2]
0.7 × VDDD
–
–
–
–
–
–
–
2
–
–
0.3 × VDDD
–
–
–
0.8
IOH = 4 mA,
VDDD = 5 V +/- 10%
VOH
VOH
VOH
VOL
VOL
VOL
CMOS output voltage high level
CMOS output voltage high level
CMOS output voltage high level
CMOS output voltage low level
CMOS output voltage low level
CMOS output voltage low level
VDDD – 0.4
–
–
–
–
–
–
–
–
V
V
V
V
V
V
IOH = 4 mA,
VDDD = 3.3 V +/- 10%
VDDD – 0.6
IOH = 1 mA,
VDDD = 1.8 V +/- 5%
VDDD – 0.5
–
IOL = 8 mA,
VDDD = 5 V +/- 10%
–
–
–
0.4
0.6
0.6
IOL = 8 mA,
VDDD = 3.3 V +/- 10%
IOL = 4 mA,
VDDD = 1.8 V +/- 5%
Rpullup
Rpulldown
IIL
Pull-up resistor
3.5
5.6
5.6
–
8.5
8.5
2
kΩ
kΩ
nA
pF
–
Pull-down resistor
3.5
–
Input leakage current (absolute value)
Input capacitance
–
25 °C, VDDD = 3.0 V
CIN
–
25
–
7
–
–
–
Vhysttl
Input hysteresis LVTTL; VDDD > 2.7 V
Input hysteresis CMOS
40
–
C
mV
mV
Vhyscmos
0.05 × VDDD
–
Note
2.
V
must not exceed V
+ 0.2 V.
IH
DDD
Table 7. GPIO AC Specifications
Parameter Description
TRiseFast1
Min
Typ
Max
Units
Details/Conditions
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
–
12
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TFallFast1
TRiseSlow1
TFallSlow1
2
–
–
–
12
60
60
ns
ns
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
10
10
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TRiseFast2
TFallFast2
TRiseSlow2
TFallSlow2
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
20
2
–
–
–
–
20
100
20
ns
ns
ns
ns
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
20
100
Document Number: 002-31602 Rev. **
Page 11 of 27
CY7C65216
nXRES
Table 8. nXRES DC Specifications
Parameter
VIH
Description
Min
Typ
–
Max
Units
V
Details/Conditions
Input voltage high threshold
Input voltage low threshold
Pull-up resistor
0.7 × VDDD
–
–
–
–
–
–
VIL
–
3.5
–
–
0.3 × VDDD
V
Rpullup
CIN
5.6
5
8.5
–
kΩ
pF
Input capacitance
Vhysxres
Input voltage hysteresis
–
100
–
mV
Table 9. nXRES AC Specifications
Parameter
Description
Reset pulse width
Min
Typ
Max
Units
Details/Conditions
Details/Conditions
Details/Conditions
Tresetwidth
1
–
–
µs
–
2
I C Specifications
Table 10. I2C Specifications
Parameter
FI2C
Description
I2C frequency
Min
Typ
Max
Units
1
–
400
kHz
–
Flash Memory Specifications
Table 11. Flash Memory Specifications
Parameter
Fend
Description
Flash endurance
Min
Typ
Max
Units
100K
–
–
cycles
–
Flash retention. TA 85 °C, 10 K
program/erase cycles
Fret
10
–
–
years
–
Document Number: 002-31602 Rev. **
Page 12 of 27
CY7C65216
Pin Description
Pin[3]
Type
GPIO
GPIO
Power
GPIO
GPIO
GPIO
Output
Name
GPIO_6
GPIO_7
Default
Description
1
2
3
4
5
6
7
GPIO IN
GPIO Input Pin (see Table 12 and Table 13)
GPIO OUT GPIO Output Pin (see Table 12 and Table 13)
VSSD
Digital Ground
GPIO_8
GPIO_9
GPIO_10
GPIO OUT GPIO Output Pin (see Table 12 and Table 13)
GPIO OUT GPIO Output Pin (see Table 12 and Table 13)
GPIO OUT GPIO Output Pin (see Table 12 and Table 13)
POWER#
Signal to external logic to indicate USB Unconfigured state and USB Suspend
Indicates device in suspend mode. Can be configured as active low/high using
the configuration utility.
8
9
Output
Input
Suspend
Wakeup
Wakeup device from suspend mode. Can be configured as active low/high using
the configuration utility.
USB Data Signal Plus, integrates termination resistor and a 1.5-kΩ pull-up
resistor
10
11
12
13
14
USBIO
USBIO
Power
Power
Reset
USBDP
USBDM
VCCD
USB Data Signal Minus, integrates termination resistor
This pin should be decoupled to ground using a 1-µF capacitor or by connecting
a 1.8-V supply (Internal LDO Output)
VSSD
Digital Ground
Chip Reset active, low. Can be left unconnected or have a pull up resistor
connected when not in use.
nXRES
15
16
17
Power
Power
Power
VBUS
VSSD
VSSA
VBUS Supply, 3.15 V to 5.25 V
Digital Ground
Analog Ground
Notification LED
I2C Tx/Rx
18
GPIO
Rx/Tx LED
19
20
GPIO
GPIO
GPIO_1
GPIO IN
GPIO IN
GPIO Input Pin (see Table 12 and Table 13)
GPIO Input Pin (see Table 12 and Table 13)
GPIO_2
21
SCB/GPIO
SCL
SDA
I2C Clock
22
23
SCB/GPIO
GPIO
I2C Data
GPIO_5
GPIO IN
GPIO Input Pin (see Table 12 and Table 13)
VDDD Core
24
Power
VDDD
Note
3. Any pin acting as an Input pin should not be left unconnected.
Document Number: 002-31602 Rev. **
Page 13 of 27
CY7C65216
Figure 2. 24-pin QFN Pinout
GPIO_6
GPIO_7
VSSD
1
2
3
4
5
6
18
TX_RX_LED
VSSA
17
16
15
14
13
VSSD
CY7C65216-24QFN
Top View
VBUS
GPIO_8
GPIO_9
GPIO_10
nXRES
VSSD
Table 12. Serial Communication Block Configurations
[4]
Mode 0
Mode 1
Pin
Serial Port
I2C Slave
GPIO_6
GPIO_2
SCL_IN
SDA
I2C Master
GPIO_6
GPIO_2
SCL_OUT
SDA
1
SCB_0
SCB_1
SCB_2
SCB_3
SCB_4
SCB_5
20
21
22
23
2
GPIO_5
GPIO_7
GPIO_5
GPIO_7
Note
4. The device is configured in Mode 0 as the default. Other modes can be configured using the configuration utility provided by Cypress.
Legend
GPIO
SCB
Document Number: 002-31602 Rev. **
Page 14 of 27
CY7C65216
Table 13. GPIO Configurations[5]
GPIO Configuration Option
Description
TRISTATE
DRIVE 1
DRIVE 0
I/O tristated
Output static 1
Output static 0
This output is used to control power to an external logic through a switch to cut power off during an
unconfigured USB device and USB suspend.
0 - USB device in Configured state
POWER#
1 - USB device in Unconfigured state or during USB suspend mode
TXLED#
RXLED#
Drives LED during USB transmit
Drives LED during USB receive
TX or RX LED#
Drives LED during USB transmit or receive
Configurable battery charger detect pins to indicate the type of USB charger (SDP, CDP, or DCP)
Configuration example:
00 - Draw up to 100 mA (unconfigured state)
01 - SDP (up to 500 mA)
10 - CDP/DCP (up to 1.5 A)
BCD0
BCD1
11 - Suspend (up to 2.5 mA)
This truth table can be configured using a configuration utility
VBUS detection. Connect the VBUS to this pin through a resistor network for VBUS detection when
using the BCD feature (refer to Figure 8, Figure 9, and Figure 10).
BUSDETECT
Note
5. These signal options can be configured on any of the available GPIO pins using the configuration utility provided by Cypress.
Document Number: 002-31602 Rev. **
Page 15 of 27
CY7C65216
The USB bus-powered system must comply with the following
requirements:
USB Power Configurations
The following section describes possible USB power
configurations for the CY7C65216. Refer to the Pin Description
on page 13 for signal details.
1. The system should not draw more than 100 mA prior to USB
enumeration (Unconfigured state).
2. The system should not draw more than 2.5 mAduring the USB
Suspend mode.
USB Bus-Powered Configuration
3. A high-power bus-powered system (can draw more than
100 mA when operational) must use POWER# (configured
over GPIO) to keep the current consumption below 100 mA
prior to USB enumeration, and 2.5 mA during USB Suspend
state.
Figure 3 shows an example of the CY7C65216 in a bus-powered
design. The VBUS is connected directly to the CY7C65216
because it has an internal regulator.
4. The system should not draw more than 500 mA from the USB
host.
The configuration descriptor in the CY7C65216 flash should be
updated to indicate bus power and the maximum current
required by the system using the configuration utility.
Figure 3. Bus-Powered Configuration
CY7C65216
18 TX_RX_LED
19 GPIO_1
20 SSEL_OUT
21 SCL
24
15
USB
CONNECTOR
VDDD
22 SDA
VBUS
USBDP
USBDM
VBUS
D+
D-
23 GPIO_5
10
11
1
2
4
5
6
7
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
POWER#
GND
0.1 uF
4.7 uF
14
nXRES
VCCD
8
9
12
SUSPEND
WAKEUP
1 uF
17 16 13
3
Document Number: 002-31602 Rev. **
Page 16 of 27
CY7C65216
When the VBUS is present, CY7C65216 enables an internal,
1.5-k pull-up resistor on USBDP. When the VBUS is absent
(USB host is powered down), CY7C65216 removes the 1.5-k
pull-up resistor on USBDP. This ensures that no current flows
from the USBDP to the USB host through a 1.5-k pull-up
resistor, to comply with the USB 2.0 specification.
Self-Powered Configuration
Figure 4 shows an example of CY7C65216 in a self-powered
design. A self-powered system does not use the VBUS from the
host to power the system, but it has its own power supply. A
self-powered system has no restriction on current consumption
because it does not draw any current from the VBUS.
When reset is asserted to CY7C65216, all the I/O pins are
tristated.
The configuration descriptor in the CY7C65216 flash should be
updated to indicate self-power using the configuration utility.
Figure 4. Self-Powered Configuration
3.3 V
3.3 V
CY7C65216
18 TX_RX_LED
19 GPIO_1
20 GPIO_2
21 SCL
24
15
VDDD
USB
CONNECTOR
22 SDA
VBUS
USBDP
USBDM
VBUS
D+
D-
23 GPIO_5
10
11
1
2
4
5
6
7
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
POWER#
GND
4.7 uF
0.1 uF
4.7 KΩ
10 KΩ
14
nXRES
VCCD
8
9
12
SUSPEND
WAKEUP
1 uF
17 16 13
3
Document Number: 002-31602 Rev. **
Page 17 of 27
CY7C65216
The USB bus-powered system must comply with the following
conditions:
USB Bus-Powered with Variable I/O Voltage
Figure 5 shows CY7C65216 in a bus-powered system with
variable I/O voltage. A low dropout (LDO) regulator is used to
supply 1.8 V or 3.3 V, using a jumper switch the input of which is
5 V from the VBUS. Another jumper switch is used to select
1.8/3.3 V or 5 V from the VBUS for the VDDD pin of CY7C65216.
This allows I/O voltage and supply to external logic to be selected
among 1.8 V, 3.3 V, or 5 V.
■ The system should not draw more than 100 mA prior to USB
enumeration (unconfigured state)
■ The system should not draw more than 2.5 mA during USB
Suspend mode
■ A high-power bus-powered system (can draw more than 100
mA when operational) must use POWER# (configured over
GPIO) to keep the current consumption below 100 mA prior to
USB enumeration and 2.5 mA during the USB Suspend state
Figure 5. USB Bus-Powered with 1.8-V, 3.3-V, or 5-V Variable I/O Voltage[6]
1.8 V or 3.3 V or 5 V
Supply to External Logic
Power
Switch
CY7C65216
18 TX_RX_LED
1.8/3.3 V
19 GPIO_1
20 GPIO_2
21 SCL
1
2
3
24
Jumper to select
1.8 V/3.3 V or 5 V
VDDD
22 SDA
15
10
VBUS
USBDP
USBDM
VBUS
D+
D-
GND
23 GPIO_5
USB
CONNECTOR
1
2
4
5
6
7
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
POWER#
11
0.1uF
4.7 uF
14
nXRES
VCCD
VBUS
12
8
9
SUSPEND
WAKEUP
TC 1070
Vout Vin
1.8/3.3 V
1 uF
17 16 13
3
SHDn
GND
0.1 uF
Vadj
1uF
1M
1 2 3
3.3 V
562K
1.8 V
2M
Jumper to select
1.8 V or 3.3 V
Note
6. 1.71 V VDDD 1.89 V - Short VCCD pin with VDDD pin; VDDD > 2 V - connect a 1-µF decoupling capacitor to the VCCD pin.
Document Number: 002-31602 Rev. **
Page 18 of 27
CY7C65216
In the master mode, SCL is output from CY7C65216. In the slave
mode, SCL is input to CY7C65216. The I2C slave address for
CY7C65216 can be configured using the configuration utility.
The SDA data line is bi-directional in the master/slave modes.
The drive modes of the SCL and SDA port pins are always open
drain.
GPIO8 and GPIO9 are configured as RXLED# and TXLED# to
drive two LEDs to indicate USB receive and transmit.
Refer to the NXP I2C specification for further details on the
protocol.
Application Examples
The following section provides CY7C65216 application
examples.
2
USB to I C Bridge
In Figure 6, CY7C65216 is configured as a USB to I2C Bridge.
The CY7C65216 I2C can be configured as a master or a slave
using the configuration utility. CY7C65216 supports I2C data
rates up to 100 kbps in the standard mode (SM) and 400 kbps in
the fast mode (FM).
Figure 6. USB to I2C Bridge
1.8/3.3 V
VDDD
CY7C65216
1
2
3
2.2K 2.2K
24
Jumper to select
1.8 V/3.3 V or 5 V
VDDD
VCC
21
SCL
I2C
Master
15
22
VBUS
SDA
VBUS
D+
D-
10
11
USB
CONNECTOR
USBDP
GND
USBDM
GND
0.1 uF
14
nXRES
VCCD
12
1 uF
VBUS
17 16 13
3
TC 1070
1.8/3.3 V
Vout
Vin
SHDn
0.1 uF
Vadj GND
1uF
1M
VBUS
0.1 uF
VDDD
1 2 3
3.3 V
562K
1.8 V
2M
4.7 uF
4.7 uF
0.1 uF
Jumper to select
1.8 V or 3.3 V
Document Number: 002-31602 Rev. **
Page 19 of 27
CY7C65216
To comply with the first requirement, the VBUS from the USB
host is connected to the battery charger as well as to
CY7C65216, as shown in Figure 7. When the VBUS is
connected, CY7C65216 initiates battery charger detection and
indicates the type of USB charger over BCD0 and BCD1. If the
USB charger is SDP or CDP, CY7C65216 enables a 1.5-k
pull-up resistor on the USBDP for Full-Speed enumeration.
When the VBUS is disconnected, CY7C65216 indicates an
absence of the USB charger over BCD0 and BCD1, and
removes the 1.5-k pull-up resistor on USBDP. Removing this
resistor ensures that no current flows from the supply to the USB
host through the USBDP, to comply with the USB 2.0
specification.
Battery-Operated, Bus-Powered USB to MCU with
Battery Charge Detection
Figure 7 illustrates CY7C65216 as a USB-to-microcontroller
interface. The TXD and RXD lines are used for data transfer, and
the RTS# and CTS# lines are used for handshaking. The
SUSPEND pin indicates to the MCU if the device is in USB
Suspend, and the WAKEUP pin is used to wake up CY7C65216,
which in turn issues a remote wakeup to the USB host.
This application illustrates a battery-operated system, which is
bus-powered. CY7C65216 implements the battery charger
detection functionality based on the USB Battery Charging
Specification, Rev. 1.2.
To comply with the second and third requirements, two signals
(BCD0 and BCD1) are configured over GPIO to communicate
the type of USB host charger and the amount of current it can
draw from the battery charger. BCD0 and BCD1 signals can be
configured using the configuration utility.
Battery-operated bus power systems must comply with the
following conditions:
■ Thesystemcanbe powered from the battery(if notdischarged)
andcanbeoperationaliftheVBUSisnotconnectedorpowered
down.
■ The system should not draw more than 100 mAfrom the VBUS
prior to USB enumeration and USB Suspend.
■ The system should not draw more than 500 mA for SDP and
1.5 A for CDP/DCP
Figure 7. USB to MCU Interface with Battery Charge Detection[7, 8, 9]
VDDD
2.2K
VCC
CY7C65216
2.2K
24
VDDD
21
22
SCL
SDA
10K
10K
EN1
SCL
SDA
4
BCD0
BCD1
SYS
BAT
Battery
Charger
(MAX8856)
GPIO_8
GPIO_9
EN2
5
14
3
IN
MCU
nXRES
GPIO_9
BUSDETECT
15
VBUS
OVP
VBUS
D+
D-
10
11
USB
USBDP
USBDM
CONNECTOR
8
9
SUSPEND
WAKEUP
I/O
I/O
GND
12
VCCD
0.1 uF
1 uF
GND
17 16 13
3
VBUS
0.1 uF
4.7 uF
Notes
7. Add a 100-k pull-down resistor on the V
pin for quick discharge.
BUS
8. Refer Figure 8, Figure 9, Figure 10 and the corresponding descriptions for handling VBUS Over Voltage Protection (OVP).
9. BCD and BUSDETECT functionality are not enabled by default. USB-Serial Configuration Utility is provided to enable BCD and BUSDETECT functionality.
Document Number: 002-31602 Rev. **
Page 20 of 27
CY7C65216
In a battery charger system, a 9-V spike on the VBUS is possible. The CY7C65216 VBUS pin is intolerant to voltage above 6 V. In
the absence of over-voltage protection (OVP) on the VBUS line, the VBUS should be connected to BUSDETECT (GPIO configured)
using the resistive network and the output of the battery charger to the VBUS pin of CY7C65216, as shown in Figure 8.
Figure 8. 9 V Tolerant
B
A
Rs
Rs = 10 K
VBUS
VBUS = VDDD
SYS
BAT
Battery Charger
B
CY7C65216
B
A
R1
R2
R1 ≥ 10 kΩ
R2/(R1+R2) = VDDD/VBUS
BUSDETECT
A
GPIO
VBUS > VDDD
VBUS
When the VBUS and VDDD are at the same voltage potential,
the VBUS can be connected to the GPIO using a series resistor
(Rs) (see Figure 9). If there is a charger failure and the VBUS
becomes 9 V, then the 10-k resistor plays two roles. It reduces
the amount of current flowing into the forward-biased diodes in
the GPIO, and it reduces the voltage seen on the pad.
When the VBUS > VDDD, a resistor voltage divider is required
to reduce the voltage from the VBUS down to VDDD for the GPIO
sensing the VBUS voltage (see Figure 10).
The resistors should be sized as follows:
R1 10 k
R2 / (R1 + R2) = VDDD / VBUS
Figure 9. GPIO VBUS Detection, VBUS = VDDD
The first condition limits the voltage and current for the charger
failure situation, as described in the previous paragraph, while
the second condition allows for normal-operation VBUS
detection.
VDDD
BUSDETECT
CY7C65216
VBUS
Rs
Figure 10. GPIO VBUS detection, VBUS > VDDD
VDDD
BUSDETECT
CY7C65216
VBUS
R1
R2
Document Number: 002-31602 Rev. **
Page 21 of 27
CY7C65216
Ordering Information
Table 14 lists the key package features and ordering codes of the CY7C65216. For more information, contact your local sales
representative.
Table 14. Key Features and Ordering Information
Package
Ordering Code
Operating Range
24-pin QFN (4.00 × 4.00 × 0.55 mm, 0.5 mm pitch) (Pb-free)
CY7C65216-24LTXI
Industrial
24-pin QFN (4.00 × 4.00 × 0.55 mm, 0.5 mm pitch) (Pb-free)
– Tape and Reel
CY7C65216-24LTXIT
Industrial
Ordering Code Definitions
CY
7
C
65 XXX - 24 XX X
I
X
X = blank or T
blank = Tray; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
LT = QFN
Number of pins: 24 pins
Part Number: XXXX = 216
Family Code:
65 = USB Hubs
Technology Code: C = CMOS
Marketing Code: 7 = Cypress products
Company ID: CY = Cypress
Document Number: 002-31602 Rev. **
Page 22 of 27
CY7C65216
Package Information
Support currently is planned for the 24-pin QFN package.
Figure 11. 24-pin QFN 4 mm 4 mm 0.55 mm LQ24A 2.65 2.65 EPAD (Sawn)
001-13937 *H
Table 15. Package Characteristics
Parameter Description
Min
-40
–
Typ
25
Max
85
–
Units
°C
TA
THJ
Operating ambient temperature
Package JA
18.4
°C/W
Table 16. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
24-pin QFN
260 °C
30 seconds
Table 17. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
24-pin QFN
MSL 3
Document Number: 002-31602 Rev. **
Page 23 of 27
CY7C65216
Acronyms
Document Conventions
Table 18. Acronyms Used in this Document
Units of Measure
Acronym
BCD
CDC
CDP
DCP
DLL
Description
battery charger detection
Table 19. Units of Measure
Symbol
Unit of Measure
communication driver class
charging downstream port
dedicated charging port
dynamic link library
C
degree Celsius
DMIPS
Dhrystone million instructions per second
k
kilo-ohm
KB
kilobyte
ESD
GPIO
HBM
I2C
electrostatic discharge
general purpose input/output
human-body model
kHz
kV
kilohertz
kilovolt
Mbps
MHz
mm
V
megabits per second
megahertz
millimeter
volt
inter-integrated circuit
microcontroller unit
MCU
OSC
PHDC
PID
oscillator
personal health care device class
product identification
serial communication block
I2C serial clock
SCB
SCL
SDA
SDP
SIE
I2C serial data
standard downstream port
serial interface engine
virtual communication port
Universal Serial Bus
vendor identification
VCOM
USB
VID
Document Number: 002-31602 Rev. **
Page 24 of 27
CY7C65216
Errata
This section describes the errata for the CY7C65216 USB-Serial family. Details include errata trigger conditions, scope of impact, and
available workaround.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
Device Characteristics
CY7C65216
All Variants
Qualification Status
Production
Errata Summary
The following table defines the errata applicability to available USB-Serial devices.
Items
Affected Part Number
CY7C65216
Fix Status
[1.] I2C Reads are slower when USB-Serial is configured as I2C Master.
No Fix
1. I2C Reads are slower when USB-Serial is configured as I2C Master.
I2C reads done by USB-Serial configured as I2C Master are observed to be slower. This is because of
significant delay between the I2C read initiation and the reception of data from the I2C Slave.
Problem Definition
Parameters Affected
Trigger Condition(s)
NA
No specific trigger condition. The delay is observed between every I2C Read initiation from the master
and reception of slave data.
Scope of Impact
Workaround
Fix Status
I2C read operations from the master are slower.
KBA227320 mentions the steps needed to be taken for reducing this delay.
No fix. Workaround is proven.
Document Number: 002-31602 Rev. **
Page 25 of 27
CY7C65216
Document History Page
Document Title: CY7C65216, USB-I2C Single Channel Bridge Controller
Document Number: 002-31602
Submission
Revision
ECN
Description of Change
Date
**
7021631
11/26/2020 Final datasheet to NSO.
Document Number: 002-31602 Rev. **
Page 26 of 27
CY7C65216
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
© Cypress Semiconductor Corporation, 2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware
included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all
rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the
Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-31602 Rev. **
Revised November 26, 2020
Page 27 of 27
相关型号：
CY7C65223D-32LTXI
USB-UART dual channel bridge controller with 4 GPIOs, RS485, software/hardware flow control, 24-pin QFN
INFINEON
©2020 ICPDF网 联系我们和版权申明