CYPD4126-40LQXI [INFINEON]
EZ-PD™ CCG4 Two-Port USB-C & PD;
| 型号： | CYPD4126-40LQXI |
| 厂家： | 
Infineon |
| 描述： | EZ-PD™ CCG4 Two-Port USB-C & PD 光电二极管 |
| 文件： | 总46页 (文件大小：627K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EZ-PD™ CCG4
USB type-c port controller
General description
EZ-PD™ CCG4 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards.
CCG4 provides a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks, power
adapters and docking stations. It can also be used in dual role and downstream facing port applications.
CCG4 uses Infineon’s proprietary M0S8 technology with a 32-bit, 48-MHz Arm® Cortex®-M0 processor with 128 KB
flash and integrates two complete Type-C transceivers including the Type-C termination resistors RP and RD.
Applications
• Notebooks
• Power adapters
• Docking stations
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0 CPU
- 128-KB Flash
- 8-KB SRAM
• Integrated digital blocks
- Up to four integrated timers and counters to meet response times required by the USB-PD protocol
- Four run-time serial communication blocks (SCBs) with re-configurable I2C, SPI, or UART functionality
• Clocks and oscillators
- Integrated oscillator eliminating the need for external clock
• Type-C and USB-PD support
- Integrated USB Power Delivery 3.0 support (only PD 2.0 support for 33-ball CSP part)
- Two integrated USB-PD BMC transceivers
- Integrated UFP[1] (RD) and current sources for DFP[2] (RP) on both Type-C ports
- Integrated dead battery termination for DRP (Power Source/Sink) applications
- Supports two USB Type-C ports
- Integrated VCONN FETs to power EMCA cables
- Integrated fast role swap and extended data messaging (not supported for 33-ball CSP part)
• Low-power operation
- 2.7-V to 5.5-V operation
- Independent supply voltage pin for GPIO that allows 1.71-V to 5.5-V signaling on the I/Os
- Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.5 mA
• System-level ESD on CC pins
- ± 8-kV contact discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C (on 40-pin QFN and
33-ball CSP only)
Notes
1. UFP refers to Power Sink.
2. DFP refers to Power Source.
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
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USB type-c port controller
Logic block diagram
• Hot swappable I/Os
- Port 0 I2C pins and CC1, CC2 pins are hot-swappable
• Packages
- 4.0 mm 4.0 mm, 0.5 mm, 24-pin QFN
- 6.0 mm 6.0 mm, 0.6 mm, 40-pin QFN
- 2.4 mm x 2.5 mm, 0.5 mm, 33-ball CSP
- Supports extended industrial temperature range (–40°C to +105°C)
Logic block diagram
EZ-PDTM CCG4: Single chip type-C controller
MCU Subsystem
I/O Subsystem
Integrated digital blocks
4x TCPWM1
CC_PORT15
arm®
Cortex® - M0 48MHz
4x SCB2
(I2C, SPI, UART)
CC_PORT25
Flash (128KB)
SRAM (8 KB)
Profiles and
configurations
2 x VCONN
FETs
( PORT1)
2 x Baseband MAC
2 x Baseband PHY
2 x VCONN
FETs
( PORT2)
Serial wire debug
GPIOs6
Integrated R3d and R4
d
4x8-bit SAR ADCs
1. Timer, counter, pulse-width modulation block
2. Serial communication block configurable as UART, SPI, or I2C
3. Termination resistor denoting a UFP
4. Current sources to indicate a DFP
5. Configuration channel
6. General purpose input/output
Datasheet
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USB type-c port controller
Table of contents
Table of contents
General description ...........................................................................................................................1
Applications......................................................................................................................................1
Features ...........................................................................................................................................1
Logic block diagram ..........................................................................................................................2
Table of contents...............................................................................................................................3
1 Available firmware and software tools .............................................................................................5
1.1 EZ-PD™ configuration utility ..................................................................................................................................5
2 EZ-PD™ CCG4 block diagram ............................................................................................................6
3 Functional overview .......................................................................................................................7
3.1 CPU and memory subsystem .................................................................................................................................7
3.1.1 CPU .......................................................................................................................................................................7
3.1.2 Flash .....................................................................................................................................................................7
3.1.3 SROM ....................................................................................................................................................................7
3.2 USB-PD sub system (SS) .........................................................................................................................................7
3.3 System resources....................................................................................................................................................8
3.3.1 Power system.......................................................................................................................................................8
3.3.2 Clock system ........................................................................................................................................................8
3.4 Peripherals ..............................................................................................................................................................8
3.4.1 Serial Communication Blocks (SCB) ...................................................................................................................8
3.4.2 Timer/counter/PWM block (TCPWM) ..................................................................................................................9
3.5 GPIO.........................................................................................................................................................................9
4 Pinouts ........................................................................................................................................10
5 Power ..........................................................................................................................................20
6 Application diagrams ....................................................................................................................21
7 Electrical specifications.................................................................................................................24
7.1 Absolute maximum ratings ..................................................................................................................................24
7.2 Device level specifications....................................................................................................................................25
7.2.1 I/O .......................................................................................................................................................................27
7.2.2 XRES....................................................................................................................................................................28
7.3 Digital peripherals.................................................................................................................................................28
7.3.1 Pulse-width modulation (PWM) for GPIO pins..................................................................................................28
7.3.2 I2C .......................................................................................................................................................................29
7.3.3 UART ...................................................................................................................................................................29
7.3.4 SPI.......................................................................................................................................................................29
7.4 Memory..................................................................................................................................................................30
7.5 System resources..................................................................................................................................................30
7.5.1 Power-on-reset (POR) with brown out .............................................................................................................30
7.5.2 SWD interface.....................................................................................................................................................31
7.5.3 Internal main oscillator .....................................................................................................................................31
7.5.4 Internal low-speed oscillator ............................................................................................................................31
7.5.5 Power Down .......................................................................................................................................................32
7.5.6 Analog to digital converter................................................................................................................................32
8 Ordering information ....................................................................................................................33
8.1 Ordering code definitions.....................................................................................................................................33
9 Packaging ....................................................................................................................................34
10 Acronyms ...................................................................................................................................38
11 Document conventions................................................................................................................40
11.1 Units of measure .................................................................................................................................................40
12 References and links to applications collaterals ............................................................................41
12.1 Knowledge base articles.....................................................................................................................................41
12.2 Application notes................................................................................................................................................41
Datasheet
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USB type-c port controller
Table of contents
12.3 Reference designs...............................................................................................................................................42
12.4 Kits .......................................................................................................................................................................42
12.5 Datasheets...........................................................................................................................................................42
Revision history ..............................................................................................................................43
Datasheet
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USB type-c port controller
Available firmware and software tools
1
Available firmware and software tools
1.1
EZ-PD™ configuration utility
The EZ-PD™ configuration utility is a GUI-based Microsoft® Windows application developed by Infineon to guide
a CCGx user through the process of configuring and programming the chip. The utility allows users to:
1. Select and configure the parameters they want to modify
2. Program the resulting configuration onto the target CCGx device.
The utility works with the Infineon supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers
along with a USB interface. This version of the EZ-PD™ Configuration Utility supports configuration and firmware
update operations on CCGx controllers implementing EMCA and Display Dongle applications. Support for other
applications, such as Power Adapters and Notebook port controllers, will be provided in later versions of the
utility.
For the application and its associated documentation, see the USB EZ-PD™ Configuration Utility web page.
Datasheet
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USB type-c port controller
EZ-PD™ CCG4 block diagram
2
EZ-PD™ CCG4 block diagram
CPU subsystem
SWD/TC
EZ-PDTM CCG4
SPCIF
Cortex® - M0
48MHz
Flash
(128 KB)
SRAM
(8 KB)
ROM
(8 KB)
32-bit
FAST MUL
NVIC, IRQMX
AHB-Lite
Read accelerator
SRAM controller
ROM controller
System resources lite
System interconnect (Single Layer AHB)
Peripheral interconnect (MMIO)
Power
Sleep control
WIC
Peripherals
POR
REF
PCLK
PWRSYS
Clock
Clock control
WDT
2 x USB-PD 3.0
IMO
ILO
Reset
Reset control
XRES
Test
DFT Logic
DFT Analog
Pads, ESD
Power modes
Active/Sleep
Deep Sleep
High-speed I/O matrix
28 x GPIOs, 2 OVTs
I/O Subsystem
Figure 1
EZ-PD™ CCG4 block diagram
Datasheet
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USB type-c port controller
Functional overview
3
Functional overview
3.1
CPU and memory subsystem
3.1.1
CPU
The Cortex®-M0 CPU in CCG4 is part of the 32-bit MCU subsystem, which is optimized for low-power operation
with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction
set. This enables fully compatible binary upward migration of the code to higher performance processors such
as the Cortex®-M3 and M4, thus enabling upward compatibility. The Infineon implementation includes a
hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller
(NVIC) block with 32 interrupt inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake
the processor up from the Deep Sleep mode, allowing power to be switched off to the main processor when the
chip is in the Deep Sleep mode. The Cortex®-M0 CPU provides a nonmaskable interrupt (NMI) input, which is made
available to the user when it is not in use for system functions requested by the user.
The CPU also includes a serial wire debug (SWD) interface, which is a 2-wire form of JTAG. The debug configu-
ration used for CCG4 has four break-point (address) comparators and two watchpoint (data) comparators.
3.1.2
Flash
The EZ-PD™ CCG4 device has a flash module with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The flash block is designed to deliver two wait-states (WS) access time
at 48 MHz and with 0-WS access time at 16 MHz. The flash accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash module can be used to emulate EEPROM operation if required.
3.1.3
SROM
A supervisory ROM that contains boot and configuration routines is provided.
3.2
USB PD sub system (SS)
CCG4 has two USB PD sub systems consisting of USB Type-C baseband transceivers and physical-layer logic.
These transceivers perform the BMC and the 4b/5b encoding and decoding functions as well as the 1.2-V analog
front end. This subsystem integrates the required termination resistors to identify the role of the CCG4 solution.
RD is used to identify CCG4 as a UFP in a DRP application. When configured as a DFP, integrated current sources
perform the role of RP or pull-up resistors. These current sources can be programmed to indicate the complete
range of current capacity on VBUS defined in the USB Type-C spec. CCG4 responds to all USB-PD communication.
The USB-PD sub-system contains two 8-bit SAR (successive approximation register) ADCs for analog to digital
conversions. The ADCs include an 8-bit DAC and a comparator. The DAC output forms the positive input of the
comparator. The negative input of the comparator is from a 4-input multiplexer. The four inputs of the multi-
plexer are a pair of global analog multiplex buses an internal bandgap voltage and an internal voltage propor-
tional to the absolute temperature. All GPIO inputs can be connected to the global analog multiplex buses
through a switch at each GPIO that can enable that GPIO to be connected to the mux bus for ADC use. The CC1
and CC2 pins of both Type-C ports are not available to connect to the mux buses.
To support the latest USB-PD 3.0 specification, CCG4 has implemented the fast role swap feature. Fast Role Swap
enables externally powered docks and hubs to rapidly switch to bus power when their external power supply is
removed. For more details, refer to Section 6.3.17 (FR_Swap Message) in the USB-PD 3.0 specification.
CCG4 is designed to be fully inter-operable with revision 3.0 of the USB Power Delivery specification as well as
revision 2.0 of the USB Power Delivery specification.
CCG4 supports Extended Messages containing data of up to 260 bytes. The Extended Messages will be larger than
expected by the USB-PD 2.0 hardware. To accommodate Revision 2.0 based systems, a Chunking mechanism is
implemented such that Messages are limited to Revision 2.0 sizes unless it is discovered that both systems
support the longer Message lengths.
Datasheet
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USB type-c port controller
Functional overview
To/From System Resources
vref
iref
To/ from AHB
From AMUX
2
x 8-bit ADC
per Type-C port
VCONN FET Enable
TxRx Enable
V5V
VCONN
FETs
2 x Digital Baseband PHY
Tx_data
Enable Logic
from AHB
Tx
SRAM
4b5b
Encoder
BMC
Encoder
SOP
Insert
Rp
TX
CC1
RD1
CC2
CRC
Rx_data
to AHB
RX
Rx
4b5b
SOP
BMC
SRAM
Decoder
Detect
Decoder
Ref
DB
Rd
Comp
RD2
Active
Rd
CC control
CC detect
8kV IEC ESD
2 x Analog Baseband PHY
Deep Sleep Reference Enable
Functional, Wakeup Interrupts
Deep Sleep
Vref Iref Gen
RD1 shorted to CC1 and RD2 shorted to CC2 for DRP applications using
bondwire. For DFP applications, RD1 and RD2 not shorted to CC1 and CC2.
Dead Battery (DB) Rd termination removed after MCU boots up
&
vref, iref
Figure 2
USB PD sub system
3.3
System resources
Power system
3.3.1
The power system is described in detail in the section “Power” section on page 20. It provides the assurance that
voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR),
for example) until voltage levels are as required for proper function or generate resets (brown-out detect (BOD))
or interrupts (low voltage detect (LVD)). CCG4 can operate from three different power sources over the range of
2.7 to 5.5 V and has three different power modes, transitions between which are managed by the power system.
CCG4 provides Sleep and Deep Sleep low-power modes.
3.3.2
Clock system
The clock system for CCG4 consists of the internal main oscillator (IMO) and the internal low-power oscillator
(ILO).
3.4
Peripherals
3.4.1
Serial Communication Blocks (SCB)
CCG4 has four SCBs, which can be configured to implement an I2C, SPI, or UART interface. The hardware I2C
blocks implement full multi-master and slave interfaces capable of multimaster arbitration. In the SPI mode, the
SCB blocks can be configured to act as a master or a slave.
In the I2C mode, the SCB blocks are capable of operating at speeds up to 1 Mbps (Fast Mode Plus) and have flexible
buffering options to reduce interrupt overhead and latency for the CPU. These blocks also support I2C that
creates a mailbox address range in the memory of CCG4 and effectively reduce I2C communication to reading
from and writing to an array in memory. In addition, the blocks support 8-deep FIFOs for receive and transmit
which, by increasing the time given for the CPU to read data, greatly reduce the need for clock stretching caused
by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as
defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/Os are implemented with GPIO
in open-drain modes.
The I2C port on SCB 1, SCB 2 and SCB 3 blocks of EZ-PD CCG4 are not completely compliant with the I2C spec in
the following:
• The GPIO cells for SCB 1 to SCB 3 I2C port are not overvoltage-tolerant and, therefore, cannot be hot-swapped
or powered up independently of the rest of the I2C system.
Datasheet
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USB type-c port controller
Functional overview
• Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8-mA
IOL with a VOL maximum of 0.6 V.
• Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong
mode can help meet this spec depending on the bus load.
3.4.2
Timer/counter/PWM block (TCPWM)
CCG4 has up to four TCPWM blocks. Each implements a 16-bit timer, counter, pulse-width modulator (PWM), and
quadrature decoder functionality. The block can be used to measure the period and pulse width of an input signal
(timer), find the number of times a particular event occurs (counter), generate PWM signals, or decode
quadrature signals.
3.5
GPIO
CCG4 has 30 GPIOs that includes the I2C and SWD pins, which can also be used as GPIOs. The I2C pins from only
SCB 0 are overvoltage-tolerant. The number of available GPIOs vary with the part numbers. The GPIO block imple-
ments the following:
• Seven drive strength modes:
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL)
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode)
• Selectable slew rates for dV/dt related noise control to improve EMI
During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or
cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Datasheet
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USB type-c port controller
Pinouts
4
Pinouts
Table 1
Group
Pinout for CYPD4225-40LQXIT, CYPD4226-40LQXIT, and CYPD4236-40LQXIT
Pin
ESD
Pin name
Description
number protection
USB
CC1_P0
9
HBM, IEC USB PD connector detect/Configuration Channel
1
HBM, IEC USB PD connector detect/Configuration Channel
2
type-C
port 0
CC2_P0
7
USB
CC1_P1
22
24
11
12
HBM, IEC USB PD connector detect/Configuration Channel
1
HBM, IEC USB PD connector detect/Configuration Channel
2
type-C
port 1
CC2_P1
VBUS
VBUS_P_CTRL_P0/P1.6
VBUS_C_CTRL_P0/P1.7
HBM
Full rail control I/O for enabling/disabling
Provider load FET of USB Type-C port 0
control
HBM
Full rail control I/O for enabling/disabling
Consumer load FET of USB Type-C port 0/SCB0
(see Table 3 through
Table 6)
VBUS_P_CTRL_P1/P4.2
VBUS_C_CTRL_P1/P4.1
39
38
20
40
19
25
HBM
HBM
HBM
HBM
HBM
HBM
Full rail control I/O for enabling/disabling
Provider load FET of USB Type-C port 1
Full rail control I/O for enabling/disabling
Consumer load FET of USB Type-C port 1
I/O used for discharging VBUS line during voltage
change
I/O used for discharging VBUS line during voltage
change
VCONN_MON_P0 (Monitor VCONN for UVP
condition on port 0)/GPIO
SCB2 (see Table 3 through Table 6) or
VCONN_MON_P1(Monitor VCONN for UVP
condition on port 1)
VBUS_DISCHARGE_P0/
P2.5
VBUS_DISCHARGE_P1/
P4.3
VCONN
control
VCONN_MON_P0/P2.4
SCL_2/VCONN_MON_P1
/P2.7
Over-volta OVP_TRIP_P0/P2.1
ge
OVP_TRIP_P1/P3.0
(OVP)
14
21
HBM
HBM
VBUS over-voltage output indicator for port 0
(active LOW)/SCB0 (See Table 3 through Table 6)
protection
VBUS over-voltage output indicator for port 1
(active LOW)/SCB2 (See Table 3 through Table 6)
Datasheet
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USB type-c port controller
Pinouts
Table 1
Group
Pinout for CYPD4225-40LQXIT, CYPD4226-40LQXIT, and CYPD4236-40LQXIT (continued)
Pin
ESD
Pin name
Description
number protection
GPIOs and VBUS_MON_P0/P2.0
serial
13
HBM
VBUS_MON_P0 (VBUS over-voltage protection
monitoring signal)/GPIO
HPD_P0 (Hot Plug Detect I/O for port 0)/GPIO
HPD_P1 (Hot Plug Detect I/O for port 1)/GPIO
MUX_CTRL_3_P1 (Mux control for port 1) or VBUS
Overcurrent Protection Input for port 1 (active
LOW)
interfaces
HPD_P0/P2.3
HPD_P1/P3.4
MUX_CTRL_3_P1/
OCP_DET_P1/P3.5
18
30
34
HBM
HBM
HBM
MUX_CTRL_2_P1/P3.6
MUX_CTRL_1_P1/P3.7
VBUS_MON_P1/P4.0
VSEL_2_P1/P3.1
35
36
37
27
HBM
HBM
HBM
HBM
MUX_CTRL_2_P1 (Mux control for port 1)/SCB3
(see Table 3 through Table 6)
MUX_CTRL_1_P1 (Mux control for port 2)/SCB3
(see Table 3 through Table 6)
VBUS_MON_P1 (VBUS over-voltage protection
monitoring signal)
VSEL_2_P1 (Voltage selection control for VBUS on
port 1)/GPIO/SCB2 (see Table 3 through Table 6)
I2C_SCL_SCB0_EC/P0.1
I2C_SDA_SCB0_EC/P0.0
I2C_INT_EC/P2.2
I2C_SCL_SCB1_AR/
VSEL_1_P1/P1.0
17
16
15
4
HBM
HBM
HBM
HBM
SCB0/SCB3 (see Table 3 through Table 6)
SCB0/SCB2 (see Table 3 through Table 6)
I2C Interrupt line
SCB1 (see Table 3 through Table 6) or VSEL_1_P1
(Voltage selection control for VBUS on port 1)
I2C_SDA_SCB1_AR/
VSEL_1_P0/P1.3
3
HBM
SCB0/SCB1 (see Table 3 through
Table 6) or VSEL_1_P0 (Voltage selection control
for VBUS on port 0)
I2C_INT_AR_P0/
5
6
HBM
HBM
HBM
I2C interrupt line or VBUS Overcurrent Protection
Input for port 0 (active LOW)
I2C interrupt line/SCB0/SCB1 (see Table 3
through Table 6)
SCB2 (see Table 3 through Table 6) or MUX_C-
TRL_3_P1 (Mux control for port 0) or VSEL_2_P0
(Voltage selection control for VBUS on port 0)
OCP_DET_P0/P1.4
I2C_INT_AR_P1/P1.5
SDA_2/MUX_CTRL_3_P0
/VSEL_2_P0/P2.6
26
SCL_3/MUX_CTRL_1_P0
/P3.3
SDA_3/MUX_CTRL_2_P0
/P3.2
29
28
1
HBM
HBM
HBM
HBM
HBM
SCB3 (see Table 3 through Table 6)
/MUX_CTRL_1_P0 (Mux control for port 0)
SCB3 (see Table 3 through Table 6)
/MUX_CTRL_2_P0 (Mux control for port 0)
SWD_IO/AR_RST#/P1.1
SWD_IO (serial wire debug I/O)/SCB1. (See
Table 3 through Table 6)
SWD_CLK/I2C_CFG_EC/
P1.2
XRES[3]
2
SWD Clock/I2C_CFG_EC
Reset
10
Reset input (active LOW)
Datasheet
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USB type-c port controller
Pinouts
Table 1
Group
Power
Pinout for CYPD4225-40LQXIT, CYPD4226-40LQXIT, and CYPD4236-40LQXIT (continued)
Pin
ESD
Pin name
Description
number protection
V5V_P0
8
HBM
HBM
2.7-V to 5.5-V supply for VCONN FET of Type-C port
0
2.7-V to 5.5-V supply for VCONN FET of Type-C port
1
V5V_P1
23
VDDIO
VCCD
32
33
HBM
HBM
1.71-V to 5.5-V supply for I/Os
1.8-V regulator output for filter capacitor. This pin
cannot drive external load.
VDDD
VSS
31
EPAD
HBM
HBM
VDDD supply input/output (2.7 V to 5.5 V)
Ground supply
1
30
SWD_IO/AR_RST#/P1.1
HPD_P1/P3.4
2
3
4
5
6
7
8
9
29
SWD_CLK/I2C_CFG_EC/P1.2
I2C_SDA_SCB1_AR/VSEL_1_P0/P1.3
I2C_SCL_SCB1_AR/VSEL_1_P1/P1.0
I2C_INT_AR_P0/OCP_DET_P0/P1.4
I2C_INT_AR_P1/P1.5
CC2_P0
SCL_3/MUX_CTRL_1_P0/P3.3
28
27
26
25
24
23
22
21
SDA_3/MUX_CTRL_2_P0/P3.2
VSEL_2_P1/P3.1
SDA_2/MUX_CTRL_3_P0/VSEL_2_P0/P2.6
SCL_2/VCONN_MON_P1/P2.7
CC2_P1
V5V_P1
CC1_P1
V5V_P0
CC1_P0
XRES
OVP_TRIP_P1/P3.0
10
Figure 3
Note
40-pin QFN pin map (Top view) for CYPD4225-40LQXIT, CYPD4226-40LQXIT, and
CYPD4236-40LQXIT
3. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and
enable/disable I/O buffers.
Datasheet
12
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Pinouts
Table 2
Group
Pinout for CYPD4125-40LQXIT and CYPD4126-40LQXIT
Pin
ESD
Pin name
Description
number protection
USB type-C
port 0
CC1_P0
9
7
HBM, IEC USB PD connector detect/Configuration
Channel 1
HBM, IEC USB PD connector detect/Configuration
Channel 2
CC2_P0
VBUS control
VBUS_P_CTRL_P0/P
1.6
VBUS_C_CTRL_P0/P
1.7
11
12
HBM
Full rail control I/O for enabling/disabling.
Provider load FET of USB Type-C port 0.
HBM
Full rail control I/O for enabling/disabling.
Consumer load FET of USB Type-C port 0/SCB0
(see Table 3 through
Table 6).
VBUS_DISCHARGE_
P0/P2.5
VCONN control VCONN_MON_P0/
P2.4
20
19
14
HBM
HBM
HBM
I/O used for discharging VBUS line during
voltage change
VCONN_MON_P0 (Monitor VCONN for OVP
condition on port 0)/GPIO
VBUS over-voltage output indicator for port 0
(active LOW)/SCB0 (see Table 3 through
Table 6)
Overvoltage
protection
(OVP)
OVP_TRIP_P0/P2.1
GPIOs and
P3.1
27
13
HBM
HBM
SCB2 (see Table 3 through Table 6)/GPIO
VBUS_MON_P0 (VBUS over-voltage protection
monitoring signal)/GPIO
serial interfaces
VBUS_MON_P0/P2.0
HPD_P0/P2.3
P3.0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
18
21
30
34
35
36
37
38
39
40
17
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HPD_P0 (Hot Plug Detect I/O for port 0)/GPIO
GPIO/SCB2 (see Table 3 through Table 6)
GPIO
GPIO
GPIO/SCB3 (see Table 3 through Table 6)
GPIO/SCB3 (see Table 3 through Table 6)
GPIO
P4.3
I2C_S-
SCB0/SCB3 (see Table 3 through Table 6)
SCB0/SCB2 (see Table 3 through Table 6)
CL_SCB0_EC/P0.1
I2C_SDA_SCB0_EC/
P0.0
16
HBM
I2C_INT_EC/P2.2
15
4
HBM
HBM
I2C interrupt line
SCB1 (see Table 3 through Table 6)
I2C_S-
CL_SCB1_AR/P1.0
I2C_SDA_SCB1_AR/
VSEL_1_P0/P1.3
3
5
HBM
HBM
SCB0 or SCB1 (see Table 3 through Table 6) or
voltage selection control for VBUS on port 0
I2C_INT_AR_P0/
I2C interrupt line or VBUS Overcurrent
Protection Input for port 0 (Active LOW)
OCP_DET_P0/P1.4
Datasheet
13
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Pinouts
Table 2
Group
Pinout for CYPD4125-40LQXIT and CYPD4126-40LQXIT (continued)
Pin
ESD
Pin name
Description
number protection
GPIOs and
P1.5
SCL_2/P2.7
6
25
26
HBM
HBM
HBM
GPIO/SCB0/SCB1 (see Table 3 through Table 6)
GPIO/SCB2 (see Table 3 through Table 6)
SCB2 (see Table 3 through Table 6) or MUX_C-
TRL_3_P0 (Mux control for port 0), or Voltage
selection control for VBUS on port 0
serial interfaces
SDA_2/
MUX_CTRL_3_P0/
VSEL_2_P0/P2.6
SCL_3/
29
28
HBM
HBM
SCB3 (see Table 3 through Table 6) or MUX_C-
MUX_CTRL_1_P0/P3
.3
TRL_1_P0 (Mux control for port 0)
SDA_3/
SCB3 (see Table 3 through Table 6) or MUX_C-
MUX_CTRL_2_P0/P3
.2
TRL_2_P0 (Mux control for port 0)
SWD_IO/AR_RST#/P
1.1
SWD_CLK/I2C_CFG_
EC/P1.2
1
2
HBM
HBM
Serial wire debug I/O (SWD IO)/SCB1. (see
Table 3 through Table 6) or Alpine Ridge Reset.
SWD Clock/I2C_CFG_EC
Reset
Power
XRES[4]
V5V_P0
10
8
HBM
HBM
Reset input (active LOW)
2.7-V to 5.5-V supply for VCONN FET of Type-C
port 0
VDDIO
VCCD
32
33
HBM
HBM
1.71-V to 5.5-V supply for I/Os
1.8-V regulator output for filter capacitor. This
pin cannot drive external load.
VDDD
VSS
NC
NC
NC
31
EPAD
22
23
24
HBM
HBM
-
-
-
VDDD supply I/O (2.7 V to 5.5 V)
Ground supply
These pins are not bonded
No connect
Note
4. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and
enable/disable IO buffers.
Datasheet
14
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Pinouts
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
24
23
22
21
SWD_IO/AR_RST#/P1.1
SWD_CLK/I2C_CFG_EC/P1.2
P3.4
SCL_3/MUX_CTRL_1_P0/P3.3
SDA_3/MUX_CTRL_2_P0/P3.2
P3.1
I2C_SDA_SCB1_AR/VSEL_1_P0/P1.3
I2C_SCL_SCB1_AR/P1.0
SDA_2/MUX_CTRL_3_P0/VSEL_2_P0/P2.6
SCL_2/P2.7
I2C_INT_AR_P0/OCP_DET_P0/P1.4
P1.5
CC2_P0
V5V_P0
CC1_P0
XRES
NC
NC
NC
P3.0
10
Figure 4
40-pin QFN pin map (Top view) for CYPD4125-40LQXIT and CYPD4126-40LQXIT
Datasheet
15
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Pinouts
Table 3
GPIO
P1.7
P2.1
P0.1
Serial Communication Block (SCB0) configuration
UART
UART_TX_SCB0
UART_RX_SCB0
SPI master
SPI_MOSI_SCB0 SPI_MOSI_SCB0 I2C_SDA_SCB0
SPI_CLK_SCB0 SPI_CLK_SCB0 I2C_SCL_SCB0
SPI slave
I2C master
I2C slave
I2C_SDA_SCB0
I2C_SCL_SCB0
I2C_SCL_SCB0
I2C_SDA_SCB0
–
UART_RTS_SCB0 SPI_MISO_SCB0 SPI_MISO_SCB0 I2C_SCL_SCB0
P0.0
P1.3
UART_CTS_SCB0 SPI_SEL_SCB0
SPI_SEL_SCB0
SPI_SEL_SCB0
I2C_SDA_SCB0
–
–
–
–
SPI_SEL_SCB0
P1.5
SPI_MISO_SCB0 SPI_MISO_SCB0
–
Table 4
GPIO
P1.0
Serial Communication Block (SCB1) configuration
UART
SPI master
SPI slave
I2C master
I2C_SCL_SCB1
I2C slave
I2C_SCL_SCB1
I2C_SDA_SCB1
UART_TX_SCB1
UART_RX_SCB1
SPI_CLK_SCB1
SPI_MISO_SCB1 SPI_MISO_SCB1 I2C_SDA_SCB1
SPI_CLK_SCB1
P1.3
P1.5
P1.1
UART_RTS_SCB1 SPI_SEL_SCB1
UART_CTS_SCB1 SPI_MOSI_SCB1 SPI_MOSI_SCB1
SPI_SEL_SCB1
–
–
–
–
Table 5
GPIO
P2.6
Serial Communication Block (SCB2) configuration
UART
SPI master
SPI slave
I2C master
I2C slave
I2C_SDA_SCB2
I2C_SCL_SCB2
UART_TX_SCB2
UART_RX_SCB2
SPI_MOSI_SCB2 SPI_MOSI_SCB2 I2C_SDA_SCB2
SPI_MISO_SCB2 SPI_MISO_SCB2 I2C_SCL_SCB2
P2.7
P3.1
P0.0
P3.0
UART_RTS_SCB2 SPI_SEL_SCB2
UART_RTS_SCB2 SPI_SEL_SCB2
UART_CTS_SCB2 SPI_CLK_SCB2
SPI_SEL_SCB2
SPI_SEL_SCB2
SPI_CLK_SCB2
–
–
–
–
–
–
Table 6
GPIO
P3.2
Serial Communication Block (SCB3) configuration
UART
SPI master
SPI slave
I2C master
I2C slave
I2C_SDA_SCB3
I2C_SCL_SCB3
UART_TX_SCB3
UART_RX_SCB3
SPI_MOSI_SCB3 SPI_MOSI_SCB3 I2C_SDA_SCB3
SPI_MISO_SCB3 SPI_MISO_SCB3 I2C_SCL_SCB3
P3.3
P3.7
P0.1
P3.6
UART_RTS_SCB3 SPI_SEL_SCB3
UART_RTS_SCB3 SPI_SEL_SCB3
UART_CTS_SCB3 SPI_CLK_SCB3
SPI_SEL_SCB3
SPI_SEL_SCB3
SPI_CLK_SCB3
–
–
–
–
–
–
Datasheet
16
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Pinouts
Table 7
CYPD4126-24LQXIT and CYPD4136-24LQXIT pin list
Pin name Pin number ESD protection Description
P1.2
P1.3
P1.5
CC2
1
2
3
4
5
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
GPIO/SWD_CLK
GPIO
GPIO
Configuration channel 2
2.7-V to 5.5-V supply for VCONN FET of Type-C
Configuration channel 1
Reset input (active LOW)
GPIO
SCB0_I2C_SDA
SCB0_I2C_SCL
HotPlug_Detect
GPIO/VBUS_DISCHARGE
GPIO
GPIO
GPIO
SCB3_I2C_SDA
SCB3_I2C_SCL
V5V
CC1
6
7
8
9
XRES
P1.7
P0.0
P0.1
P2.3
P2.5
P3.0
P2.6
P3.1
P3.2
P3.3
P3.4
GND
VDDD
VDDIO
10
11
12
13
14
15
16
17
18
19
20
21
GPIO
Ground supply
VDDD supply input/output (2.7 V to 5.5 V)
1.71-V to 5.5-V supply for I/Os
1.8-V regulator output for filter capacitor. This pin cannot drive
external load.
VCCD
22
HBM
P3.6
P1.1
VSS
23
24
25/EPAD
HBM
HBM
HBM
GPIO
GPIO/SWD_DATA
Ground supply
1
18
17
16
15
14
13
P1.2
P3.4
P3.3
P3.2
P3.1
P2.6
P3.0
2
3
4
5
6
P1.3
P1.5
CC2
V5V
CC1
24-QFN
Figure 5
24-pin QFN pin map for CYPD4126-24LQXIT and CYPD4136-24LQXIT
Datasheet
17
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Pinouts
Table 8
CYPD4225A0-33FNXIT pin list
ESD
Pin name
CCG4 ball #
Description
protection
P3.1
P3.6
P0.0
P0.1
P1.0
P1.1
P1.2
P1.3
P1.5
P1.7
P2.1
P2.3
P2.6
P2.7
P3.0
P3.2
P3.3
P3.4
C6
A6
F5
G8
C10
B11
A10
B9
B7
G10
F7
G6
D5
D3
G4
C2
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
HBM
GPIO
GPIO
GPIO/optional SWD_DATA
GPIO/optional SWD_CLK
GPIO
GPIO/SWD_DATA
GPIO/SWD_CLK
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
C4
B1
USB PD connector detect/ Configuration Channel 2 - Port 0. This pin
can be hot swappable.
5V supply for VCONN FETs - Port 0.
USB PD connector detect/ Configuration Channel 1 - Port 0. This pin
can be hot swappable. RD1_P0 is shorted to CC1_P0.
Reset input.
CC2_P0
V5V_P0
CC1_P0
XRES
D9
E10
E8
HBM, IEC
HBM
HBM, IEC
HBM
F9
USB PD connector detect/ Configuration Channel 1 - Port 1. This pin
can be hot swappable. RD1_P1 is shorted to CC1_P1.
5V supply for VCONN FETs - Port 1.
USB PD connector detect/ Configuration Channel 2- Port 1. This pin
can be hot swappable.
CC1_P1
V5V_P1
CC2_P1
F3
HBM, IEC
HBM
E4
E2
HBM, IEC
VDDD
VDDIO
B3
B5
HBM
HBM
VDDD supply input/output (2.7 V to 5.5 V)
1.71-V to 5.5-V supply for I/Os
1.8-V regulator output for filter capacitor. This pin cannot drive
external load.
VCCD
A8
HBM
VSS
RD2_P0
RD2_P1
A2, C8, G2
HBM
HBM
HBM
Ground supply
Rd for Port 0.
Rd for Port 1.
D7
E6
Datasheet
18
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Pinouts
10
11
8
6
4
2
9
7
5
3
1
P1.2
VCCD
P3.6
VSS
A
B
C
D
E
F
P1.1
P1.3
P1.5
VDDI O
VDDD
P3.4
P1.0
VSS
P3.1
P3.3
P3.2
CC2_P0
RD2_P0
P2.6
P2.7
V5V_P0
CC1_P0
RD2_P1
V5V_P1
CC2_P1
XRES
P2.1
P0.0
CC1_P1
P1.7
P0.1
P2.3
P3.0
VSS
G
Figure 6
33-CSP ball map for CYPD4225A0-FNXIT (bottom view)
Datasheet
19
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Power
5
Power
The following power system diagram shows the set of power supply pins as implemented in EZ-PD™ CCG4.
CCG4 will be able to operate from three possible external supply sources: V5V_P0 for first Type-C port, V5V_P1 for
second Type-C port and VDDD.
CCG4 has the power supply input V5V_P0 and V5V_P1 pins for providing power to EMCA cables through integrated
VCONN FETs. There are two VCONN FETs in CCG4 per Type-C port to power either CC1 or CC2 pin. These FETs are
capable of providing a minimum of 1W on the CC1 and CC2 pins for the EMCA cables. In USB-PD applications, the
valid levels on V5V_P0 and V5V_P1 supplies can range from 4.85 V to 5.5 V.
The device’s internal operating power supply is derived from VDDD. In UFP mode, CCG4 operates in 2.7 V– 5.5V.
In DFP and DRP modes, it operates in the 3.0 V–5.5 V range.
A separate I/O supply pin, VDDIO, allows the GPIOs to operate at levels from 1.71 V to 5.5 V. The VDDIO pin can be
equal to or less than the voltages connected to the V5V_P0 or V5V_P1 and VDDD pins. The VDDIO supply should
be less than or equal to VDDD supply.
The VCCD output of CCG4 must be bypassed to ground via an external capacitor (in the range of 80 to 120 nF; X5R
ceramic or better).
Bypass capacitors must be used from VDDD and V5V_P0 or V5V_P1 pins to ground; typical practice for systems in
this frequency range is to use a 0.1-µF capacitor on VDDD, V5V_P0 and V5V_P1. Note that these are simply rules
of thumb; for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be
simulated to design and obtain optimal bypassing.
Figure 7 shows an example of the power supply bypass capacitors.
[6]
[7]
CC1_P1
CC2_P1
[5]
V5V_P1
CC1_P0
CC2_P0
VDDD
V5V_P0
VDDIO
Core Regulator
(SRSS-Lite)
VCCD
2 x CC
Tx/Rx
GPIOs
Core
VSS
Figure 7
Notes
EZ-PD™ CCG4 power and bypass scheme example
5. V5V_P0 denoted power supply input for Type-C port 0
V5V_P1 denoted power supply input for Type-C port 1
6. CC1_P0:USB PD connector detect/Configuration Channel 1 for Type-C port 0
CC1_P1:USB PD connector detect/Configuration Channel 1 for Type-C port 1
7. CC2_P0:USB PD connector detect/Configuration Channel 2 for Type-C port 0
CC2_P1:USB PD connector detect/Configuration Channel 2 for Type-C port 1
Datasheet
20
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Application diagrams
6
Application diagrams
Figure 8 and Figure 9 show a dual Type-C port and a single Type-C port Notebook DRP application diagram using
a EZ-PD™ CCG4 device. The Type-C port can be used as a power provider or a power consumer.
In each of these applications, CCG4 communicates with the Embedded Controller (EC), which manages the
Battery Charger Controller (BCC) to control the charging and discharging of internal battery. It also controls the
Data Mux to route the High-speed signals either to the USB chipset (during normal mode) or the DisplayPort
Chipset (during Alternate Mode).The SBU, SuperSpeed, and High-speed lines are routed directly from the Display
Mux of the notebook to the Type-C receptacle.
For the dual Type-C notebook application, these Type-C ports can be power providers or power consumers simul-
taneously. In addition, the CCG4 device controls the transfer of DisplayPort signals over the Type-C interface
using the display mux controllers.
Optional FETs are provided for applications that need to provide power for accessories and cables using VCONN
pin of the Type-C receptacle. VBUS FETs are also used for providing power over VBUS and for consuming power
over VBUS. A VBUS_DISCHARGE FET controlled by CCG4 device is used to quickly discharge VBUS after the Type-C
connection is detached.
Datasheet
21
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Application diagrams
2
4
HS
USB 3.0
SSTX/RX
HOST
TX
4
4
2
RX
MUX
4
4
ML_LANE_[0:3]N
SBU
ML_LANE_[0:3]P
DISPLAY PORT
AUX P/N
CONTROLLER 1
2
HPD_P0
I2C_SCL I2C_SDA
VBUS_SINK
49.9KO
10 O
4.7 uF
4.7 uF
100 KO
2
100 KO
VBUS_C_CTRL_P0
100 KO
2
VBUS_SOURCE
VBUS
OPTIONAL VDDIOSUPPLY. CAN SHORT
TO VDDD IN SINGLE SUPPLY SYSTEMS.
49.9KO
100 KO
4.7 uF
5.0V
5.0V
3.3V VDDIO
100 KO
10 O
VBUS_P_CTRL_P0
100 KO
1µF
SWD_IO/AR_RST#
1µF
1µF
0.1µF
1
2
SWD_CLK/I2C_CFG_EC
200 O
10O
TYPE-C
RECEPTACLE 1
TO DISPLAY_PORT
CONTROLLER 1
VBUS_DISCHARGE_P0
100 KO
HPD_P0
HPD_P1
18
VBUS
100 KO
HPD_P0/GPIO
30
TO DISPLAY PORT
CONTROLLER 2
HPD_P1/GPIO
13 VBUS_MON_P0
10 KO
VBUS_MON_P0/GPIO
0.1µF
19
14
27
VCONN_MON_P0/GPIO
7
9
CC2
CC1
OVP_TRIP_P0
CC2_P0
CC1_P0
VSEL_2_P1
VSEL_2_P1/GPIO
DC/DC
OR
AC-DC
SECONDARY
(5-20V)
VDDIO
VDDIO
100 KO
0.1µF
2.2 KO
11 VBUS_P_CTRL_P0
330pF
330pF
CHARGER
VBUS_P_CTRL_P0
10
21
15
VBUS_DISCHARGE_P0
20
XRES
GND
GND
VBUS_DISCHARGE_P0
2.2 KO
12 VBUS_C_CTRL_P1
34
OVP_TRIP_P1
2.2 KO
CCG4
VBUS_C_CTRL_P0
EMBEDDED
CONTROLLER
(CYPD4225-40LQXIT)
40-QFN
I2C_INT_EC
MUX_CTRL_3_P1/GPIO
MUX_CTRL_2_P1/GPIO
17
16
I2C_SCL_SCB0_EC
35
36
I2C_SDA_SCB0_EC
VSEL_1_P1
VSEL_1_P0
4
3
MUX_CTRL_1_P1/GPIO
VBUS_C_CTRL_P1
I2C_SCL_SCB1_AR/VSEL_1_P1
VBUS_C_CTRL_P1
38
I2C_SDA_SCB1_AR/VSEL_1_P0
I2C_INT_AR_P0
5
6
VBUS_P_CTRL_P1
39
VBUS_P_CTRL_P1
VBUS_DISCHARGE_P1
CC2_P1
I2C_INT_AR_P1
VBUS_DISCHARGE_P1
40
24
VDDIO
2.2 KO 2.2 KO
25
SCL_2/VCONN_MON_P1/GPIO
SDA_2/MUX_CTRL_3_P0/VSEL_2_P0
SCL_3/MUX_CTRL_1_P0/GPIO
SDA_3/MUX_CTRL_2_P0/GPIO
CC2
VSEL_2_P0
I2C_SCL
26
29
22
I2C MASTER
FOR ALT
CC1_P1
CC1
VBUS
100 KO
TYPE-C
I2C_SDA
28
330pF
330pF
MODE MUX
CONTROL
CONNECTED
TO TYPE-C
PORT1 or
RECEPTACLE 2
37
VBUS_MON_P2
EPAD
VBUS_MON_P1
VSS
0.1µF
10 KO
PORT2
VBUS_SINK
VBUS
49.9KO
100 KO
2
4.7 uF
4.7 uF
2
10 O
VBUS_C_CTRL_P1
100 KO
VBUS (5-20V)
VBUS_SOURCE
49.9KO
100 KO
4.7 uF
10 O
VBUS_P_CTRL_P1
100 KO
200 O
10 O
VBUS_DISCHARGE_P1
100 KO
2
4
HS
USB 3.0
HOST
SSTX/RX
TX
4
4
RX
MUX
4
4
ML_LANE_[0:3]N
SBU
2
ML_LANE_[0:3]P
AUX P/N
DISPLAY PORT
CONTROLLER 2
2
HPD_P1
I2C_SDA
I2C_SCL
Figure 8
CCG4 in a dual port notebook application using CYPD4225-40LQXIT
Datasheet
22
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Application diagrams
HS
2
4
USB 3.0
HOST
SSTX/RX
TX
4
4
2
RX
MUX
SBU
4
4
ML_LANE_[0:3]N
ML_LANE_[0:3]P
AUX P/N
DISPLAY PORT
CONTROLLER 1
2
HPD_P0
VBUS_SINK
I2C_SCL
I2C_SDA
CHARGER
49.9KO
10 O
2
4.7 uF
100 KO
100 KO
VBUS_C_CTRL_P0
100 KO
2
VBUS (5-20V)
DC/DC
OR
AC-DC
VSEL_2_P0
VSEL_1_P0
VBUS_SOURCE
VBUS
SECONDARY
(5-20V)
OPTIONAL VDDIO SUPPLY. CAN SHORT
TO VDDD IN SINGLE SUPPLY SYSTEMS.
49.9KO
4.7 uF
4.7 uF
100 KO
5.0V
3.3V VDDIO
100 KO
10 O
VBUS_P_CTRL_P0
100 KO
1µF
1µF
0.1µF
1
200O
SWD_IO/AR_RST#
VBUS_DISCHARGE_P0 10 O
100 KO
2
SWD_CLK/I2C_CFG_EC
HPD_P0/GPIO
TO DISPLAY_PORT
CONTROLLER 1
TYPE-C
RECEPTACLE 1
HPD_P0
18
VBUS
100 KO
13 VBUS_MON_P0
VBUS_MON_P0/GPIO
0.1µF
19
14
10 KO
VCONN_MON__P0/GPIO
OVP_TRIP_P0
7
9
CC2
CC1
CC2_P0
CC1_P0
VDDIO
VDDIO
11 VBUS_P_CTRL_P0
VBUS_DISCHARGE_P0
330pF
330pF
VBUS_P_CTRL_P0
100 KO
0.1µF
10
21
15
20
XRES
GPIO
VBUS_DISCHARGE_P0
GND
2.2 KO
12 VBUS_C_CTRL_P0
2.2 KO
CCG4
VBUS_C_CTRL_P0
2.2 KO
EMBEDDED
CONTROLLER
(CYPD4125-40LQXIT)
40-QFN
I2C_INT_EC
27
30
GPIO
GPIO
GPIO
GPIO
17
16
I2C_SCL_SCB0_EC
I2C_SDA_SCB0_EC
34
35
4
3
I2C_SCL_SCB1_AR
VSEL_1_P0
I2C_SDA_SCB1_AR/VSEL_1_P0
I2C_INT_AR_P0
5
6
VDDIO
36
GPIO
GPIO
GPIO
37
38
39
40
24
22
25
2.2 KO
VSEL_2_P0
SCL_2
GPIO
GPIO
2.2 KO
26
29
SDA_2/MUX_CTRL_3_P0/VSEL_2_P0
SCL_3/MUX_CTRL_1_P0
SDA_3/MUX_CTRL_2_P0
I2C_SCL
I2C MASTER FOR ALT MODE
MUX CONTROL CONNECTED TO
TYPE-C PORT1
GPIO
NC
I2C_SDA
28
EPAD
VSS
NC
Figure 9
CCG4 in a single port notebook application using CYPD4125-40LQXIT
Datasheet
23
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Electrical specifications
7
Electrical specifications
7.1
Absolute maximum ratings
Table 9
Parameter
VDDD_MAX
V5V_P0
Absolute maximum ratings[8]
Description
Min
Typ
–
–
Max
6
6
Unit Details/conditions
Digital supply relative to VSS
Max supply voltage relative
to VSS
–0.5
–
V
V
Absolute max
Absolute max
V5V_P1
Max supply voltage relative
to VSS
Max supply voltage relative
to VSS
–
–
–
–
6
6
V
V
Absolute max
Absolute max
VDDIO_MAX
VGPIO_ABS
IGPIO_ABS
IGPIO_injection
GPIO voltage
Maximum current per GPIO
GPIO injection current,
Max for VIH > VDDD, and
Min for VIL < VSS
–0.5
–25
–0.5
–
–
–
VDDIO + 0.5
V
mA
mA
Absolute max
Absolute max
Absolute max,
current injected per
pin
25
0.5
ESD_HBM
ESD_CDM
Electrostatic discharge
human body model
Electrostatic discharge
charged device model
Pin current for latch-up
Electrostatic discharge
IEC61000-4-2
2200
500
–
–
–
–
V
V
–
–
–
LU
–200
8000
–
–
200
–
mA
V
ESD_IEC_CON
Contact discharge on
CC1 and CC2 pins
ESD_IEC_AIR
Electrostatic discharge
IEC61000-4-2
15000
–
–
V
Air discharge for pins
CC1 and CC2
Note
8. Usage above the absolute maximum conditions listed in Table 9 may cause permanent damage to the de-
vice. Exposure to absolute maximum conditions for extended periods of time may affect device reliability.
The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Tem-
perature Storage Life. When used below absolute maximum conditions but above normal operating condi-
tions, the device may not operate to specification.
Datasheet
24
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Electrical specifications
7.2
Device level specifications
All specifications are valid for –40°C TA 85°C and TJ 100°C, except where noted. Specifications are valid for
3.0 V to 5.5 V, except where noted.
Table 10
Spec ID
DC specifications
Parameter Description
Min Typ Max Unit Details/conditions
SID.PWR#1
VDDD
Power supply input
2.7
–
–
–
5.5
5.5
5.5
V
V
V
UFP applications
voltage
SID.PWR#1_A VDDD
Power supply input
voltage
Power supply input
voltage
3.15
4.85
DFP/DRP applications
–
SID.PWR#26 V5V_P0,
V5V_P1
PWR#13
VDDIO
GPIO power supply
Output voltage
(for core logic)
External regulator voltage
bypass on VCCD
Power supply decoupling
capacitor on VDDD
1.71
–
–
1.8
5.5
–
V
V
–
–
SID.PWR#24 VCCD
SID.PWR#15 CEFC
SID.PWR#16 CEXC
SID.PWR#27 CEXV
80 100 120 nF X5R ceramic or better
0.8
–
1
–
–
µF X5R ceramic or better
µF X5R ceramic or better
Power supply decoupling
capacitor on V5V_P0 and
V5V_P1
0.1
Active mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDD = 3.3 V.
SID.PWR#4
IDD12
Supply current
–
10
–
mA V5V_P0 and V5V_P1 = 5 V,
TA = 25°C,
CC I/O IN Transmit or
Receive, no I/O sourcing
current, CPU at 24 MHz, two
PD ports active
Sleep mode, VDDD = 2.7 to 5.5 V
SID25A
IDD20A
I2C wakeup
WDT ON
IMO at 48 MHz
–
2.5 4.0 mA
VDDD = 3.3 V, TA = 25°C, all
blocks except CPU are ON,
CC I/O ON, no I/O sourcing
current
Deep Sleep mode, VDDD = 2.7 to 3.6 V (Regulator on)
SID34
IDD29
VDDD = 2.7 to 3.6 V
–
–
80
–
–
µA
VDDD = 3.3 V, TA = 25°C
I2C wakeup and WDT ON
SID_DS
IDD_DS
VDDD = 2.7 to 3.6 V
CC wakeup ON
2.5
µA Power source = VDDD,
Type-C not attached, CC
enabled for wakeup, RP
disabled
SID_DS1
IDD_DS1
VDDD = 2.7 to 3.6 V
CC wakeup ON
–
100
–
µA Power source = VDDD,
Type-C not attached, CC
enabledforwakeup, RP and
RD connected at 70 ms
intervals by CPU. RP, RD
connection should be
enabled for both PD ports.
Datasheet
25
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Electrical specifications
Table 10
Spec ID
XRES current
SID307
DC specifications (continued)
Parameter Description
Min Typ Max Unit Details/conditions
10 µA
IDD_XR
Supply current while XRES
asserted
–
1
–
Table 11
Spec ID
AC specifications
Parameter Description
Min Typ Max Unit Details/conditions
SID.CLK#4
SID.PWR#20 TSLEEP
FCPU
CPU frequency
Wakeup from sleep mode
DC
–
–
0
48
–
MHz 3.0 V VDDD 5.5 V
µs Guaranteed by
characterization
SID.PWR#21 TDEEPSLEEP Wakeup from Deep Sleep
mode
–
–
35
µs 24-MHz IMO.
Guaranteed by
characterization.
SID.XRES#5 TXRES
External reset pulse width
5
–
–
5
–
µs Guaranteed by
characterization
ms Guaranteed by
characterization
SYS.FES#1
T_PWR_RDY Power-up to “Ready to
accept I2C / CC command”
25
Datasheet
26
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Electrical specifications
7.2.1
I/O
Table 12
I/O DC specifications
Spec ID
Parameter Description
Min
0.7 × VDDIO
Typ
–
Max
–
Unit Details/conditions
[9]
SID.GIO#37 VIH
SID.GIO#38 VIL
SID.GIO#39 VIH
SID.GIO#40 VIL
SID.GIO#41 VIH
SID.GIO#42 VIL
Input voltage HIGH
threshold
V
V
V
V
V
V
V
V
V
V
CMOS input
Input voltage LOW
threshold
LVTTL input, VDDIO
2.7 V
LVTTL input, VDDIO
2.7 V
–
–
–
–
–
–
–
–
–
–
0.3 ×
VDDIO
–
CMOS input
[9]
[9]
<
0.7× VDDIO
–
<
–
0.3 ×
VDDIO
–
LVTTL input, VDDIO
2.7 V
2.0
–
0.8
–
–
LVTTL input, VDDIO
2.7 V
Output voltage HIGH
level
Output voltage HIGH
level
Output voltage LOW
level
Output voltage LOW
level
–
–
SID.GIO#33 VOH
SID.GIO#34 VOH
SID.GIO#35 VOL
SID.GIO#36 VOL
VDDIO –0.6
IOH = 4 mA at 3 V VDDIO
VDDIO –0.5
–
IOH = 1 mA at 1.8 V
VDDIO
IOL = 4 mA at 1.8 V
VDDIO
–
–
0.4
0.6
IOL = 8 mA at 3 V VDDIO
SID.GIO#5
SID.GIO#6
SID.GIO#16 IIL
RPULLUP
Pull-up resistor
3.5
3.5
–
5.6
5.6
–
8.5
8.5
2
kΩ
kΩ
–
–
RPULLDOWN Pull-down resistor
Input leakage current
(absolute value)
nA 25°C, VDDIO = 3.0 V
SID.GIO#17 CIN
SID.GIO#43 VHYSTTL
Input capacitance
Input hysteresis LVTTL
–
25
–
40
7
–
pF
mV
–
V
DDIO 2.7 V.
Guaranteed by
characterization.
SID.GPIO#44 VHYSCMOS
Input hysteresis CMOS
0.05 ×
VDDIO
–
–
–
mV Guaranteed by
characterization
µA Guaranteed by
characterization
SID69
IDIODE
Current through
protection diode to
VDDIO/Vss
–
100
SID.GIO#45 ITOT_GPIO
Maximum total source
or sink chip current
–
–
200
mA Guaranteed by
characterization
Note
9. VIH must not exceed VDDIO + 0.2 V.
Datasheet
27
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Electrical specifications
Table 13
I/O AC specifications
(Guaranteed by Characterization)
Spec ID
Parameter Description
Min
Typ
Max
Unit Details/conditions
3.3-V VDDIO
,
SID70
TRISEF
TFALLF
Rise time
Fall time
2
–
12
ns
ns
Cload = 25 pF
3.3-V VDDIO
Cload = 25 pF
,
SID71
2
–
12
7.2.2
XRES
Table 14
XRES DC specifications
Spec ID
Parameter Description
Min
Typ
Max
Unit Details/conditions
SID.XRES#1 VIH
SID.XRES#2 VIL
Input voltage HIGH
threshold
Input voltage LOW
threshold
Input capacitance
Input voltage hysteresis
0.7 ×
–
–
V
CMOS input
CMOS input
–
VDDIO
–
–
0.3 × VDDIO
7
V
SID.XRES#3 CIN
SID.XRES#4 VHYSXRES
–
–
–
–
pF
0.05 ×
VDDIO
mV Guaranteed by
characterization
7.3
Digital peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
7.3.1
Pulse-width modulation (PWM) for GPIO pins
Table 15
PWM AC specifications
(Guaranteed by Characterization)
Spec ID
Parameter Description
Min Typ Max Unit Details/conditions
SID.TCPWM.3 TCPWMFREQ Operating frequency
–
–
–
Fc
–
–
–
MHz Fc max = CLK_SYS. Maximum = 48
MHz
ns For all trigger events
SID.TCPWM.4 TPWMENEXT Input trigger pulse
width
2/Fc
2/Fc
SID.TCPWM.5 TPWMEXT
Output trigger pulse
width
ns Minimum possible width of
Overflow, Underflow, and CC
(Counter equals Compare value)
outputs
SID.TCPWM.5A TCRES
SID.TCPWM.5B PWMRES
SID.TCPWM.5C QRES
Resolution of counter
PWM resolution
–
–
–
1/Fc
1/Fc
1/Fc
–
–
–
ns Minimum time between
successive counts
ns Minimum pulse width of PWM
output
ns Minimum pulse width between
quadrature-phase inputs
Quadrature inputs
resolution
Datasheet
28
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Electrical specifications
7.3.2
Table 16
I2C
Fixed I2C AC specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter Description
Min Typ Max Unit Details/conditions
Mbps –
FI2C1
Bit rate
–
–
1
7.3.3
UART
Table 17
Fixed UART AC specifications
(Guaranteed by Characterization)
Spec ID
SID162
Parameter Description
Min Typ Max Unit Details/conditions
Mbps –
FUART
Bit rate
–
–
1
7.3.4
SPI
Table 18
Fixed SPI AC specifications
(Guaranteed by Characterization)
Spec ID
SID166
Parameter Description
Min Typ Max Unit Details/conditions
MHz –
FSPI
SPI operating frequency
(Master; 6X
–
–
8
oversampling)
Table 19
Fixed SPI Master Mode AC specifications
(Guaranteed by Characterization)
Spec ID
Parameter Description
Min Typ Max Unit Details/conditions
SID167
TDMO
MOSI valid after SClock
driving edge
MISO valid before
SClock capturing edge
Previous MOSI data
hold time
–
20
0
–
–
–
15
ns
–
SID168
SID169
TDSI
–
ns Full clock, late MISO sampling
THMO
–
ns Referred to Slave capturing
edge
Table 20
Fixed SPI Slave Mode AC specifications
(Guaranteed by Characterization)
Details/
Spec ID
Parameter Description
Min Typ
Max
Unit
conditions
SID170
TDMI
MOSI valid before Sclock
capturing edge
MISO valid after Sclock
driving edge
MISO valid after Sclock
driving edge in Ext Clk mode
Previous MISO data hold
time
SSEL valid to first SCK valid
edge
40
–
–
–
–
–
–
–
ns
–
SID171
SID171A
SID172
SID172A
TDSO
48 + (3 ×TSCB
)
ns TSCB = TCPU
1/24 MHz
=
TDSO_EXT
THSO
–
48
–
ns
ns
ns
–
0
–
TSSELSCK
100
–
–
Datasheet
29
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Electrical specifications
7.4
Memory
Table 21
Flash AC specifications
Spec ID
SID.MEM#4 TROWWRITE
Parameter
Description
Row (block) write time
(erase and program)
Row erase time
Row program time after
erase
Min Typ Max
Unit Details/conditions
[10]
–
–
20
ms
–
[10]
SID.MEM#3 TROWERASE
SID.MEM#8 TROWPROGRAM
–
–
–
–
13
7
ms
ms
–
–
[10]
[10]
SID178
SID180
TBULKERASE
TDEVPROG
Bulk erase time (128 KB)
Total device program time
–
–
–
–
35
ms
–
[10]
25 second Guaranteed by
characterization
s
SID.MEM#6 FEND
Flash endurance
100K
20
–
–
–
–
–
–
cycles Guaranteed by
characterization
years Guaranteed by
characterization
years Guaranteed by
characterization
SID182
FRET1
FRET2
Flash retention.
TA 55°C, 100 K P/E cycles
Flash retention.
TA 85°C, 10 K P/E cycles
SID182A
10
7.5
System resources
7.5.1
Power-on-reset (POR) with brown out
Table 22
Imprecise POR (PRES)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Unit
conditions
SID185
VRISEIPOR
Rising trip voltage
0.80
–
1.50
1.4
V
V
Guaranteed by
characterization
SID186
VFALLIPOR
Falling trip voltage
0.75
–
Guaranteed by
characterization
Table 23
Spec ID
SID190
Precise POR (POR)
Details/
Parameter
Description
Min
Typ Max
Unit
conditions
VFALLPPOR
BOD trip voltage in active
and sleep modes
1.48
–
–
1.62
1.5
V
Guaranteed by
characterization
Guaranteed by
characterization
SID192
VFALLDPSLP
BOD trip voltage in deep
sleep
1.1
V
Note
10.It can take as much as 20 milliseconds to write to flash. During this time the device should not be reset, or
flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the
XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and
watchdogs. Make certain that these are not inadvertently activated.
Datasheet
30
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Electrical specifications
7.5.2
SWD interface
Table 24
SWD interface specifications
Spec ID
Parameter
Description
Min Typ Max Unit Details/conditions
SID.SWD#1 F_SWDCLK1
3.3 V VDDIO 5.5 V
–
–
–
–
–
–
–
14
MHz SWDCLK ≤1/3 CPU clock
frequency
SID.SWD#2 F_SWDCLK2
1.8 V VDDIO 3.3 V
–
7
MHz SWDCLK ≤1/3 CPU clock
frequency
SID.SWD#3 T_SWDI_-
SETUP
SID.SWD#4 T_SWDI_HOL T = 1/f SWDCLK
D
SID.SWD#5 T_SWDO_VALI T = 1/f SWDCLK
D
SID.SWD#6 T_SWDO_HOL T = 1/f SWDCLK
D
T = 1/f SWDCLK
0.25 × T
–
ns Guaranteed by
characterization
ns Guaranteed by
characterization
0.25 × T
–
–
1
0.5 × T ns Guaranteed by
characterization
–
ns Guaranteed by
characterization
7.5.3
Internal main oscillator
Table 25
IMO AC specifications
Spec ID
Parameter
Description
Min Typ Max Unit Details/conditions
SID.CLK#13 FIMOTOL
Frequency variation at 24, 36,
and 48 MHz (trimmed)
–
–
±2
%
–
SID226
SID229
FIMO
TSTARTIMO
TJITRMSIMO
–
IMO startup time
RMS jitter at 48 MHz
IMO frequency
–
–
24
–
145
–
7
–
48
µs
ps
MHz –
–
–
7.5.4
Internal low-speed oscillator
ILO AC specifications
Table 26
Spec ID
SID234
Parameter Description
Min Typ Max Unit Details/conditions
TSTARTILO
ILO startup time
ILO duty cycle
ILO frequency
–
–
2
ms Guaranteed by
characterization
SID236
TILODUTY
40
20
50
40
60
80
%
Guaranteed by
characterization
SID.CLK#5 FILO
kHz
–
Datasheet
31
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Electrical specifications
7.5.5
Power Down
Table 27
PD DC specifications
Spec ID Parameter
Description
Min Typ Max Unit Details/conditions
SID.PD.1 Rp_std
DFP CC termination for default 64
USB Power
80
96
µA
–
–
–
–
SID.PD.2 Rp_1.5A
SID.PD.3 Rp_3.0A
DFP CC termination for 1.5A
power
166 180 194 µA
304 330 356 µA
4.59 5.1 5.61 kΩ
DFP CC termination for 3.0A
power
SID.PD.4 Rd
UFP CC termination
SID.PD.5 Rd_DB
UFP Dead Battery CC
4.08 5.1 6.12 kΩ All supplies forced to 0 V
and1.0 V applied at CC1 or
termination on CC1 and CC2
CC2. Applicable for DRP
applications only.
SID.PD.15 Vdrop_V5V_C Voltage drop from V5V_P0 and
–
–
100 mV
–
C1
V5V_P1 pins to CC1 pin while
sourcing 215 mA.
CC1 and CC2 pins of Port0 and
Port1 are not short circuit
protected.
Max sourcing current allowed
is 500 mA.
SID.PD.16 Vdrop_V5V_C Voltage drop from V5V_P0 and
–
–
100 mV
–
C2
V5V_P1 pins to CC2 pin while
sourcing 215 mA.
CC1 and CC2 pins of Port0 and
Port1 are not short circuit
protected.
Max allowed sourcing current
is 500 mA.
7.5.6
Analog to digital converter
Table 28
ADC DC specifications
Spec ID
Parameter
Description
Min Typ Max Unit Details/conditions
SID.ADC.1 Resolution
SID.ADC.2 INL
SID.ADC.3 DNL
ADC resolution
Integral nonlinearity
Differential nonlinearity
Gain error
–
8
–
–
–
–
bits
–
–
–
–
–1.5
–2.5
–1.0
1.5 LSB
2.5 LSB
1.0 LSB
SID.ADC.4 Gain Error
Table 29
ADC AC specifications
Spec ID Parameter
SID.ADC.5 SLEW_Max
Description
Rate of change of sampled
voltage signal
Min Typ Max Unit Details/conditions
V/ms –
–
–
3
Datasheet
32
001-98440 Rev. *N
2023-03-30
USB type-c port controller
Ordering information
8
Ordering information
The EZ-PD™ CCG4 part numbers and features are listed in Table 30.
Table 30
EZ-PD CCG4 ordering information
Type-C
PD
Dead Battery Termination
Part Number
Application
TCPWM
Role
Package
Ports
Spec# Termination Resistor
[12]
[12]
[12]
[12]
RP[11], RD[12], RD-DB
RP[11], RD[12], RD-DB
RP[11], RD[12], RD-DB
RP[11], RD[12], RD-DB
40-pin QFN
40-pin QFN
40-pin QFN
40-pin QFN
40-pin QFN
40-pin QFN
24-pin QFN
33-ball CSP
CYPD4125-40LQXIT
CYPD4225-40LQXIT
CYPD4126-40LQXIT
CYPD4226-40LQXIT
CYPD4236-40LQXIT
CYPD4236-40LQXQT
CYPD4126-24LQXIT
CYPD4225A0-33FNXIT
Notebooks, desktops
Notebooks, desktops
Notebooks, desktops
Notebooks, desktops
Docking station
1
2
1
2
2
2
1
2
4
4
2
2
2
2
2
4
PD2.0
PD2.0
PD3.0
PD3.0
PD3.0
PD3.0
PD3.0
PD2.0
Yes
Yes
Yes
Yes
No
DRP
DRP
DRP
DRP
DRP
DFP
DRP
DRP
[12]
RP[11], RD
[12]
RP[11], RD
Dual Port Power Adapter
Notebooks, desktops
Notebooks, desktops
No
[12]
[12]
RP[11], RD[12], RD-DB
RP[11], RD[12], RD-DB
Yes
Yes
8.1
Ordering code definitions
CY PD
4
1/2 2/3 2/3 XX
-
XX XX
X
X
XX
X
T = Tape and reel
ES (optional field): Pre-production engineering samples only.
Temperature range: I = Industrial (-40oC to 85oC);
Q = Extended industrial (-40oC to 105oC)
X = Pb-free
Package type: FN = CSP
Number of pins in the package
Si Rev = A0 (optional field)
Device role: Unique combination of role and termination:
X = 5 or 6
Feature: Unique Applications
2 = Notebooks, desktops; 3 = Docking station
Number of Type-C ports: 1 = 1 Port, 2 = 2 Ports
Product type: 4 = Fourth-Generation Product Family, CCG4
Marketing Code: PD = Power Delivery product family
Company ID: CY = CYPRESS(an Infineon company)
Notes
11.Termination resistor denoting a downstream facing port.
12.Termination resistor denoting an accessory or upstream facing port.
Datasheet
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USB type-c port controller
Packaging
9
Packaging
Table 31
Package characteristics
Parameter Description
Conditions
Min
Typ
Max
Unit
Operating ambient
–
TA
TJ
–40
25
85
°C
temperature
Operating junction
temperature
–
–40
–
100
°C
TJA
TJC
TJA
TJC
TJA
TJC
Package θJA (40-pin QFN)
Package θJC (40-pin QFN)
Package θJA (24-pin QFN)
Package θJC (24-pin QFN)
Package θJA (33-ball CSP)
Package θJC (33-ball CSP)
–
–
–
–
–
–
–
–
–
–
–
–
31
29
22
29
24
1
–
–
–
–
–
–
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Table 32
Solder reflow peak temperature
Maximum time within 5°C of peak
temperature
Package
Maximum peak temperature
24-pin QFN
40-pin QFN
33-ball CSP
260°C
260°C
260°C
30 seconds
30 seconds
30 seconds
Table 33
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2
Package
MSL
24-pin QFN
40-pin QFN
33-ball CSP
MSL 3
MSL 3
MSL 1
Datasheet
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USB type-c port controller
Packaging
001-80659 *A
Figure 10
40-Pin QFN (6 × 6 × 0.6 mm), LR40A/LQ40A 4.6 × 4.6 E-PAD (Sawn) package outline, 001-80659
Datasheet
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USB type-c port controller
Packaging
NOTES
DIMENSIONS
1. ALL DIMENSIONS ARE IN MILLIMETERS.
SYMBOL
MIN. NOM. MAX.
0.60
2. DIE THICKNESS ALLOWABLE IS 0.305 mm MAXIMUM(.012 INCHES MAXIMUM)
3. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. -1994.
A
A1
4. THE PIN #1 IDENTIFIER MUST BE PLACED ON THE TOP SURFACE OF THE
PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF
PACKAGE BODY.
0.00
0.05
A3 (Option 1)
A3 (Option 2)
0.152 REF
0.127 REF
0.25
5. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
6. PACKAGE WARPAGE MAX 0.08 mm.
0.18
2.65
0.30
2.85
b
7. APPLIED FOR EXPOSED PAD AND TERMINALS. EXCLUDE EMBEDDING PART
OF EXPOSED PAD FROM MEASURING.
D
4.00 BSC
2.75
D2
E
8. APPLIED ONLY TO TERMINALS.
4.00 BSC
2.75
9. JEDEC SPECIFICATION NO. REF: N.A.
E2
L
2.65
0.30
2.85
0.50
10. INDEX FEATURE CAN EITHER BE AN OPTION 1 : "MOUSE BITE" OR
OPTION 2 : CHAMFER.
0.40
002-16934 *E
e
0.50 BSC
R
0.09
Figure 11
24-pin QFN package outline
Datasheet
36
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USB type-c port controller
Packaging
002-28711 **
Figure 12
33-ball CSP package outline
Datasheet
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USB type-c port controller
Acronyms
10
Acronyms
Table 34
Acronym
ADC
Acronyms used in this document
Description
analog-to-digital converter
API
Arm®
CC
application programming interface
advanced RISC machine, a CPU architecture
configuration channel
CPU
central processing unit
CRC
CS
cyclic redundancy check, an error-checking protocol
current sense
DFP
downstream facing port
DIO
DRP
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
dual role port
EEPROM
electrically erasable programmable read-only memory
a USB cable that includes an IC that reports cable characteristics (e.g., current rating) to the
Type-C ports
EMCA
EMI
electromagnetic interference
electrostatic discharge
flash patch and breakpoint
full-speed
ESD
FPB
FS
GPIO
IC
general-purpose input/output
integrated circuit
IDE
integrated development environment
Inter-Integrated Circuit, a communications protocol
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
input/output, see also GPIO
low-voltage detect
I2C, or IIC
ILO
IMO
I/O
LVD
LVTTL
MCU
NC
low-voltage transistor-transistor logic
microcontroller unit
no connect
NMI
NVIC
opamp
OCP
OVP
PCB
PD
nonmaskable interrupt
nested vectored interrupt controller
operational amplifier
overcurrent protection
overvoltage protection
printed circuit board
power delivery
PGA
PHY
POR
programmable gain amplifier
physical layer
power-on reset
Datasheet
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USB type-c port controller
Acronyms
Table 34
Acronym
PRES
PSoC™
PWM
RAM
RISC
RMS
RTC
Acronyms used in this document (continued)
Description
precise power-on reset
Programmable System-on-Chip™
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
RX
receive
SAR
SCL
SDA
successive approximation register
I2C serial clock
I2C serial data
S/H
sample and hold
SPI
Serial Peripheral Interface, a communications protocol
static random access memory
serial wire debug, a test protocol
transmit
SRAM
SWD
TX
a new standard with a slimmer USB connector and a reversible cable, capable of sourcing
up to 100 W of power
Type-C
UART
USB
Universal Asynchronous Transmitter Receiver, a communications protocol
Universal Serial Bus
USBIO
XRES
USB input/output, CCG4 pins used to connect to a USB port
external reset I/O pin
Datasheet
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USB type-c port controller
Document conventions
11
Document conventions
11.1
Table 35
Symbol
°C
Units of measure
Units of measure
Unit of measure
degrees Celsius
hertz
Hz
KB
1024 bytes
kHz
k
kilohertz
kilo ohm
Mbps
MHz
M
Msps
µA
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
µF
µs
µV
microsecond
microvolt
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
ohm
ns
pF
picofarad
ppm
ps
s
parts per million
picosecond
second
sps
V
samples per second
volt
Datasheet
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USB type-c port controller
References and links to applications collaterals
12
References and links to applications collaterals
12.1
Knowledge base articles
• Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and CCG4 - KBA210740
• Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™ CCG4 Using PSoC® Programmer and MiniProg3 -
KBA96477
• CCGX Frequently Asked Questions (FAQs) - KBA97244
• Handling Precautions for CY4501 CCG1 DVK - KBA210560
• EZ-PD™ CCGx Hardware - KBA204102
• Difference between USB Type-C and USB-PD - KBA204033
• CCGx Programming Methods - KBA97271
• Getting started with USB Type-C Products - KBA04071
• Type-C to DisplayPort Cable Electrical Requirements
• Dead Battery Charging Implementation in USB Type-C Solutions - KBA97273
• Termination Resistors Required for the USB Type-C Connector – KBA97180
• VBUS Bypass Capacitor Recommendation for Type-C Cable and Type-C to Legacy Cable/Adapter Assem-
blies – KBA97270
• Need for Regulator and Auxiliary Switch in Type-C to DisplayPort (DP) Cable Solution - KBA97274
• Need for a USB Billboard Device in Type-C Solutions – KBA97146
• CCG1 Devices in Type-C to Legacy Cable/Adapter Assemblies – KBA97145
• USB Type-C Controller Supported Solutions – KBA97179
• Termination Resistors for Type-C to Legacy Ports – KBA97272
• Handling Instructions for CY4502 CCG2 Development Kit – KBA97916
• Thunderbolt™ Cable Application Using CCG3 Devices - KBA210976
• Power Adapter Application Using CCG3 Devices - KBA210975
• Methods to Upgrade Firmware on CCG3 Devices - KBA210974
• Device Flash Memory Size and Advantages - KBA210973
• Applications of EZ-PD™ CCG4 - KBA210739
12.2
Application notes
• AN96527 - Designing USB Type-C Products Using Infineon’s CCG1 Controllers
• AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™ CCG2
• AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
• AN210403 - Hardware Design Guidelines for Dual Role Port Applications Using EZ-PD™ USB Type-C
Controllers
• AN210771 - Getting Started with EZ-PD™ CCG4
Datasheet
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USB type-c port controller
References and links to applications collaterals
12.3
Reference designs
• EZ-PD™ CCG2 Electronically Marked Cable Assembly (EMCA) Paddle Card Reference Design
• EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution
• EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution
• EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution
• CCG2 20W Power Adapter Reference Design
12.4
Kits
• CY4502 EZ-PD™ CCG2 Development Kit
• CY4531 EZ-PD CCG3 Evaluation Kit
• CY4541 EZ-PD™ CCG4 Evaluation Kit
12.5
Datasheets
• CYPD1120 Datasheet: USB Power Delivery Alternate Mode Controller on Type-C
• CCG2: USB Type-C Port Controller Datasheet
• CCG3: USB Type-C Controller Datasheet
Datasheet
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USB type-c port controller
Revision history
Revision history
Document
Date
Description of changes
revision
**
2015-09-24 New data sheet.
*A
2015-11-03 Updated Pinouts:
Updated Table 1.
Updated Table 2.
Updated Figure 3.
Updated Figure 4
Updated Application diagrams:
Updated Figure 8.
Updated Figure 9.
Updated Electrical specifications:
Updated Absolute maximum ratings:
Updated Table 9.
Updated Device level specifications:
Updated Table 10.
Updated Digital peripherals:
Updated SPI:
Updated Table 20.
Updated System resources:
Updated Internal main oscillator:
Updated Table 25.
*B
*C
2015-12-14 Updated Electrical specifications:
Updated Device level specifications:
Updated Table 10.
Updated System resources:
Updated Analog to digital converter:
Updated Table 28.
2016-03-02 Updated Features:
Replaced “Sleep: 2 mA” with “Sleep: 2.5 mA”.
Updated Pinouts:
Updated Table 1:
Updated details in “Description” column corresponding to pins 34, 5, and 10.
Updated Table 2:
Updated details in “Description” column corresponding to pins 5, and 10.
Updated Application diagrams:
Updated Figure 8.
Updated Figure 9.
Updated Electrical specifications:
Updated Digital peripherals:
Updated I2C:
Removed table “Fixed I2C DC Specifications”.
Updated UART:
Removed table “Fixed UART DC Specifications”.
Updated SPI:
Removed table “Fixed SPI DC Specifications”.
Updated System resources:
Updated Internal main oscillator:
Removed table “IMO DC Specifications”.
Updated Internal low-speed oscillator:
Removed table “ILO DC Specifications”.
Updated copyright information.
Datasheet
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USB type-c port controller
Revision history
Document
Date
Description of changes
revision
*D
2016-05-31 Updated EZ-PD™ CCG4 block diagram:
Updated Figure 1.
Updated Functional overview:
Updated USB PD sub system (SS):
Updated description (Updated to include support for PD 3.0 features).
Updated Table 33.
*E
*F
2016-06-14 Added Available firmware and software tools.
Updated Application diagrams:
Added description (Added descriptive notes).
Added References and links to applications collaterals.
Updated copyright information.
2017-03-30 Changed status from Preliminary to Final.
Updated Electrical specifications:
Updated Device level specifications:
Updated Table 10:
Changed typical value of IDD29 parameter from 60 µA to 80 µA corresponding to
Condition “VDDD = 3.3 V, TA = 25 °C”.
Updated Ordering information:
Updated Table 30:
Updated part numbers.
Updated to new template.
*G
*H
2017-07-24 Updated Pinouts:
Added Table 7.
Added Figure 5.
Updated Ordering information:
Updated Table 30:
Updated part numbers.
Updated Packaging:
Added spec 002-16934 *A.
Completing Sunset Review.
2017-09-29 Updated Pinouts:
Updated Table 1(Updated caption only).
Updated Table 2 (Updated caption only).
Updated Figure 3 (Updated caption only).
Updated Figure (Updated caption only).
Updated Electrical specifications:
Updated Device level specifications:
Updated Table 10:
Changed minimum value of VDDD parameter from 3 V to 3.15 V corresponding to Test
Condition “DFP/DRP applications”.
*I
2017-11-10 Updated Ordering information:
No change in part numbers.
Updated Ordering code definitions:
Updated details under “Device Role”.
*J
2018-01-25 Updated Electrical specifications:
Updated Device level specifications:
Updated I/O:
Updated Table 12:
Changed maximum value of VOL parameter from 0.6 V to 0.4 V corresponding to Test
Condition “IOL = 4 mA at 1.8 V VDDIO”.
Updated to new template.
Datasheet
44
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USB type-c port controller
Revision history
Document
Date
Description of changes
revision
*K
*L
2018-06-26 Updated Ordering code definitions.
2019-11-15 Changed document status from Final to Preliminary.
Updated Features.
Updated Table 1 through Table 7 and Table 31 through Table 33.
Updated Figure 3 and Figure .
Added CY MPN “CYPD4225A0-33FNXIT” to Table 30.
Added Table 8 for 33-ball CSP part.
Added Figure 6 for 33-ball CSP part.
Added Figure for 33-ball CSP part.
Updated 8.1Ordering code definitions.
Updated spec 002-16934 *B in Packaging.
Updated SCB nomenclatures from SCB1 thru SCB4 to SCB0 thru SCB3 across the entire
document. Updated Port 1 and Port 2 nomenclatures to Port 0 and Port 1 across the
entire document.
*M
*N
2020-12-08 Removed Preliminary status.
Updated Features.
Added CY MPN “CYPD4236-40LQXQT” to Table 30.
Updated Table 31.
Updated Ordering code definitions.
Updated Figure 11 in Packaging (spec 002-16934 *B to *C).
2023-03-30 Migrated to IFX template.
Removed “CYPD4136-24LQXIT”
Updated Figure 11 in Packaging (spec 002-16934 *C to *E).
Updated Table 1.
Updated Table 2.
Updated Table 3.
Updated Table 4.
Updated Table 5.
Updated Table 6
Datasheet
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Edition 2023-03-30
Published by
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characteristics (“Beschaffenheitsgarantie”).
in question please contact your nearest Infineon
Technologies office.
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Document reference
001-98440 Rev. *N
相关型号：
CYPD4255-96BZXI
Microprocessor Circuit, CMOS, PBGA96, 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, MO-225, BGA-96
CYPRESS
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