CYPD5225-96BZXI [INFINEON]
EZ-PD™ CCG5 CCG5C Dual-Single-Port USB-C PD;型号: | CYPD5225-96BZXI |
厂家: | Infineon |
描述: | EZ-PD™ CCG5 CCG5C Dual-Single-Port USB-C PD 光电二极管 外围集成电路 |
文件: | 总44页 (文件大小:989K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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EZ-PD™ CCG5
USB Type-C Port Controller
EZ-PD™ CCG5, USB Type-C Port Controller
General Description
EZ-PD™ CCG5 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG5 provides
a complete dual USB Type-C and USB-Power Delivery port control solution for PCs, notebook, and dock. It can also be used in dual
role and downstream-facing port applications. EZ-PD CCG5 uses Cypress’ proprietary M0WS8 technology with a 32-bit, 48-MHz
Arm® Cortex®-M0 processor with 128-KB flash and integrates two complete Type-C Transceivers including the Type-C termination
resistors, RP and RD. CCG5 also integrates high-voltage regulator. CCG5 is available in 40-QFN (1 port[3]) and 96-BGA (2 ports)
packages.
32-bit MCU Subsystem
■ 48-MHz Arm Cortex-M0 CPU
Applications
■ PCs, Notebook, and Dock
■ 128-KB Flash
■ Thunderbolt hosts and devices
■ 12-KB SRAM
Features
Integrated Digital Blocks
■ Up to two integrated timers and counters to meet response
times required by the USB-PD protocol
Type-C and USB-PD Support
■ Integrated USB Power Delivery (USB-PD) 3.0 support
■ Four run-time serial communication blocks (SCBs) with
reconfigurable I2C, SPI, or UART functionality
■ Two integrated USB-PD Type-C ports
■ Integrated UFP[1] (RD) and current sources for DFP[2] (RP) on
both Type-C ports
Clocks and Oscillators
■ Integrated oscillator eliminating the need for an external clock
■ Integrated dead battery termination for DRP (Power
Source/Sink) applications
Low-Power Operation
■ 2.75 V to 21.5 V operation
■ Integrated VCONN FETs to power EMCA cables
■ Integrated fast role swap and extended data messaging
■ Integrated high-voltage LDO, operational up to 21.5 V
■ Integrated 2x USB Analog Mux
System-Level ESD on CC, D±, and SBU Pins
■ ±8-kVContactDischargeand±15-kVAirGapDischargebased
on IEC61000-4-2 level 4C
■ Integrated 2x SBU Analog Mux
Hot-Swappable I/Os
■ Port 1 I2C pins and CC1, CC2 pins are hot-swappable
■ Integrated 2x USB Charger detect blocks – BC v1.2, Apple
Charging (source only)
■ Integrated overvoltage protection (OVP) and overcurrent
protection (OCP) on the VBUS
Packages
■ Integrated OCP protection on the VCONN
■ 6.0 mm 6.0 mm, 0.6 mm, 40-pin QFN
6.0 mm 6.0 mm, 1.0 mm, 96-ball BGA
■ Supports industrial temperature range (–40 °C to +85 °C)
■ Integrated high-voltage protection on CC and SBU pins to
protectagainstaccidentalshortstotheVBUSpinontheType-C
connector
■ Integrated current sense amplifier that supports high-side
current sensing
■ Integrated gate drivers for external VBUS PFET control on
Type-C Ports
■ Supports high-voltage tolerant PFET-controlled GPIOs
Notes
1. UFP refers to Power Sink.
2. DFP refers to Power Source.
3. NRND (Not Recommended for New Designs). Refer to the CCG5C Datasheet for pin to pin compatible replacement part.
Cypress Semiconductor Corporation
Document Number: 002-17682 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 28, 2019
EZ-PD™ CCG5
Logic Block Diagram
CCG5: Single--Chip Type- C Controller
MCU Subsystem
I/O Subsystem
CC
Integrated Digital Blocks
2x TCPWM
ARM
CORTEX-M0
48 MHz
SCB
VCONN
(I2 C, SPI, UART)
SCB
(I2 C, SPI, UART)
28 GPIO
Pins
Flash
(128KB)
SCB
(I2 C, SPI, UART)
SCB
(I2C, SPI, UART)
SRAM
(12KB)
USB PD Subsystem x2
Baseband MAC
VBUS OVP
Protection
System
Resources
HV Protection
On CC & SBU
Baseband PHY
Under Voltage
Protection
Hi-Voltage LDO
( 21.5V)
2x SBU Analog
Mux Switch
1x8- bit SAR ADC
2x VCONN FETs
2x Gate Drivers
2x2 USB Analog
Mux Switch
VBUS/VCONN OCP
Protection
2x USB Charge
Detect
Document Number: 002-17682 Rev. *M
Page 2 of 43
EZ-PD™ CCG5
Contents
Functional Overview ........................................................4
USB-PD Subsystem (SS) ............................................4
CPU and Memory Subsystem .....................................6
Power System Overview ..................................................7
Peripherals ..................................................................8
GPIO ...........................................................................8
Pinouts ..............................................................................9
Application Diagrams .....................................................16
Electrical Specifications ................................................21
Absolute Maximum Ratings .......................................21
Device-Level Specifications ......................................22
Digital Peripherals .....................................................25
System Resources ....................................................26
Ordering Information ......................................................34
Ordering Code Definitions .........................................34
Packaging ........................................................................35
Acronyms ........................................................................37
Document Conventions .................................................38
Units of Measure .......................................................38
References and Links To Applications Collaterals ....39
Document History Page .................................................40
Sales, Solutions, and Legal Information ......................43
Worldwide Sales and Design Support .......................43
Products ....................................................................43
PSoC® Solutions ......................................................43
Cypress Developer Community .................................43
Technical Support .....................................................43
Document Number: 002-17682 Rev. *M
Page 3 of 43
EZ-PD™ CCG5
Functional Overview
USB-PD Subsystem (SS)
USB-PD Physical Layer
To support the latest USB-PD 3.0 specification, CCG5 has imple-
mented the Fast Role Swap (FRS) feature. The FRS feature
enables externally powered docks and hubs to rapidly switch to
bus power when their external power supply is removed. CCG5
also supports DeepSleep in notebook systems where CCG5 is
expecting FRS detection.
The CCG5 has two USB-PD subsystems consisting of the
USB-PD physical layer (PHY) block and supporting circuits. The
USB-PD PHY consists of a transmitter and receiver that commu-
nicate BMC and 4b/5b encoded data over the CC channel based
on the PD 3.0 standard. All communication is half-duplex. The
PHY practices collision avoidance to minimize communication
errors on the channel.
For more details, refer to Section 6.3.17 in the USB-PD 3.0
specification.
CCG5 is designed to be fully interoperable with revision 3.0 of
the USB Power Delivery specification as well as revision 2.0 of
the USB Power Delivery specification.
In addition, the CCG5 USB-PD block includes all termination
resistors (RP and RD) and their switches as required by the USB
Type-C spec. RP and RD resistors are required to implement
connection detection, plug orientation detection, and for estab-
lishing the USB source/sink roles.
CCG5 supports Extended Messages containing data of up to 260
bytes. The Extended Messages will be larger than expected by
the USB-PD 2.0 hardware. To accommodate Revision 2.0 based
systems, a Chunking mechanism is implemented such that
messages are limited to Revision 2.0 sizes unless it is
discovered that both systems support longer message lengths.
The integrated RP resistor enables CCG5 to be configured as a
DFP. The RP resistor is implemented as a current source and can
be programmed to support the complete range of current
capacity on the VBUS defined in the USB Type-C Spec.
The RD resistor is used to identify CCG5 as a UFP in a DRP
application. The RD resistor on CC pins is required even when
the part is not powered for dead battery termination detection
and charging.
Figure 1. USB-PD Subsystem
To/From System Resources
vref
iref
To/ from AHB
From AMUX
8-bit ADC
VCONN FET Enable
TxRx Enable
V5V
VCONN
FETs
Digital Baseband PHY
Tx_data
Enable Logic
from AHB
Tx
SRAM
4b5b
Encoder
BMC
Encoder
SOP
Insert
Rp
TX
CC1
RD1
CC2
CRC
Rx_data
to AHB
RX
Rx
4b5b
SOP
BMC
SRAM
Decoder
Detect
Decoder
Ref
DB
Rd
Comp
RD2
Active
Rd
CC control
CC detect
8kV IEC ESD
Analog Baseband PHY
Deep Sleep Vref &
Iref Gen (common
for both ports)
Deep Sleep Reference Enable
Functional, Wakeup Interrupts
RD1 shorted to CC1 and RD2 shorted to CC2 for DRP applications using
bondwire. For DFP applications, RD1 and RD2 not shorted to CC1 and CC2.
Dead Battery (DB) Rd termination removed after MCU boots up
vref, iref
Document Number: 002-17682 Rev. *M
Page 4 of 43
EZ-PD™ CCG5
VCONN FET
SBU Mux
CCG5 has two power supply inputs, V5V_P1 and V5V_P2 pins,
for providing power to EMCA cables through integrated VCONN
FETs. There are two VCONN FETs for each PD port to power
either CC1 or CC2 pins. These FETs can provide 1.5-W power
over VCONN on the CC1 and CC2 pins for the EMCA cables.
CCG5 also supports integrated OCP on VCONN.
The SBU switch mux contains 2x1 Mux and a single 2x2 cross
bar SBU switch per the Type-C port. The 2x1 MUX enables you
to select between the Display Port or Thunderbolt alternate
mode and the single-ended 2x2 switch enables you to route
signals to the appropriate SBU1/2 based on CC (Type-C plug)
orientation.
The AUX port of the SBU switch supports only differential
signals. Non-differential signals on the AUX port cause signal
coupling at the output of the SBU switch. The LS port of the SBU
switch supports both non-differential and differential signals.
ADC
The USB-PD subsystem contains one 8-bit successive approxi-
mation register (SAR) for analog-to-digital conversions (ADC).
The ADCs include an 8-bit DAC and a comparator. The DAC
output forms the positive input of the comparator. The negative
input of the comparator is from a 4-input multiplexer. The four
inputs of the multiplexer are a pair of global analog multiplex
busses, an internal bandgap voltage, and an internal voltage
proportional to the absolute temperature. All GPIOs on the chip
have access to the ADCs through the chip-wide analog mux bus.
The CC1 and CC2 pins of both Type-C ports are not available to
connect to the mux bus.
Figure 2. CCG5 SBU Crossbar Switch Block Diagram
USB HS Mux
To meet the HS eye diagram requirements with sufficient margin,
follow these guidelines:
The HS Mux contains a 2×2 cross bar switch to route the system
D± lines to the Type-C top or bottom ports based on the CC
(Type-C plug) orientation. The unused D± top or bottom lines can
be connected to a UART (Debug) port. The maximum operating
frequency of UART must be 1 Mbps.
■ It is recommended to keep the total USB HS signal trace
lengths (USB 2.0 host to CCG5 + CCG5 to Type-C connector
pins) to 4 inches.
■ Total USB HS signal trace lengths can be increased up to 8
inches by adjusting the drive strength on the USB 2.0 host.
The HS Mux also contains charger detection/emulation for
detecting USB BC 1.2 (source only) and Apple terminations. The
charger detection block is connected to the D± from the system
as shown in Figure 3.
■ The differential impedance across the DP/DM signal traces
shall be 90 Ω.
■ Trace width shall be 6 mils.
■ Air Gap (distance between lines) shall be 8 mils.
Figure 3. CCG5 DP/DM Switch Block Diagram
Overvoltage and Undervoltage Protection on VBUS
Overcurrent Protection on VBUS
CCG5 implements an undervoltage/overvoltage (UV/OV)
detection circuit for the VBUS supply. The threshold for OV and
UV detection can be set independently. Both UV and OV detector
have programmable thresholds and is controlled by the
firmware.
CCG5 integrates a high-side current sense amplifier to detect
overcurrent on the VBUS. Overcurrent protection is enabled by
sensing the current through the 10-m sense resistor connected
between the “CSP_Px” and “CSN_Px” pins.
Document Number: 002-17682 Rev. *M
Page 5 of 43
EZ-PD™ CCG5
VBUS Discharge
CPU and Memory Subsystem
CCG5 also has integrated VBUS discharge FETs and resistors
for each port. It is used to discharge VBUS to meet the USB-PD
specification timing on a detach condition and negative voltage
transition.
CPU
The Cortex-M0 CPU in EZ-PD CCG5 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating.
VBUS Regulator
The CPU also includes a serial wire debug (SWD) interface,
which is a 2-wire form of JTAG. The debug configuration used for
EZ-PD CCG5 has four break-point (address) comparators and
two watchpoint (data) comparators.
CCG5 can operate from three power supplies – VSYS, VBUS_P1
and VBUS_P2. CCG5 integrates the regulator (that supports up to
21.5 V) to derive operating supply voltage. The VSYS always
,
takes priority over VBUS_P1/VBUS_P2. In the absence of VSYS
the regulator powers CCG5 either from VBUS_P1 or VBUS_P2.
,
Flash
The EZ-PD CCG5 device has a flash module with a flash accel-
erator, tightly coupled to the CPU to improve average access
times from the flash block. The flash block is designed to deliver
two wait states (WS) access time at 48 MHz. The flash accel-
erator delivers 85% of single-cycle SRAM access performance
on average. Part of the flash module can be used to emulate
EEPROM operation if required.
PFET Gate Driver for VBUS
CCG5 supports the consumer-side and provider-side external
power FET Drivers for PFET. The VBUS_P_CTRL and
VBUS_C_CTRL gate drivers can drive only low or high-Z, thus
requiring an external pull-up. These pins are VBUS
voltage-tolerant.
SROM
Charger Detect
A supervisory ROM that contains boot and configuration routines
is provided.
CCG5 integrates battery charger emulation and detection for
USB BC.1.2, Apple charge (source only).
SRAM
IEC Compliant VBUS, CC, D±, and SBU Lines
CCG5 supports 12-KB SRAM.
The chip supports IEC-compliant ESD protection on VBUS, CC,
D±, and SBU lines.
High-Voltage Tolerant SBU and CC Lines
The chip supports high-voltage tolerant SBU and CC lines. In the
case of SBU/CC short to VBUS through connectors, these lines
will be protected internally.
Document Number: 002-17682 Rev. *M
Page 6 of 43
EZ-PD™ CCG5
Power System Overview
Table 1. CCG5 Power Modes
Mode
Description
Figure 4 provides an overview of the EZ-PD CCG5 power
system. CCG5 can operate from three possible external supply
sources: VBUS_P1/VBUS_P2 (4 V–21.5 V) or VSYS (2.75 V–5.5 V).
The VBUS_P1 and VBUS_P2 supply is regulated inside the chip
with a LDO. The switched supply, VDDD, is either used directly
Power is valid and XRES is not asserted. An
internal reset source is asserted or Sleep
Controller is sequencing the system out of reset.
RESET
ACTIVE
Power is valid and CPU is executing instructions.
Main regulator and most blocks are shut off.
inside some analog blocks or further regulated down to VCCD
,
which powers majority of the core using the regulators. CCG5
has two different power modes: Active and Deep sleep. Transi-
tions between these power modes are managed by the power
system. A separate power domain, VDDIO, is provided for the
GPIOs. The VDDD and VCCD pins, both outputs of regulators, are
brought out for connecting a 1 µF and 0.1 µF capacitor respec-
tively for the regulator stability only. The VCCD pin is not
supported as a power supply. VDDD can source 2 mA (max) for
external load.
DEEP SLEEP Deep Sleep regulator powers logic, but only
low-frequency clock if available.
Figure 4. EZ-PD CCG5 Power System
LDO
LDO
VBUS_P1
VBUS_P2
VDDD
VSYS
CC1_P2
CC2_P2
CC2_P1
V5V_P2
CC1_P1
V5V_P1
VDDIO
Core Regulator
(SRSS-Lite)
VCCD
2 x CC
Tx/Rx
GPIOs
Core
VSS
Document Number: 002-17682 Rev. *M
Page 7 of 43
EZ-PD™ CCG5
Peripherals
Serial Communication Blocks (SCB)
GPIO
EZ-PD CCG5 has 28 GPIOs that includes the I2C and SWD pins,
which can also be used as GPIOs. The I2C pins from only SCB
1 are overvoltage-tolerant. The number of available GPIOs vary
with the part numbers. The GPIO block implements the following:
EZ-PD CCG5 has four SCBs, which can be configured to
implement an I2C, SPI, or UART interface. The hardware I2C
blocks implement full multi-master and slave interfaces capable
of multimaster arbitration. In the SPI mode, the SCB blocks can
be configured to act as a Master/slave.
■ Seven drive strength modes:
❐ Input only
In the I2C mode, the SCB blocks are capable of operating at
speeds up to 1 Mbps (Fast Mode Plus) and have flexible
buffering options to reduce interrupt overhead and latency for the
CPU. These blocks also support I2C that creates a mailbox
address range in the memory of EZ-PD CCG5 and effectively
reduce I2C communication to reading from and writing to an
array in memory. In addition, the blocks support 8-deep FIFOs
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/Os are implemented with GPIO in open-drain modes.
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL)
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■ Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
■ Selectable slew rates for dV/dt related noise control to improve
EMI
The I2C port on SCB 2, SCB 3 and SCB 4 blocks of EZ-PD CCG5
are not completely compliant with the I2C spec in the following:
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
connect to an I/O pin.
■ The GPIO cells for SCB 2 to SCB 4 I2C port are not
overvoltage-tolerant and, therefore, cannot be hot-swapped or
powered up independently of the rest of the I2C system.
■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 10-mA IOL with
a VOL maximum of 0.6 V.
■ Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.
Timer/Counter/PWM Block (TCPWM)
EZ-PD CCG5 has up to two TCPWM blocks. Each implements
a 16-bit timer, counter, pulse-width modulator (TCPWM), and
quadrature decoder functionality. The block can be used to
measure the period and pulse width of an input signal (timer),
find the number of times a particular event occurs (counter),
generate PWM signals, or decode quadrature signals.
Document Number: 002-17682 Rev. *M
Page 8 of 43
EZ-PD™ CCG5
Pinouts
Table 2. Pinout for CYPD5125-40LQXIT[4]
Group Name
Pin Name
CC1
Port
Pin
9
Description
Analog
Analog
Analog
Analog
P4.0
USB PD connector detect/Configuration Channel 1
USB PD connector detect/Configuration Channel 2
USB 2.0 DP from the Host System
USB 2.0 DM from the Host System
UART TX from Host System/GPIO
UART RX from Host System/GPIO
USB 2.0 DP from Bottom of Type-C Connector
USB 2.0 DM from Bottom of Type-C Connector
USB 2.0 DM from Top of Type-C Connector
USB 2.0 DP from Top of Type-C Connector
Sideband Use signal
USB Type-C
CC2
7
DPLUS_SYS
DMINUS_SYS
UART_TX/GPIO
UART_RX/GPIO
DPLUS_BOT
DMINUS_BOT
DMINUS_TOP
DPLUS_TOP
SBU2
23
24
29
30
26
25
27
28
34
35
36
37
38
39
P4.1
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Mux
SBU1
Sideband Use signal
AUX_P
Auxiliary signal for DisplayPort
AUX_N
Auxiliary signal for DisplayPort
LSTX
Thunderbolt Link Management UART Rx
Thunderbolt Link Management UART Tx
LSRX
Full rail control I/O for enabling/disabling Provider load PFET of
USB Type-C Port 1
0: Path ON
VBUS_P_CTRL
VBUS_C_CTRL
Analog
Analog
11
12
High Z: Path OFF
VBUS Control
VBUS OCP
Full rail control I/O for enabling/disabling Consumer load PFET of
USB Type-C port1
0: Path ON
High Z: Path OFF
CSP
CSN
Analog
Analog
P1.6
1
40
6
Current Sense positive Input for VBUS side external Rsense
Current sense negative for other side of external Rsense
SWD I/O/GPIO
SWD_IO/AR_RST/GPIO
SWD Clock/ I2C config line.
I2C config line is used to select the I2C address of HPI interface.
The state of line decides the 7 bit I2C address for HPI.
I2C Config Line Floating: 0x08
SWD_CLK/I2C_CFG_EC/ GPIO
P1.0
2
Pulled up with 1 K: 0x42
Pulled down with 1 K: 0x40
SCB2 I2C Data/GPIO
I2C_SDA_SCB2_TBT/GPIO
I2C_SCL_SCB2_TBT/GPIO
I2C_INT_TBT/GPIO
P1.1
P1.2
P1.3
P2.4
3
4
SCB2 I2C Clock/GPIO
5
TBT interrupt for port 1/GPIO
GPIOs and Serial
Interfaces
OVP_TRIP/I2C_SDA_SCB4/GPIO
14
VBUS overvoltage output indicator for port 1/SCB4 I2C Data
VBUS undervoltage or OCP Output Indicator for Port1 / SCB4 I2C
Clock / GPIO
UV_OCP_TRIP/I2C_SCL_SCB4/GPIO
P2.3
13
I2C_SDA_SCB1_EC/GPIO
I2C_SCL_SCB1_EC/GPIO
I2C_INT_EC/GPIO
P5.0
P5.1
P2.5
P3.0
P3.6
P3.7
16
17
15
18
20
21
SCB1 I2C Data / GPIO
SCB1 I2C Clock / GPIO
Embedded Controller interrupt/GPIO
HPD/GPIO
Hot Plug Detect I/O for port 1/GPIO
I2C_SDA_SCB3 / GPIO / VSEL_2
I2C_SCL_SCB3 / GPIO /VSEL_1
SCB3 I2C Data or GPIO or voltage selection control for VBUS
SCB3 I2C Clock or GPIO or voltage selection control for VBUS
Note
4. NRND (Not Recommended for New Designs). Refer to the CCG5C Datasheet for pin to pin compatible replacement part.
Document Number: 002-17682 Rev. *M
Page 9 of 43
EZ-PD™ CCG5
Table 2. Pinout for CYPD5125-40LQXIT[4] (continued)
Group Name
Pin Name
XRES
Port
Pin
10
Description
Reset
Analog
Power
Power
Reset input (Active LOW)
VBUS
22
19
VBUS Input for Port 1 (4 V to 21.5 V)
VSYS
2.75 V to 5.5 V supply for the system
VDDD supply output
1. VSYS powered - (Min: VSYS-50 mV) 2.7 V to 5.5 V
2. VBUS powered - 3.15 V to 3.65 V
VDDD
Power
31
Power
VDDIO
VCCD
Power
Power
Power
32
33
8
At system-level short the VDDD to VDDIO
1.8 V regulator output for filter capacitor. This pin cannot drive
external load.
V5V
VSS
4.85 V to 5.5 V supply for VCONN FET of Type-C Port 1
Ground
Ground EPAD Ground
Note
4. NRND (Not Recommended for New Designs). Refer to the CCG5C Datasheet for pin to pin compatible replacement part.
Figure 5. 40-Pin QFN Pin Map (Top View) for CYPD5125-40LQXIT[5]
1
2
3
CSP
SWD_CLK / I2C_CLK_CFG
I2C_SDA_SCB2_TBT
I2C_SCL_SCB2_TBT
I2C_INT_TBT
30
29
28
27
UART_RX
UART_TX
DPLUS_TOP
DMINUS_TOP
4
5
6
40-QFN
(Top View)
DPLUS_BOT
DMINUS_BOT
DMINUS_SYS
DPLUS_SYS
26
25
24
23
SWD_IO/ AR_RST
7
8
9
CC2
V5V
CC1
XRES
VBUS
22
21
10
I2C_SCL_SCB3 / VSEL_1
Note
5. NRND (Not Recommended for New Designs). Refer to the CCG5C Datasheet for pin to pin compatible replacement part.
Document Number: 002-17682 Rev. *M
Page 10 of 43
EZ-PD™ CCG5
Table 3. Pinout for CYPD5225-96BZXI, CYPD5235-96BZXI, and CYPD5236-96BZXI
Ball
Group Name
Pin Name
Port
Description
Location
CC1_P1
CC2_P1
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
P4.1
K2
USB PD connector detect/Configuration Channel 1
USB PD connector detect/Configuration Channel 2
USB PD connector detect/Configuration Channel 1
USB PD connector detect/Configuration Channel 2
Auxiliary signal for DisplayPort
USB Type-C Port 1
H2
CC1_P2
K9
USB Type-C Port 2
CC2_P2
K10
B11
C11
A11
A10
A3
AUX_P_P1
AUX_N_P1
Auxiliary signal for DisplayPort
LSRX_P1
Thunderbolt Link Management UART Rx
Thunderbolt Link Management UART Tx
Sideband Use signal
LSTX_P1
SBU1_P1
SBU2_P1
A4
Sideband Use signal
DMINUS_SYS_P1
DPLUS_SYS_P1
UART_RX_P1/GPIO
UART_TX_P1/GPIO
DMINUS_BOT_P1
DPLUS_BOT_P1
DMINUS_TOP_P1
DPLUS_TOP_P1
AUX_P_P2
A7
USB 2.0 DM from the Host System
USB 2.0 DP from the Host System
UART Rx from Host System/GPIO
UART Tx from Host system/GPIO
MUX Type-C Port 1
A6
A9
P4.0
A8
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
P0.2
C1
USB 2.0 DM from Bottom of Type-C Connector
USB 2.0 DP from Bottom of Type-C Connector
USB 2.0 DM from Top of Type-C Connector
USB 2.0 DP from Top of Type-C Connector
Auxiliary signal for DisplayPort
B1
A2
A1
D11
E11
L11
K11
E1
AUX_N_P2
Auxiliary signal for DisplayPort
LSRX_P2
Thunderbolt Link Management UART Rx
Thunderbolt Link Management UART Tx
Sideband Use signal
LSTX_P2
SBU1_P2
SBU2_P2
F1
Sideband Use signal
DMINUS_SYS_P2
DPLUS_SYS_P2
UART_RX_P2/GPIO
UART_TX_P2/GPIO
DMINUS_BOT_P2
DPLUS_BOT_P2
DMINUS_TOP_P2
DPLUS_TOP_P2
G11
F11
J11
H11
L1
USB 2.0 DM from the Host System
USB 2.0 DP from the Host System
UART Rx from Host System/GPIO
UART Tx from Host system/GPIO
MUX Type-C Port 2
P0.1
Analog
Analog
Analog
Analog
USB 2.0 DM from Bottom of Type-C Connector
USB 2.0 DP from Bottom of Type-C Connector
USB 2.0 DM from Top of Type-C Connector
USB 2.0 DP from Top of Type-C Connector
K1
H1
G1
Full rail control I/O for enabling/disabling Provider load PFET
of USB Type-C Port 1
0: Path ON
VBUS_P_CTRL_P1
VBUS_C_CTRL_P1
Analog
Analog
K3
K4
High Z: Path OFF
VBUSControlType-C
Port1
Full rail control I/O for enabling/disabling Consumer load PFET
of USB Type-C Port 1
0: Path ON
High Z: Path OFF
Document Number: 002-17682 Rev. *M
Page 11 of 43
EZ-PD™ CCG5
Table 3. Pinout for CYPD5225-96BZXI, CYPD5235-96BZXI, and CYPD5236-96BZXI (continued)
Ball
Location
Group Name
Pin Name
Port
Description
Full rail control I/O for enabling/disabling Provider load PFET
of USB Type-C Port 2.
0: Path ON
High Z: Path OFF
VBUS_P_CTRL_P2
Analog
B4
VBUSControlType-C
Port2
Full rail control I/O for enabling/disabling Consumer load PFET
of USB Type-C Port 2.
0: Path ON
VBUS_C_CTRL_P2
Analog
B5
High Z: Path OFF
CSP_P1
CSN_P1
CSP_P2
CSN_P2
GPIO
Analog
Analog
Analog
Analog
P3.1
J1
B3
L2
K8
L7
Current Sense Positive Input for P1
Current Sense Negative Input for P1
Current Sense Positive Input for P2
Current Sense Negative Input for P2
GPIO
VBUS OCP
I2C_SDA_SCB4/OVP_TRIP_P1/
GPIO
VBUS overvoltage output indicator for Port 1 / SCB4 I2C Data/
GPIO
P2.4
K5
OVP_TRIP_P2 / GPIO
VSEL_1_P2 / GPIO
UV_OCP_TRIP_P1/GPIO
HPD_P1/GPIO
P2.2
P0.0
P1.4
P3.0
P3.4
L8
L4
VBUS overvoltage output indicator for Port 2 / GPIO
Voltage selection control for VBUS on Port 2 / GPIO
VBUS undervoltage of OCP output indicator for Port 1/GPIO
Hot Plug Detect I/O for Port 1 /GPIO
B6
K7
HPD_P2/GPIO
E10
Hot Plug Detect I/O for Port 2 /GPIO
VCONN_OCP_TRIP_P2/
GPIO
P3.3
B9
VCONN OCP output indicator for Port 2 / GPIO
VCONN_OCP_TRIP_P1/GPIO
UV_OCP_TRIP_P2/GPIO
VSEL_2_P2 / GPIO
P3.5
P1.5
P2.0
B8
B7
VCONN OCP output indicator for Port 1/ GPIO
VBUS undervoltage or OCP output indicator for Port 2/GPIO
Voltage selection control for VBUS on Port 2 / GPIO
H10
I2C_SCL_SCB1_EC/
GPIO
P5.1
P5.0
L6
K6
SCB1 I2C Clock
SCB1 I2C Data
I2C_SDA_SCB1_EC/
GPIO
GPIOs and Serial
Interfaces
I2C_INT_EC/GPIO
I2C_SCL_SCB2_TBT/GPIO
I2C_SDA_SCB2_TBT/GPIO
I2C_INT_TBT_P1/GPIO
I2C_INT_TBT_P2/GPIO
P2.5
P1.2
P1.1
P1.3
P2.1
L5
E2
D2
F2
G2
I2C interrupt line
SCB2 I2C Clock/GPIO
SCB2 I2C Data /GPIO
I2C interrupt line/GPIO
I2C interrupt line
I2C_SCL_SCB3 / VSEL_1_P1
/GPIO
SCB3 I2C Clock/ Voltage selection control for VBUS on Port 1/
GPIO
SCB3 I2C Data / Voltage selection control for VBUS on Port 1
/GPIO
P3.7
P3.6
L10
J10
I2C_SDA_SCB3 / VSEL_2_P1 /
GPIO
I2C_SCL_SCB4/GPIO
I2C_SDA_SCB4/GPIO
SWD_IO/AR_RST# /GPIO
P2.3
P3.2
P1.6
F10
G10
B2
SCB4 I2C Clock /GPIO
SCB4 I2C Data /GPIO
SWD I/O / AR Reset / GPIO
SWD Clock / I2C config line / GPIO.
I2C config line is used to select the I2C address of HPI interface.
The state of line decides the 7 bit I2C address for HPI.
I2C Config Line Floating: 0x08
SWD_CLK/I2C_CFG_EC/GPIO
XRES
P1.0
C2
H6
Pulled up with 1 K: 0x42
Pulled down with 1 K: 0x40
Reset
Analog
Reset input (Active LOW)
Document Number: 002-17682 Rev. *M
Page 12 of 43
EZ-PD™ CCG5
Table 3. Pinout for CYPD5225-96BZXI, CYPD5235-96BZXI, and CYPD5236-96BZXI (continued)
Ball
Location
Group Name
Pin Name
Port
Description
VBUS_P1
VBUS_P2
VSYS
Power
Power
Power
D1
L3
A5
VBUS Input for Port 1 (4 V to 21.5 V)
VBUS Input for Port 2 (4 V to 21.5 V)
2.75 V to 5.5 V supply for the system
VDDD supply output
VDDD
VCCD
Power
Power
D10
B10
1. VSYS powered - (Min: VSYS-50 mV) 2.7 V to 5.5 V
2. VBUS powered - 3.15 V to 3.65 V
Power
1.8 V regulator output for filter capacitor. This pin cannot drive
external load.
VDDIO
V5V_P1
V5V_P2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
DNU
C10
J2
At system-level short the VDDD to VDDIO
4.85 V to 5.5 V supply for VCONN FET of Type-C Port 1
L9
4.85 V to 5.5 V supply for VCONN FET of Type-C Port 2
D5
D6
D7
D8
E4
E5
E6
E7
E8
F4
F5
F6
F7
F8
G4
G5
G6
G7
H7
G8
H4
H5
H8
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Not Connect
Not Connect
Not Connect
Not Connect
NC
DNU
No Connect
NC
DNU
NC
DNU
Document Number: 002-17682 Rev. *M
Page 13 of 43
EZ-PD™ CCG5
Figure 6. 96-Pin BGA Pin Map for CYPD5225-96BXZI, CYPD5235-96BZXI, and CYPD5236-96BZXI
1
2
3
4
5
6
7
8
9
10
11
DPLUS_TO DMINUS_TOP
DPLUS_SY DMINUS_S UART_Tx_P UART_Rx_
A
B
SBU1_P1
SBU2_P1
VSYS
LSTx_P1
LSRx_P1
P_P1
_P1
S_P1
YS_P1
1 / P4.0
P1 / P4.1
SWD_DATA/
TBT_RST# /
P1.6
P1.4 /
P1.5 /
P3.5 /
P3.3 /
DPLUS_BO
T_P1
VBUS_P_C VBUS_C_CT
TRL_P2
CSN_P1
UV_OCP_T UV_OC_TRI VCON_OCP VCON_OCP
VCCD
VDDIO
VDDD
AUX_P_P1
AUX_N_P1
AUX_P_P2
AUX_N_P2
RL_P2
RIP_P1
P_P2
_TRIP_P1
_TRIP_P2
SWD_CLK/
I2C_CFG_EC/
P1.0
DMINUS_B
OT_P1
C
D
E
I2C_SDA_SC
B 2 _ T B T /
P1.1
VBUS_P1
GND
GND
GND
GND
GND
GND
GND
GND
I2C_SCL_SCB
2 _ T B T /
HPD_P2 /
P3.4
SBU1_P2
SBU2_P2
GND
P1.2
I2C_INT_TBT_
P1/ P1.3
DPLUS_SYS_
P2
F
G
H
GND
GND
DNU
GND
GND
DNU
GND
GND
GND
GND
GND
GND
DNU
DNU
SCL_4 / P2.3
DPLUS_TO I2C_INT_TBT_
SDA_4 /
P3.2
DMINUS_SYS
_P2
P_P2
P2/ P2.1
DMINUS_T
OP_P2
VSEL_2_P2/ UART_Tx_P2/
CC2_P1
XRES
P2.0
P0.1
SDA_3/
VSEL_2_P1/
P3.6
UART_Rx_P2
/ P0.2
J
K
L
CSP_P1
V5V_P1
CC1_P1
CSP_P2
I2C_SDA_S I2C_SDA_S
CB4/OVP_T CB1_EC /
DPLUS_BO
T_P2
VBUS_P_C VBUS_C_C
H P D _ P 1 /
P3.0
CSN_P2
CC1_P2
V5V_P2
CC2_P2
LSTx_P2
LSRx_P2
TRL_P1
TRL_P1
RIP_P1/P2.4
P5.0
I2C_SCL_S
CB1_EC /
P5.1
SCL_3 /
VSEL_1_P1/
P3.7
DMINUS_B
OT_P2
VSEL_1_P2 I2C_INT_EC
/P0.0 / P2.5
OVP_TRIP_
P2/P2.2
VBUS_P2
P3.1
Type-C Port
1
Type-C Port
2
Power Pins
GND
GPIOs
Document Number: 002-17682 Rev. *M
Page 14 of 43
EZ-PD™ CCG5
Table 4 through Table 7 provide the various configuration options for the serial interfaces.
Table 4. Serial Communication Block (SCB1) Configuration
QFN Pin BGA Pin
UART
SPI
I2C
GPIO Functionality
16
17
K6
L6
–
–
–
–
I2C_SDA_SCB1
I2C_SCL_SCB1
GPIO
GPIO
VCONN OCP output indicator for port 1/
GPIO
B8
UART_CTS_SCB1
–
–
20
21
J10
L10
UART_TX_SCB1
UART_RX_SCB1
SPI_SEL_SCB1
SPI_MISO_SCB1
–
–
I2C_SDA_SCB3/ VSEL_2_P1 /GPIO
I2C_SCL_SCB3 / VSEL_1_P1/GPIO
18
29
30
K7
A8
A9
UART_RTS_SCB1
–
–
–
–
HPD_P1/GPIO
–
–
SPI_MOSI_SCB1
SPI_CLK_SCB1
UART_TX_P1/GPIO
UART_RX_P1/GPIO
Note: UART TX and RX of the SCB1 is also the I2C SDA and SCL of the SCB3. So if SCB 3 is in use, then SCB1 cannot be used for
UART and SPI.
Table 5. Serial Communication Block (SCB2) Configuration
QFN Pin BGA Pin
UART
SPI Master
I2C Slave
GPIO Functionality
SWD_CLK/I2C_CFG_EC/GPIO
I2C_SDA_SCB2_TBT/GPIO
I2C_SCL_SCB2_TBT/GPIO
I2C_INT_TBT_P1/GPIO
2
3
4
5
C2
D2
E2
F2
UART_RX_SCB2
UART_TX_SCB2
UART_CTS_SCB2
UART_RTS_SCB2
SPI_SEL_SCB2
SPI_MOSI_SCB2
SPI_MISO_SCB2
SPI_CLK_SCB2
–
I2C_SDA_SCB2
I2C_SCL_SCB2
–
Table 6. Serial Communication Block (SCB3) Configuration
QFN Pin BGA Pin
UART
–
SPI Master
–
I2C Slave
GPIO Functionality
20
21
J10
L10
G2
H10
L4
I2C_SDA_SCB3 UART_TX_SCB1/VSEL_2_P1 /GPIO
I2C_SCL_SCB3 UART_RX_SCB1 / VSEL_1_P1/GPIO
–
–
UART_CTS_SCB3
UART_TX_SCB3
UART_RX_SCB3
UART_RTS_SCB3
SPI_MISO_SCB3
SPI_MOSI_SCB3
SPI_SEL_SCB3
SPI_CLK_SCB3
–
–
–
–
I2C_INT_TBT_P2/GPIO
VSEL_2_P2 / GPIO
VSEL_1_P2 / GPIO
OVP_TRIP_P2 / GPIO
L8
Table 7. Serial Communication Block (SCB4) Configuration
QFN Pin BGA Pin
UART
SPI Master
–
I2C Slave
GPIO Functionality
13
14
F10
G10
L7
–
I2C_SCL_SCB4 GPIO
I2C_SDA_SCB4 GPIO
UART_TX_SCB4
UART_CTS_SCB4
UART_RX_SCB4
UART_RTS_SCB4
SPI_MOSI_SCB4
SPI_MISO_SCB4
SPI_SEL_SCB4
SPI_CLK_SCB4
–
–
–
GPIO
B9
VCONN_OCP_TRIP_P2/GPIO
HPD_P2/GPIO
E10
Document Number: 002-17682 Rev. *M
Page 15 of 43
EZ-PD™ CCG5
Application Diagrams
Figure 8 and Figure 9 illustrate the Dual Type-C Port and Single[6] Type-C port Thunderbolt Notebook DRP application diagrams using
a CCG5 device respectively. The Type-C port can be used as a power provider/power consumer.
The CCG5 device communicates with the embedded controller (EC), which manages the Battery Charger Controller (BCC) to control
the charging and discharging of the internal battery. It also updates the Thunderbolt Controller via I2C to route the High-speed signals
coming from the Type-C port to the USB host (during normal mode) or the Graphics processor unit (during Display port Alternate
mode) or the Thunderbolt Host (during Thunderbolt Alternate mode) based on the alternate mode negotiation.
For the dual Type-C notebook application (Figure 8), these Type-C ports can be power providers or power consumers simultaneously.
The CCG5 device controls the transfer of USB 2.0 D± lines from the top and bottom of the Type-C receptacle to the D± lines of the
USB Host controller. CCG5 also handles the routing of SBU1 and SBU2 lines from the Type-C receptacle to the Thunderbolt controller
for the Link management. CCG5 offers ESD Protection on D± and SBU lines as well as VBUS Short protection on SBU and CC lines.
The CCG5 device has an integrated VCONN FET for applications that need to provide power for accessories and cables using the
VCONN pin of the Type-C receptacle. VBUS FETs are also used for providing power over VBUS and for consuming power over VBUS.
The 10-m resistor between the 5-V supply and FETs is used for overcurrent detection on the VBUS. The VBUS_P_CTRL pin of
CCG5 has an in-built VBUS monitoring circuit that can detect OVP and UVP on VBUS.
CCG5 also has an in-built VBUS discharge circuit that is used to quickly discharge VBUS after the Type-C connection is detached.
The internal resistance (as listed in Table 41) of this VBUS discharge circuit is expected to be sufficient for typical CCG5 applications.
However, customers can include an optional VBUS discharge circuit as shown in Figure 7 using any available GPIO. This optional
circuit can be added to the design if the discharge time using the in-built VBUS discharge circuit needs to be further reduced; that is,
VBUS transition time from higher to lower voltages can be further reduced using the external VBUS discharge circuit shown in Figure 7.
This optional external circuit comprises of a N-channel MOSFET and the CCG5 device can be used to enable or disable it as
appropriate.
Figure 7. Optional External VBUS Discharge Circuit
V BU S
200
C C G 5 G P IO Pin
(VB U S _D ISC H AR G E _PIN )
100 K
Note
6. NRND (Not Recommended for New Designs). Refer to the CCG5C Datasheet for pin to pin compatible replacement part.
Document Number: 002-17682 Rev. *M
Page 16 of 43
EZ-PD™ CCG5
Figure 8. CCG5 in a Dual Port Notebook Application using CYPD5225-96BZXI
VBUS_OUT_P2
VBUS_OUT_P1
5V
5V
BSC030P03NS3
BSC030P03NS3
BSC030P03NS3
BSC030P03NS3
8
7
6
5
8
7
6
5
0.01
0.01
8
7
6
5
8
7
6
5
3
2
1
3
2
1
3
2
1
3
2
1
10µF
50V
Provider
Path
Provider
Path
10µF
50V
1µF
35V
1µF
35V
Power
Subsystem
49.9K
49.9K
1%
1%
4
4
4
4
Consumer
Path
Consumer
Path
BSC030P03NS3
8
BSC030P03NS3
8
7
6
5
BSC030P03NS3
BSC030P03NS3
8
7
6
5
7
8
3
2
1
3
3
2
1
7
6
5
3
2
1
2
1
6
5
K8
CSN_P2
L2
CSP_P2
B3
CSN_P1
J1
CSP_P1
1µF
35V
1µF
35V
K3
K4
B4
B5
VBUS_P_CTRL_P1
VBUS_C_CTRL_P1
49.9K
1%
49.9K
1%
4
VBUS_P_CTRL_P2
VBUS_C_CTRL_P2
4
4
4
VBUS
VBUS
10µF
50V
VDDD
1K
10µF
50V
Note:
CCG5 devices I2C address is determined by SWD_CLK pin.
1K resistors not populated I2C address 0x08 (default)
1K resistor connected to GND I2C address 0x40
1K resistor connected to VDDD
=
C2
A8
X
SWD_CLK/I2C_CFG_EC/P1.0
UART_TX_P1/P4.0
UART_RX_P1/P4.1
=
1K
A9
X
=
I2C address 0x42
A4
A3
A1
B8
A8
SBU2
SBU2_P1
F1
E1
G1
H1
K1
L1
B8
A8
SBU2
SBU2_P2
SBU1_P1
SBU1
D+
A6
A7
B6
B7
SBU1
D+
SBU1_P2
DPLUS_TOP_P1
A6
A7
B6
B7
A2
DPLUS_TOP_P2
DMINUS_TOP_P1
D-
B1
C1
DMINUS_TOP_P2
D-
DPLUS_BOT_P1
DMINUS_BOT_P1
D+
D+
DPLUS_BOT_P2
DMINUS_BOT_P2
D-
B5
A5
D-
H2
K2
CC2_P1
CC1_P1
CC2
CC1
B5
A5
K10
K9
CC2_P2
CC1_P2
CC2
CC1
390pF
390pF
390pF
390pF
L8
X
OVP_TRIP_P2/P2.2
VDDD
Type-C
Receptacle
2
Type-C
Receptacle
1
L10
SCL_3/VSEL_1_P1/P3.7
UART_TX_P2/P0.1
X
D10
VDDD
H11
X
J11
X
CCG5
(CYPD5225-96BZXI)
96-BGA
1µF
0.1 µF
C10
A5
VDDIO
UART_RX_P2/P0.2
3.3V
G10
X
F10
X
J10
X
B7
X
B8
X
B9
X
B6
X
SDA_4/P3.2
SCL_4/P2.3
VSYS
VCCD
0.1µF
10V
1µF
10V
B10
0.1µF
SDA_3/VSEL_2_P1/P3.6
UV_OCP_TRIP_P2/P1.5
VCON_OCP_TRIP_P1/P3.5
5V (from System)
J2
L9
GND
V5V_P1
V5V_P2
GND
VCON_OCP_TRIP_P2/P3.3
UV_OCP_TRIP_P1/P1.4
3.3V
L4
X
H6
L5
VSEL_1_P2/P0.0
VSEL_2_P2/P2.0
NC1
XRES
2.2 K
2.2 K
H10
X
0.1µF
2.2 K
2.2 K
2.2 K
2.2 K
G8
X
2.2 K
I2C_INT_EC/P2.5
H4
X
NC2
Embedded
Controller
L6
K6
E2
I2C_SCL_SCB1_EC/P5.1
I2C_SDA_SCB1_EC/P5.0
H5
X
NC3
NC4
H8
X
I2C_SDA_SCB4/
OVP_TRIP_P1/P2.4
K5
X
L7
X
I2C_SCL_SCB2_TBT/P1.2
I2C_SDA_SCB2_TBT/P1.1
I2C_INT_TBT_P1/P1.3
D2
F2
P3.1
GND
D5, D6, D7, D8, E4, E5,
E6, E7, E8, F4, F5, F6, F7,
F8, G4, G5, G6, G7, H7
G2
I2C_INT_TBT_P2/P2.1
VBUS_OUT_P2
VBUS_OUT_P1
3.3V
D1
L3
VBUS_P1
VBUS_P2
10K
100K
3.3V
100K
B2
SWD_IO/TBT_RST/P1.6
AUX_N_P1
C11
B11
A10
A11
E11
D11
AUX_N_P2
AUX_P_P2
LSTX_P2
0.1 µF
0.1µF
0.1 µF
0.1 µF
AUX_P_P1
LSTX_P1
K11
L11
LSRX_P2
LSRX_P1
8
8
100K
Data Lines
100K
Data Lines
3.3V
3.3V
10K
DNP
10K
DNP
K7
E10
HPD_P1/P3.0
HPD_P2/P3.4
D+_SYS_P2
F11
D-_SYS_P2 D+_SYS_P1
G11 A6
D-_SYS_P1
A7
100K
100K
Note:
Route D+ and D- Host lines to system
USB Host Controller
DPSRC_HPD
DPSRC_HPD
LSRX
LSTX
LSRX
LSTX
DPSRC_AUX_P
DPSRC_AUX_P
DPSRC_AUX_N
I2C_SCL
DPSRC_AUX_N
RESET_N
Thunderbolt Controller
I2C_SDA
I2C_INT_P1
I2C_INT_P2
USB2_D_P
USB2_D_N
USB2_D_P
USB2_D_N
Note:
Follow recommendations from manufacturer
for Thunderbolt Controller connections
X
X
X
X
Document Number: 002-17682 Rev. *M
Page 17 of 43
EZ-PD™ CCG5
Figure 9 illustrates a Single Port Thunderbolt Notebook DRP application diagram using CYPD5125-40LQXIT[7]
.
Figure 9. CCG5 in a Single Port Notebook Application using CYPD5125-40LQXIT[7]
VBUS_OUT
5 V
BSC030P03NS3
BSC030P03NS3
8
7
6
5
0.01
8
7
6
5
Provider Path
3
2
1
3
2
1
10 µF
50 V
1 µF
35 V
Power
Subsystem
49.9K
1%
4
4
Consumer Path
BSC030P03NS3
BSC030P03NS3
8
7
6
5
8
7
3
2
1
3
Note:
2
1
6
5
40
CSN
1
1µF
35V
CCG5 device s I2C address is determined by SWD_CLK pin.
1K resistors not populated = I2C address 0x08 (default)
1K resistor connected to GND = I2C address 0x40
1K resistor connected to VDDD = I2C address 0x42
VDDD
1 K
11
12
CSP
VBUS_P_CTRL
VBUS_C_CTRL
49.9K
1%
4
4
2
SWD_CLK/I2C_CFG_EC/P1.0
1 K
VDDD
31
VDDD
VBUS
1µF
10 µF
50 V
0.1 µF
32
19
VDDIO
3.3 V
VSYS
VCCD
1 µF
29
X
0.1 µF
UART_TX/P4.0
UART_RX/P4.1
33
30
X
0.1 µF
34
35
28
B8
A8
5 V (from System)
VBUS_OUT
SBU2
SBU1
D+
SBU2
SBU1
8
VCONN_V5V
VBUS
A6
A7
B6
B7
DPLUS_TOP
22
10
27
DMINUS_TOP
3.3 V
D-
CCG5
26
25
XRES
[7]
DPLUS_BOT
D+
0.1µF
(CYPD5125-40LQXIT
40-QFN
)
DMINUS_BOT
D-
2.2 K
B5
A5
7
9
CC2
CC1
CC2
CC1
2.2 K
2.2 K
15
I2C_INT_EC/P2.5
3.3 V
EMBEDDED
CONTROLLER
17
16
390 pF
390 pF
I2C_SCL_SCB1_EC/P5.1
I2C_SDA_SCB1_EC/P5.0
TYPE-C
RECEPTACLE
10 K
DNP
18
HPD/P3.0
20
100 K
X
SDA_3/VSEL_2/P3.6
3.3 V
21
14
SCL_3/VSEL_1/P3.7
X
3.3V
SDA_4/OVP_TRIP/P2.4
X
13
2.2 K
SCL_4/UV_OCP_TRIP/P2.3
X
DPSRC_HPD
100 K
10 K
2.2 K
2.2 K
8
6
SWD_IO/TBT_RST/P1.6
AUX_N
4
3
RESET_N
I2C_SCL_SCB2_TBT/P1.2
I2C_SDA_SCB2_TBT/P1.1
37
DPSRC_AUX_N
Data Lines
0.1 µF
0.1 µF
36
38
39
GND
AUX_P
LSTX
DPSRC_AUX_P
LSTX
5
I2C_INT_TBT/P1.3
EPAD
41
Thunderbolt Controller
LSRX
LSRX
DPLUS_SYS
23
DMINUS_SYS
24
100 K
Note:
Route D+ and D - Host lines to system
USB Host Controller
X
X
Note:
Follow recommendations from manufacturer for
Thunderbolt Controller connections
Note
7. NRND (Not Recommended for New Designs). Refer to the CCG5C Datasheet for pin to pin compatible replacement part.
Document Number: 002-17682 Rev. *M
Page 18 of 43
EZ-PD™ CCG5
Figure 10 illustrates the Dual Type-C Port Thunderbolt device/dock upstream application diagram using a CCG5 device. The CCG5
device communicates with the power system over I2C, which manages the power provided to the upstream Type-C ports. It also
updates the Thunderbolt Controller over I2C based on the alternate mode negotiation to sink Thunderbolt or USB or DisplayPort Data.
The CCG5 device controls the transfer of USB 2.0 D± lines from the top and bottom of the Type-C receptacle to the D± lines of the
Thunderbolt Controller and Billboard controller. CCG5 also handles the routing of SBU1 and SBU2 lines from the Type-C receptacle
to the Thunderbolt controller for the link management. As mentioned in Features, CCG5 offers ESD Protection on D± and SBU lines
as well as VBUS Short protection on SBU and CC lines.
Figure 10. CCG5 in a Dual port Thunderbolt Device/Dock Upstream Port Application using CYPD5235-96BXZI
VBUS_OUT_P2
VBUS_OUT_P1
0.01
0.01
Power
Power
Subsystem
Subsystem
Provider
Path
Provider
Path
I2C
EN
INT
EN
INT
K5
G10
F10
K8
B7
B6
L2
CSP_P2
L7
B3
CSN_P1
J1
I2C_SDA_SCB4/
OVP_TRIP_P1/
CSN_P2
P1.5 P1.4
SDA_4/P3.2 SCL_4/P2.3
P3.1
CSP_P1
P2.4
X
X
B4
B5
VBUS_P_CTRL_P2
VBUS_C_CTRL_P2
VBUS_P_CTRL_P1
VBUS_C_CTRL_P1
K3
K4
X
X
L3
VBUS_P2
D1
VBUS
VBUS_P1
VBUS
10µF
50V
VDDD
1K
10µF
50V
C2
SWD_CLK/I2C_CFG_EC/P1.0
1K
A3, A4
A1, A2
SBU1/2
D+/-_T
D+/-_B
SBU1/2_P1
F1, E1
G1, H1
SBU1/2
D+/-_T
D+/-_B
SBU1/2_P2
DP/M_TOP_P1
DP/M_TOP_P2
B1, C1
H2, K2
DP/M_BOT_P1
CC1/2_P1
K1, L1
DP/M_BOT_P2
CC1/2_P2
CC1/2
K10, K9
CC1/2
390pF
390pF
L10
X
SCL_3/VSEL_1_P1/P3.7
VDDD
Type-C
Receptacle
2
Type-C
Receptacle
1
D10
VDDD
CCG5
(CYPD5235-96BZXI)
96-BGA
1µF
0.1µF
C10
A5
VDDIO
3.3V
J10
X
VSYS
VCCD
SDA_3/VSEL_2_P1/P3.6
0.1µF
10V
1µF
10V
B10
0.1µF
B8
X
VCON_OCP_TRIP_P1/P3.5
5V (from System)
J2
L9
GND
V5V_P1
V5V_P2
GND
3.3V
H6
B9
XRES
0.1µF
RESET
I2C_SDA/SCL/INT
G8
X
NC1
NC2
NC3
NC4
VCON_OCP_TRIP_P2/P3.3
I2C_INT_EC/P2.5
L5
L6
H4
X
I2C_SCL_SCB1_EC/P5.1
I2C_SDA_SCB1_EC/P5.0
USB Billboard
(CY7C65215)
H5
X
K6
H8
X
H11
A8
D+
UART_TX_P2/P0.1
UART_TX_P1/P4.0
UART_RX_P2/P0.2
UART_RX_P1/P4.1
USB FullSpeed
J11
A9
D-
SPI_Master
D5, D6, D7, D8, E4, E5,
E6, E7, E8, F4, F5, F6, F7,
F8, G4, G5, G6, G7, H7
GND
L4, L8, G2, H10
E2
4
SPI_Master
I2C_SCL_SCB2_TBT/P1.2
I2C_SDA_SCB2_TBT/P1.1
I2C_INT_TBT_P1/P1.3
3.3V
D2
F2
10K
B2
G2
I2C_INT_TBT_P2/P2.1
AUX_P/N_P2
SWD_IO/TBT_RST/P1.6
AUX_P/N_P1
B11, C11
E11, D11
0.1µF
0.1µF
K11, L11
A10, A11
LSTX/RX_P2
4
LSTX/RX_P1
8
8
Data Lines
Data Lines
SPI
Slave
Flash
3.3V
3.3V
10K
DNP
10K
DNP
K7
E10
HPD_P1/P3.0
HPD_P2/P3.4
D+_SYS_P2
F11
D-_SYS_P2 D+_SYS_P1
D-_SYS_P1
A7
100K
100K
G11
A6
USB2_P
USB2_N
USB2_P
USB2_N
DPSRC_HPD
DPSRC_HPD
LSTX/RX
Port B
LSTX/RX
Port A
DPSRC_AUX_P/N
DPSRC_AUX_P/N
I2C_SCL
I2C_SDA
Thunderbolt Controller
4
RESET_N
I2C_INT_P1
I2C_INT_P2
SPI_Master
Note:
Follow recommendations from manufacturer
for Thunderbolt Controller connections for
device/dock schematics
Document Number: 002-17682 Rev. *M
Page 19 of 43
EZ-PD™ CCG5
Figure 11 illustrates the Dual Type-C Port dock downstream application diagram using a CCG5 device. The CCG5 negotiates power
contract with the connected device on the downstream Type-C port and controls the power system. It also controls the data mux via
I2C based on the alternate mode negotiation to source USB SuperSpeed and/or DisplayPort on the downstream Type-C port. As
mentioned above, the CCG5 device offers ESD Protection on D± and SBU lines as well as VBUS Short protection on SBU and CC
lines.
Figure 11. CCG5 in a Dual port Dock Downstream Port Application using CYPD5236-96BXZI
VBUS_OUT_P2
VBUS_OUT_P1
5V
5V
BSC030P03NS3
BSC030P03NS3
BSC030P03NS3
BSC030P03NS3
8
7
6
5
8
7
6
5
0.01
0.01
8
7
6
5
8
7
6
5
3
2
1
3
2
1
3
2
1
3
2
1
10µF
50V
Provider
Path
Provider
Path
10µF
50V
1µF
35V
1µF
35V
Power
Subsystem
49.9K
1%
49.9K
1%
4
4
4
4
K8
L2
B3
CSN_P1
J1
CSN_P2
CSP_P2
CSP_P1
K3
B4
VBUS_P_CTRL_P1
VBUS_C_CTRL_P1
VBUS_P2
VBUS_P_CTRL_P2
K4
X
X
B5
VBUS_C_CTRL_P2
L3
D1
VBUS
VBUS_P1
VBUS
10µF
50V
VDDD
10µF
50V
1K
C2
SWD_CLK/I2C_CFG_EC/P1.0
1K
A3, A4
A1, A2
SBU1/2
D+/-_T
D+/-_B
SBU1/2_P1
F1, E1
G1, H1
SBU1/2
D+/-_T
SBU1/2_P2
DP/M_TOP_P1
DP/M_TOP_P2
B1, C1
DP/M_BOT_P1
CC1/2_P1
K1, L1
D+/-_B
CC1/2
DP/M_BOT_P2
CC1/2_P2
H2, K2
L8
CC1/2
K10, K9
OVP_TRIP_P2/P2.2
X
390pF
390pF
L10
SCL_3/VSEL_1_P1/P3.7
X
DS
DS
VDDD
Type-C
Receptacle
2
J10
Type-C
Receptacle
1
SDA_3/VSEL_2_P1/P3.6
UV_OCP_TRIP_P2/P1.5
VCON_OCP_TRIP_P1/P3.5
X
D10
VDDD
VDDIO
B7
B8
CCG5
(CYPD5236-96BZXI)
96-BGA
X
X
1µF
0.1µF
C10
A5
3.3V
VSYS
VCCD
0.1µF
10V
1µF
10V
B6
L4
UV_OCP_TRIP_P1/P1.4
VSEL_1_P2/P0.0
X
X
B10
0.1µF
5V (from System)
H10
K5
VSEL_2_P2/P2.0
X
X
J2
GND
V5V_P1
V5V_P2
I2C_SDA_SCB4/
OVP_TRIP_P1/P2.4
L9
GND
H6
G10
F10
3.3V
XRES
SDA_4/P3.2
SCL_4/P2.3
To Port 1& 2
Data Mux
0.1µF
RESET
B9
L5
L6
X
X
X
X
G8
H4
NC1
NC2
NC3
NC4
VCON_OCP_TRIP_P2/P3.3
I2C_INT_EC/P2.5
I2C_SDA/SCL/INT
MCU
Cypress FM0
I2C_SCL_SCB1_EC/P5.1
I2C_SDA_SCB1_EC/P5.0
H5
H8
K6
H11
X
UART_TX_P2/P0.1
UART_TX_P1/P4.0
A8
X
J11
X
A9
USB2.0 FS
UART_RX_P2/P0.2
UART_RX_P1/P4.1
D5, D6, D7, D8, E4, E5,
E6, E7, E8, F4, F5, F6, F7,
X
GND
F8, G4, G5, G6, G7, H7
E2
X
I2C_SCL_SCB2_TBT/P1.2
I2C_SDA_SCB2_TBT/P1.1
I2C_INT_TBT_P1/P1.3
3.3V
D2
X
F2
X
10K
B2
G2
X
I2C_INT_TBT_P2/P2.1
AUX_P/N_P2
SWD_IO/TBT_RST/P1.6
AUX_P/N_P1
E11, D11
B11, C11
0.1µF
0.1µF
A10, A11
X
K11, L11
X
LSTX/RX_P2
LSTX/RX_P1
8
8
Data Lines
Data Lines
3.3V
3.3V
10K
10K
DNP
To P2
DisplayPort
Source
To P1
DisplayPort
Source
DNP
K7
E10
HPD_P1/P3.0
HPD_P2/P3.4
D+/-_SYS_P2
F11 G11
D+/-_SYS_P1
A6 A7
100K
100K
USB DS 1_HS
USB DS 2_HS
AUX_P/N
AUX_P/N
I2C from
CCG5
Port 1
Data Mux
Port 2
Data Mux
I2C from
CCG5
Full Speed
USB 3.1
USB3.1 HUB
USB DS 3_HS
USB DS 1_SS
USB 3.1
USB DS 2_SS
USB US
From P1
DisplayPort
Source
From P2
DisplayPort
Source
From Upstream Host
Document Number: 002-17682 Rev. *M
Page 20 of 43
EZ-PD™ CCG5
Electrical Specifications
Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings[8]
Parameter
VSYS_MAX
Description
Min
–
Typ
–
Max
6
Unit
V
Details/Conditions
Digital supply relative to VSS
V5V_P1_MAX
V5V_P2_MAX
VBUS_P1_MAX
VBUS_P2_MAX
VDDIO_MAX
Max supply voltage relative to VSS
Max supply voltage relative to VSS
Max VBUS voltage relative to Vss
Max VBUS voltage relative to Vss
Max supply voltage relative to VSS
–
–
6
V
–
–
6
V
–
–
24
24
VDDD
V
–
–
V
Absolute max
–
–
V
Inputs to GPIO, DP/DM mux (UART,
SYS,DP/DM_top/botpins),SBUmux
(AUX, LS, SBU1/2 pins)
VGPIO_ABS
–0.5
–
VDDIO + 0.5
V
IGPIO_ABS
Maximum current per GPIO
–25
–
–
25
mA
mA
GPIO injection current, Max for VIH
VDDD, and Min for VIL < VSS
>
Absolute max, current
injected per pin
IGPIO_INJECTION
–0.5
0.5
Electrostatic discharge human body
model
Applicable for all pins except
SBU pins
ESD_HBM
2200
1100
–
–
–
–
V
V
Electrostatic discharge human body
model for SBU1, SBU2 pins
ESD_HBM_SBU[9]
Only applicable to SBU pins
Electrostatic discharge charged
device model
ESD_CDM
LU
500
–
–
–
V
–
–
Pin current for latch up
–200
200
mA
Contact Discharge for
CC1_P1/P2, CC2_P1/P2,
VBUS_P1/P2, SBU1_P1/P2,
SBU2_P1/P2,
Electrostatic discharge
ESD_IEC_CON
ESD_IEC_AIR
8000
–
–
–
–
V
V
IEC61000-4-2, contact discharge
DPLUS_TOP/BOT_P1/P2,
DMINUX_TOP/BOT_P1/P2
Air Discharge for
CC1_P1/P2, CC2_P1/P2,
VBUS_P1/P2, SBU1_P1/P2,
SBU2_P1/P2,
Electrostatic discharge
IEC61000-4-2, air discharge
15000
DPLUS_TOP/BOT_P1/P2,
DMINUX_TOP/BOT_P1/P2
VCC_PIN_ABS
VSBU_PIN_ABS
Max voltage on CC1 and CC2 pins
Max voltage on SBU1 and SBU2 pins
–
–
–
–
24
24
V
V
Absolute max
Absolute maximum for OVT
pins K6 and L6 of BGA, pins
16 and 17 of QFN
VGPIO_OVT_ABS OVT GPIO voltage
–0.5
–
6
V
Notes
8. Usage above the absolute maximum conditions listed in Table 8 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
9. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
Document Number: 002-17682 Rev. *M
Page 21 of 43
EZ-PD™ CCG5
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V
except where noted.
Table 9. DC Specifications
Spec ID
Parameter
Description
Min
2.75
3.15
4
Typ Max Unit
Details/Conditions
SID.PWR#23
VSYS
Power supply input voltage
Power supply input voltage
VBUS_P1 and VBUS_P2 valid range
–
–
–
5.5
5.5
V
V
V
UFP applications
SID.PWR#23_A VSYS
DFP/DRP applications
SID.PWR#22
VBUS
21.5
–
–
RegulatedoutputvoltagewhenVSYS is
powered
SID.PWR#1
VDDD
VSYS – 0.05
3.15
–
–
–
VSYS
3.65
5.5
V
V
V
LDO regulated output voltage when
VBUS powered
–
SID.PWR#1_A
SID.PWR#26
VDDD
V5V_P1 and
V5V_P2
Power supply Input voltage
4.85
–
At system-level short the
SID.PWR#13
SID.PWR#24
SID.PWR#15
VDDIO
VCCD
CEFC
GPIO power supply
VDDD
–
–
VDDD
–
V
V
VDDIO to VDDD
Output voltage (for Core Logic)
1.8
–
External regulator voltage bypass on
VCCD
80
100 120
nF
Power supply decoupling capacitor on
VDDD
SID.PWR#16
SID.PWR#27
SID.PWR#5
CEXC
–
–
–
1
0.1
1
–
–
2
µF X5R ceramic or better
µF
Power supply decoupling capacitor on
V5V_P1 and V5V_P2
CEXV
External load current on VDDD either in
Active or Deep Sleep mode
IVDDD_EXT
mA
–
Max LDO current for
powering VDDD and
VDDIO. For powering
SID.PWR#5A
ILDO_MAX
LDO max output current
–
–
30
mA external circuitry
connected to the chip,
max current is defined by
IVDDD_EXT
.
Active Mode, VSYS = 2.75 to 5.5 V. Typical values measured at VSYS = 3.3 V
TA = 25 °C, CC I/O IN
Transmit or Receive, no
mA I/Osourcingcurrent,CPU
at 24 MHz, two PD ports
active
SID.PWR#4
IDD12
Supply current
–
10
–
Deep Sleep Mode, VSYS = 2.75 to 3.6 V
SID34
IDD29
–
–
150
160
–
–
µA VSYS = 3.3 V, TA = 25 °C,
VSYS = 2.75 to 3.6 V, I2C, wakeup and
WDT on.
VSYS = 3.3 V, TA = 25 °C
SID34A
IDD29A
µA
for two PD ports
Power source = VSYS
,
Type-C not attached, CC
enabled for wakeup, Rp
and Rd connected at
70-ms intervals by CPU.
Rp,Rdconnectionshould
be enabled for both PD
ports.
VSYS = 3.3 V, CC wakeup on, Type-C
not connected.
SID_DS1
IDD_DS1
–
150
–
µA
Document Number: 002-17682 Rev. *M
Page 22 of 43
EZ-PD™ CCG5
Table 9. DC Specifications (continued)
Spec ID
Parameter
Description
Min
Typ Max Unit
Details/Conditions
IDD_DS1 + DP/DM,
µA SBU, CC ON,
VSYS = 3.3 V, CC wakeup on, DP/DM,
SBU ON with ADC/CSA/UVOV On
SID_DS3
IDD_DS2
–
500
–
ADC/CSA/UVOV ON
XRES Current
Power Source = VSYS
µA 3.3 V, Type-C not
attached, TA = 25 °C
=
SID307
IDD_XR
Supply current while XRES asserted
–
130
–
Table 10. AC Specifications (Guaranteed by Characterization)
Spec ID
SID.CLK#4
SID.PWR#21
Parameter
FCPU
TDEEPSLEEP Wakeup from Deep Sleep mode
Description
Min
Typ
–
Max Unit
Details/Conditions
MHz All VDDD
µs
CPU input frequency
–
–
5
48
–
35
–
SYS.XRES#5 TXRES
External reset pulse width
–
µs Guaranteed by
characterization.
ms
Power-up to “Ready to accept I2C/CC
command”
SYS.FES#1
T_PWR_RDY
–
5
25
I/O
Table 11. I/O DC Specifications
Spec ID
Parameter
VIH_CMOS
Description
Min
0.7 × VDDIO
–
Typ
Max
Unit
Details/Conditions
Input voltage HIGH
threshold
SID.GIO#37
–
–
V
CMOS input
SID.GIO#38
SID.GIO#39
SID.GIO#40
SID.GIO#41
SID.GIO#42
SID.GIO#33
SID.GIO#34
SID.GIO#35
VIL_CMOS
Input voltage LOW threshold
–
–
–
–
–
–
–
–
–
–
0.3 × VDDIO
V
V
V
V
V
V
V
V
V
V
CMOS input
VIH_VDDIO2.7- LVTTL input, VDDIO < 2.7 V 0.7 × VDDIO
–
–
VIL_VDDIO2.7-
LVTTL input, VDDIO < 2.7 V
–
2.0
–
0.3 × VDDIO
–
VIH_VDDIO2.7+ LVTTL input, VDDIO 2.7 V
VIL_VDDIO2.7+ LVTTL input, VDDIO 2.7 V
–
0.8
–
–
–
VOH
VOH
VOL
Output voltage HIGH level VDDIO – 0.6
Output voltage HIGH level VDDIO – 0.5
IOH = –4 mA at 3 V VDDIO
IOH = –1mA at 1.8 V VDDIO
IOL = 4 mA at 1.8 V VDDIO
IOL = 3 mA, VDDIO > 2 V
IOL = 6 mA, VDDIO > 1.71 V
–
Output voltage LOW level
Output low voltage
–
–
–
0.6
0.4
0.6 [10]
SID.GIO#35A VOL_I2C_2
SID.GIO#35B VOL_I2C_3
Output low voltage
I
OL = 20 mA, VDDIO > 3 V, appli-
SID.GIO#35C VOL1_20mA
Output low voltage
–
–
–
–
0.4
0.6
V
V
cable for overvoltage-tolerant
pins only.
IOL = 10 mA (IOL_LED) at 3 V
VDDIO
SID.GIO#36
VOL
Output voltage LOW level
SID.GIO#5
SID.GIO#6
RPU
RPD
Pull-up resistor value
3.5
3.5
5.6
5.6
8.5
8.5
k +25 °C TA, All VDDIO
k +25 °C TA, All VDDIO
Pull-down resistor value
Input leakage current
(absolute value)
SID.GIO#16
IIL
–
–
–
3
2
7
nA +25 °C TA, 3-V VDDIO
SID.GIO#17
CPIN
Max pin capacitance
pF –
Note
10. In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL. Parts not meeting this specification can still function, but not at 400 kHz and 400 pF.
Document Number: 002-17682 Rev. *M
Page 23 of 43
EZ-PD™ CCG5
Table 11. I/O DC Specifications (continued)
Spec ID
Parameter
VHYSTTL
VHYSCMOS
Description
Min
Typ
Max
Unit
Details/Conditions
VDDIO > 2.7 V. Guaranteed by
characterization.
SID.GIO#43
Input hysteresis, LVTTL
15
40
–
mV
0.05 ×
VDDIO
SID.GIO#44
Input hysteresis CMOS
Input hysteresis CMOS
–
–
–
–
mV VDDIO < 4.5 V
mV VDDIO > 4.5 V
SID.GIO#44A VHYSCMOS55
200
Note
10. In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL. Parts not meeting this specification can still function, but not at 400 kHz and 400 pF.
Table 12. I/O AC Specifications (Guaranteed by Characterization)
Spec ID
SID70
SID71
Parameter
TRISEF
TFALLF
Description
Min
2
Typ
–
Max
12
Unit
Details/Conditions
Rise time in Fast Strong mode
Fall time in Fast Strong mode
Rise time in Slow Strong mode
Fall time in Slow Strong mode
ns 3.3-V VDDIO, Cload = 25 pF
ns 3.3-V VDDIO, Cload = 25 pF
ns 3.3-V VDDIO, Cload = 25 pF
ns 3.3-V VDDIO, Cload = 25 pF
2
–
12
SID.GIO#46 TRISES
SID.GIO#47 TFALLS
10
10
–
60
–
60
GPIO FOUT; 3.3 V VDDIO 5.5 V.
90/10%, 25-pF load
MHz
SID.GIO#48 FGPIO_OUT1
SID.GIO#49 FGPIO_OUT2
SID.GIO#50 FGPIO_OUT3
SID.GIO#51 FGPIO_OUT4
SID.GIO#52 FGPIO_IN
–
–
–
–
–
–
–
–
–
–
16
16
7
Fast Strong mode.
GPIO FOUT; 1.7 V VDDIO 3.3 V.
Fast Strong mode.
90/10%, 25-pF load
MHz
GPIO FOUT; 3.3 V VDDIO 5.5 V.
Slow Strong mode.
90/10%, 25-pF load
MHz
GPIO FOUT; 1.7 V VDDIO 3.3 V.
Slow Strong mode.
90/10%, 25-pF load
MHz
3.5
16
GPIO input operating frequency;
1.7 V VDDIO 5.5 V.
90/10% VIO
MHz
XRES
Table 13. XRES DC Specifications
Spec ID Parameter Description
Input voltage HIGH threshold 0.7 × VDDIO
Min
Typ
Max
Unit
V
Details/Conditions
CMOS input
SID.XRES#1 VIH
SID.XRES#2 VIL
SID.XRES#3 CIN
–
–
–
–
Input voltage LOW threshold
Input capacitance
–
–
0.3 × VDDIO
7
V
CMOS input
–
pF
Guaranteed by
characterization
SID.XRES#4 VHYSXRES Input voltage hysteresis
–
0.05 × VDDIO
–
mV
Document Number: 002-17682 Rev. *M
Page 24 of 43
EZ-PD™ CCG5
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
PWM for GPIO Pins
Table 14. PWM AC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
–
Typ
–
Max
Fc
–
Unit
MHz
ns
Details/Conditions
Fc max = CLK_SYS.
Maximum = 48 MHz.
SID.TCPWM.3 TCPWMFREQ Operating frequency
SID.TCPWM.4 TPWMENEXT Input trigger pulse width
2/Fc
–
For all trigger events
Minimum possible width of Overflow,
Underflow, and CC (Counter equals
Compare value) outputs
SID.TCPWM.5 TPWMEXT
Output trigger pulse width
2/Fc
–
–
ns
Minimum time between successive
counts
SID.TCPWM.5A TCRES
SID.TCPWM.5B PWMRES
SID.TCPWM.5C QRES
Resolution of counter
PWM resolution
1/Fc
1/Fc
1/Fc
–
–
–
–
–
–
ns
ns
ns
Minimum pulse width of PWM output
Minimum pulse width between
quadrature-phase inputs
Quadrature inputs resolution
I2C
Table 15. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
Description
Min
Typ
Max
Unit
Mbps
Details/Conditions
FI2C1
Bit rate
–
–
1
–
UART
Table 16. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID
SID162
Parameter
Description
Description
Min
Typ
Max
Unit
Details/Conditions
FUART
Bit rate
–
–
1
Mbps
–
SPI
Table 17. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID
SID166
Parameter
FSPI
Min
Typ
Max
Unit
Details/Conditions
SPI operating frequency (Master; 6X
oversampling)
–
–
8
MHz
–
Table 18. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
SID167
Parameter
TDMO
Description
Min
Typ
Max
Unit
Details/Conditions
MOSI valid after SClock driving edge
–
–
15
ns
–
MISO valid before SClock capturing
edge
Full clock, late MISO
sampling
SID168
SID169
TDSI
20
0
–
–
–
–
ns
ns
Referred to slave capturing
edge
THMO
Previous MOSI data hold time
Document Number: 002-17682 Rev. *M
Page 25 of 43
EZ-PD™ CCG5
Table 19. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
SID170
Parameter
TDMI
Description
Min Typ
Max
Unit
Details/Conditions
MOSI Valid before Sclock capturing
edge
40
–
–
–
–
ns
–
SID171
TDSO
MISO Valid after Sclock driving edge
48 + 3 × TSCB ns TSCB = TCPU
MISO Valid after Sclock driving edge
in Ext Clk mode
SID171A
TDSO_EXT
–
–
48
ns
–
SID172
THSO
Previous MISO data hold time
0
–
–
–
–
ns
ns
–
–
SID172A
TSSELSCK
SSEL Valid to first SCK Valid edge
100
Memory
Table 20. Flash AC Specifications
Spec ID Parameter
Description
Min Typ Max
Unit
Details/Conditions
Row (Block) write time (erase and
program)
SID.MEM#4 TROW_WRITE
SID.MEM#3 TROW_ERASE
–
–
20
ms
–
–
Row erase time
–
–
–
–
–
–
–
13
7
ms
ms
SID.MEM#8 TROWPROGRAM Row program time after erase
25 °C to 55 °C, All VDDD
Guaranteed by design
Guaranteed by design
–
SID178
SID180
TBULKERASE
TDEVPROG
Bulk erase time (128 KB)
Total device program time
Flash endurance
–
35
25
–
ms
–
s
SID.MEM#6 FEND
100k
cycles
Flash retention, TA ≤ 55 °C,
SID182
FRET1
FRET2
20
10
–
–
–
–
years
years
–
–
100K P/E cycles
Flash retention, TA ≤ 85 °C,
10K P/E cycles
SID182A
System Resources
Power-on-Reset (POR) with Brownout
Table 21. Imprecise Power On Reset (PRES)
Spec ID
SID185
SID186
Parameter
VRISEIPOR
VFALLIPOR
Description
Rising trip voltage
Falling trip voltage
Min
0.80
0.70
Typ
Max
1.50
1.4
Unit
V
Details/Conditions
–
–
Guaranteed by
characterization
V
Table 22. Precise Power On Reset (POR) (Guaranteed by Characterization)
Spec ID
SID190
SID192
Parameter
VFALLPPOR
VFALLDPSLP
Description
Min
Typ
–
Max
1.62
1.5
Unit
V
Details/Conditions
BrownoutDetect(BOD)tripvoltagein
active/sleep modes
1.48
Guaranteed by
characterization
BOD trip voltage in Deep Sleep mode 1.1
–
V
Document Number: 002-17682 Rev. *M
Page 26 of 43
EZ-PD™ CCG5
SWD Interface
Table 23. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SWDCLK 1/3 CPU clock
SID.SWD#1 F_SWDCLK1
SID.SWD#2 F_SWDCLK2
3.3 V VDDIO 5.5 V
–
–
14
MHz
frequency
SWDCLK 1/3 CPU clock
frequency
2.7 V VDDIO 3.3 V
–
–
7
MHz
SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK
SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK
SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK
SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK
0.25 × T
–
–
–
–
–
–
ns
ns
0.25 × T
Guaranteed by
characterization
–
1
0.50 × T ns
ns
–
Internal Main Oscillator
Table 24. IMO AC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
Frequency variation at 48 MHz
(trimmed)
2.7 V ≤ VDDD < 5.5 V.
–25 °C ≤ TA ≤ 85 °C
SID.CLK#13 FIMOTOL
–
–
–
±2
%
%
Frequency variation at 48 MHz
(trimmed)
SID.CLK#13A FIMOTOLVCCD
–
±4
All conditions
SID226
TSTARTIMO
FIMO
IMO start-up time
IMO frequency
–
–
–
7
–
µs
–
–
SID.CLK#1
48
MHz
Internal Low-speed Oscillator
Table 25. ILO AC Specifications
Spec ID
SID234
Parameter
TSTARTILO1
TILODUTY
FILO
Description
ILO start-up time
ILO duty cycle
Min
–
Typ
–
Max
2
Unit
ms
Details/Conditions
Guaranteed by
characterization
SID238
40
20
50
40
60
80
%
SID.CLK#5
ILO frequency
kHz
–
Table 26. PD DC Specifications
Spec ID
Parameter
Description
Min
Typ
–
Max
Unit
Details/Conditions
SID.DC.cc_shvt.1 vSwing
SID.DC.cc_shvt.2 vSwing_low
SID.DC.cc_shvt.3 zDriver
SID.DC.cc_shvt.4 zBmcRx
Transmitter Output High Voltage
Transmitter Output Low Voltage
Transmitter output impedance
Receiver Input Impedance
1.05
1.2
0.075
75
V
–
–
–
–
V
33
10
–
Ω
–
MΩ Guaranteed by design
Source current for USB standard
advertisement
SID.DC.cc_shvt.5 Idac_std
SID.DC.cc_shvt.6 Idac_1p5a
SID.DC.cc_shvt.7 Idac_3a
64
–
–
–
96
µA
µA
µA
–
–
–
Source current for 1.5A at 5 V
advertisement
165.6
303.6
194.4
356.4
Source current for 3A at 5 V
advertisement
Pull down termination resistance
when acting as UFP (upstream
facing port)
SID.DC.cc_shvt.8 Rd
4.59
–
5.61
kΩ
–
Document Number: 002-17682 Rev. *M
Page 27 of 43
EZ-PD™ CCG5
Table 26. PD DC Specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
Pull down termination resistance
when acting as UFP, with dead
battery (upstream facing port)
SID.DC.cc_shvt.9 Rd_db
4.08
–
6.12
kΩ
–
CC impedance to ground when
disabled
SID.DC.cc_shvt.10 zOPEN
108
–
–
kΩ
V
–
–
CCvoltagesonDFPside-Standard
USB
SID.DC.cc_shvt.11 DFP_default_0p2
0.15
0.25
SID.DC.cc_shvt.12 DFP_1.5A_0p4
SID.DC.cc_shvt.13 DFP_3A_0p8
SID.DC.cc_shvt.14 DFP_3A_2p6
CC voltages on DFP side-1.5A
CC voltages on DFP side-3A
CC voltages on DFP side-3A
0.35
0.75
2.45
–
–
–
0.45
0.85
2.75
V
V
V
–
–
–
CCvoltagesonUFPside-Standard
USB
SID.DC.cc_shvt.15 UFP_default_0p66
0.61
–
0.7
V
–
SID.DC.cc_shvt.16 UFP_1.5A_1p23
SID.DC.cc_shvt.17 Vattach_ds
SID.DC.cc_shvt.18 Rattach_ds
CC voltages on UFP side-1.5A
Deep sleep attach threshold
Deep sleep pull-up resistor
1.16
0.3
10
–
–
–
1.31
0.6
50
V
%
–
–
–
kΩ
Voltage threshold for Fast Swap
Detect
SID.DC.cc_shvt.30 FS_0p53
0.49
–
0.58
V
–
Analog to Digital Converter
Table 27. ADC DC Specifications
Spec ID
SID.ADC.1
Parameter
Resolution
Description
ADC resolution
Min
–
Typ
8
Max
Unit Details/Conditions
Bits
–
–
SID.ADC.2
SID.ADC.3
SID.ADC.4
INL
Integral non-linearity
Differential non-linearity
Gain error
–1.5
–2.5
–1.5
–
1.5
2.5
1.5
LSB –
LSB –
LSB –
DNL
–
Gain Error
–
Reference voltage
generated from
VDDD
SID.ADC.5
SID.ADC.6
VREF_ADC1
VREF_ADC2
Reference voltage of ADC
Reference voltage of ADC
VDDDmin
–
VDDDmax
V
V
Reference voltage
generate from
bandgap
1.96
2.0
2.04
Document Number: 002-17682 Rev. *M
Page 28 of 43
EZ-PD™ CCG5
Charger Detect
Table 28. Charger Detect Specifications
Spec ID
Parameter
VDAT_REF
Description
Min Typ
Max
Unit Details/Conditions
Data detect voltage in charger detect
mode
DC.CHGDET.1
250
500
500
25
–
–
–
–
400
mV
mV
mV
µA
–
–
–
–
Dn voltage source in charger detect
mode
DC.CHGDET.2
DC.CHGDET.3
DC.CHGDET.4
VDM_SRC
VDP_SRC
IDM_SINK
700
700
175
Dp voltage source in charger detect
mode
Dn sink current in charger detect
mode
Dp sing current in charger detect
mode
DC.CHGDET.5
DC.CHGDET.6
IDP_SINK
IDP_SRC
25
7
–
–
–
–
–
175
13
µA
µA
kΩ
kΩ
kΩ
–
–
–
–
–
Data contact detect current source
Qualcomm pull-up termination on
Dp/Dn
DC.CHGDET.27 RDP_UP
DC.CHGDET.32 RDM_UP
DC.CHGDET.28 RDP_DWN
0.9
0.9
14.25
1.575
1.575
24.8
Dp/Dn pull-up resistance
Qualcomm pull-down termination on
Dp/Dn
DC.CHGDET.31 RDM_DWN
DC.CHGDET.29 RDAT_LKG
DC.CHGDET.34 VSETH
Dp/Dn pull-down resistance
Data line leakage on Dp/Dn
Logic Threshold
14.25
300
–
–
–
24.8
500
kΩ
kΩ
V
–
–
–
1.26
1.54
Table 29. VBUS Regulator AC Specifications
Spec ID Parameter
Description
Min Typ Max
Unit
Details/Conditions
Apply VBUS and
µs measure start time on
VDDD pin.
Total start up time for the regulator
supply outputs
SID.AC.20VREG.1 TSTART
–
–
120
Time from assertion of
an internal disable
µs signal to for load current
Regulator power down time from
vreg_en = 0 to regulator disable
SID.AC.20VREG.2 TSTOP
–
–
1
on VDDD to decrease
from 30 mA to 10 μA.
Table 30. VSYS Switch Specifications
Spec ID
Parameter
Description
Min Typ Max
1.5
Unit
Details/Conditions
Measured with a load
current of 5 mAto 10 mA
Resistance from supply input to
output supply VDDD
SID.DC.VDDDSW.1 Res_sw
–
–
Ω
on VDDD
.
Document Number: 002-17682 Rev. *M
Page 29 of 43
EZ-PD™ CCG5
Table 31. CSA DC Specifications
Spec ID Parameter
Description
Min
Typ Max Unit Details/Conditions
Cumulative output Error for Av = 15,
SID.DC.CSA.21 Out_E_Trim_15_DS after trim, using Deep sleep
(beta-multiplier) reference
–7
–
–
–
7
%
%
%
–
–
–
Cumulative output Error for Av = 15,
SID.DC.CSA.22 Out_E_Trim_15_BG
–4.5
4.5
after trim, using bandgap reference
Cumulative output Error for Av = 100,
SID.DC.CSA.23 Out_E_Trim_100_DS after trim, using Deep sleep (beta-multi- –24.5
plier) reference
24.5
Table 32. UV/OV Specifications
Spec ID
Parameter
Description
Min Typ Max Unit
Details/Conditions
Voltage threshold accuracy in active
mode using bandgap reference
SID.UVOV.1
VTHUVOV1
–
±3
–
%
–
Voltage threshold accuracy in Deep
Sleep mode using Deep Sleep
reference
SID.UVOV.2
VTHUVOV2
–
±5
–
–
%
–
–
SID.COMP_ACC
COMP_ACC Comparator input offset at 4s
–15
15
mV
Table 33. PFET Gate Driver DC Specifications
Spec ID
Parameter
Rpd
Description
Min Typ Max Unit
kΩ
Details/Conditions
Details/Conditions
SID.DC.PGDO.1
Resistance when “pull_dn” enabled
–
–
5
–
Table 34. PFET Gate Driver AC Specifications
Spec ID
Parameter
Description
Min Typ Max Unit
SID.AC.PGDO.2
Tr_discharge
Discharge Rate of output note
–
–
5
V/µs Guaranteed by design
SBU
Table 35. SBU Switch DC Specifications
Spec ID Parameter
Description
Min Typ Max Unit Details/Conditions
SID.DC.20sbu.1 Ron1
SID.DC.20sbu.2 Ron2
SID.DC.20sbu.4 Ileak1
On resistances for Aux switch at 3.3 V input
On resistances for Aux switch at 1 V input
Pin leakage current for SBU1, SBU2
–
–
4
3
–
7
5
Ω
Ω
–
–
–
–4.5
4.5 µA
Pin leakage current for LSTX, LSRX, AUX_P,
AUX_N
SID.DC.20sbu.5 Ileak2
–1
–
1
µA
–
SID.DC.20sbu.6 Rpu_aux_1
SID.DC.20sbu.7 Rpu_aux_2
SID.DC.20sbu.8 Rpd_aux_1
SID.DC.20sbu.9 Rpd_aux_2
SID.DC.20sbu.10 Rpd_aux_3
SID.DC.20sbu.11 Rpd_aux_4
Pull-up resistance on AUX_P/N
Pull-up resistance on AUX_P/N
Pull-down resistance on AUX_P/N
Pull-down resistance on AUX_P/N
Pull-down resistance on AUX_P/N
Pull-down resistance on AUX_P/N
80
0.8
80
–
–
–
–
–
–
320 KΩ –
1.4 MΩ –
120 KΩ –
1.2 MΩ –
611 KΩ –
6.11 MΩ –
0.3
250
0.3
Over-voltage protection detection threshold
above VDDIO
120
mV –
0
SID.DC.20sbu.16 OVP_threshold
200
–
Document Number: 002-17682 Rev. *M
Page 30 of 43
EZ-PD™ CCG5
Table 35. SBU Switch DC Specifications (continued)
Spec ID
Parameter
Description
Min Typ Max Unit Details/Conditions
On resistances of LSTX/LSRX to SBU1/2
switch at 3.3 V input
SID.DC.20sbu.17 lsx_ron_3p3
SID.DC.20sbu.18 lsx_ron_1
–
–
8.5 17
5.5 11
Ω
Ω
Ω
Ω
Ω
Ω
–
–
On resistances of LSTX/LSRX to SBU1/2
switch at 1 V input
Switch On flat resistances of AUX_P/N to
SBU1/2 switch (from 0 to 3.3 V)
Guaranteed by design
Guaranteed by design
SID.DC.20sbu.19 aux_ron_flat_fs
SID.DC.20sbu.20 aux_ron_flat_hs
SID.DC.20sbu.21 lsx_ron_flat_fs
SID.DC.20sbu.22 lsx_ron_flat_hs
–
–
–
–
–
2.5
0.5
5
Switch On flat resistances of AUX_P/N to
SBU1/2 switch (from 0 to 1 V)
–
Switch On flat resistances of LSTX/LSRX to
SBU1/2 switch (from 0 to 3.3 V)
–
Guaranteed by design
Guaranteed by design
Switch On flat resistances of LSTX/LSRX to
SBU1/2 switch (from 0 to 1 V)
–
0.5
Table 36. SBU Switch AC Specifications
Spec ID Parameter
Description
Min
Typ Max Unit
Details/Conditions
SID.AC.20sbu.1 Con
Switch ON capacitance
–
–
–
–
120
pF
–
Switch OFF capacitance - Connector
side
SID.AC.20sbu.2 Coff
–
80
pF
–
SID.AC.20sbu.3 Off_isolation
SID.AC.20sbu.4 TON
Switch isolation at F = 1 MHz
SBU Switch turn-on time
SBU Switch turn-off time
–50
–
dB
µs
–
–
–
200
400
60
SID.AC.20sbu.5 TOFF
–
–
–
µs Guaranteed by design
mV Guaranteed by design
SID.AC.20sbu.6 Off_isolation_tran Coupling on sbu1,2 terminated to
50 ohm, switch-OFF, Rail-to-rail
–60
toggling on LSTX/LSRX
SID.AC.20sbu.7 X_talk_AC
SID.AC.20sbu.8 X_talk_tran
Cross talk of Switch at F=1 MHz
SBU1/2 to SBU2/1
–50
–70
–
–
–
dB Guaranteed by design
mV Guaranteed by design
Check voltage coupling on SBU2(1)
when Data is transferred from LSTX
(RX) to SBU1 (2)
70
Table 37. DP/DM Switch DC Specifications
Spec ID
Parameter
Ron_HS
Description
Min
Typ
Max Unit Details/Conditions
DPDM On resistance for SYS lines (0
to 0.5 V) - HS mode
SID.DC.dpdm.1
–
–
8
–
–
DPDM On resistance for SYS lines (0
to 3.3 V) - FS mode
SID.DC.dpdm.2
SID.DC.dpdm.5
SID.DC.dpdm.6
Ron_FS
Con_FS
Con_HS
–
–
–
–
–
–
12
50
10
Switch On capacitance at FS at 6 MHz
pF Guaranteed by design
Switch on capacitance at HS at
240 MHz
pF
µA
–
pin leakage at DP/DM connector side
and host side
SID.DC.dpdm.9
Ileak_pin
–
–
–
–
–
–
1
–
DPDM On resistance for UART lines
(0 to 3.3 V)
SID.DC.dpdm.10 RON_UART
17
0.5
–
DPDM On Flat resistance in HS mode
(0 to 0.4 V)
SID.DC.dpdm.11 RON_FLAT_HS
Guaranteed by design
Document Number: 002-17682 Rev. *M
Page 31 of 43
EZ-PD™ CCG5
Table 37. DP/DM Switch DC Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max Unit Details/Conditions
DPDM On flat resistance in FS mode
(0 to 3.3 V)
SID.DC.dpdm.12 RON_FLAT_FS
–
–
4
4
Guaranteed by design
Guaranteed by design
RON_FLAT_UA DPDM UART On flat resistance (0 to
RT 3.3 V)
SID.DC.dpdm.13
–
–
Table 38. DP/DM Switch AC Specifications
Spec ID
Parameter
Description
DP/DM Switch turn-on time
DP/DM Switch turn-off time
Min
–
Typ
–
Max
200
0.4
Unit
Details/Conditions
SID.AC.dpdm.5 TON
SID.AC.dpdm.6 TOFF
µs
–
–
–
µs Guaranteed by design
Guaranteed by
µs
SID.AC.dpdm.7 TON_VPUMP
DP/DM charge pump startup time
–
–
200
characterization
SID.AC.dpdm.8 Off_isolation_HS Switch-off isolation for HS
SID.AC.dpdm.9 Off_isolation_FS Switch-off isolation for FS
–20
–50
–
–
–
–
–
–
db Guaranteed by design
db Guaranteed by design
SID.AC.dpdm.10 X_talk
Cross talk of Switch From FS to HS at –50
F = 12 MHz
db
Guaranteed by design
SID.AC.dpdm.11 uart_coupling
peak to peak coupling of UART signal
to DP lines. (UART swinging from 0 to
3.3 V)
–
–
20
mV
Guaranteed by design
Table 39. VCONN Switch DC Specifications
Spec ID
Parameter
Description
Min
Typ Max Unit Details/Conditions
SwitchONresistanceatV5V = 5 V
with 215-mA load current
SID.DC.20VCONN.1 Ron
–
1.4
–
2
–
–
Overcurrent detection range for
CC1/CC2
SID.DC.20VCONN.9 IOCP
440
600
mA
Overvoltage protection detection
threshold above VDDD or V5V
whichever is higher
SID.DC.20VCONN.10 OVP_threshold
200
–
1200 mV
–
Overvoltage protection detection
hysteresis
Guaranteed by
design
SID.DC.20VCONN.11 OVP_hysteresis
SID.DC.20VCONN.12 OCP_hysteresis
50
20
–
–
200
60
mV
mA
Overcurrent detection hysteresis
–
Overvoltage protection detection
threshold above V5V of CC1/2,
SID.DC.20vconn.14 OVP_threshold_on with CC1 or CC2 switch enabled.
Same threshold triggers reverse
200
–
700
mV
–
current protection circuit
Document Number: 002-17682 Rev. *M
Page 32 of 43
EZ-PD™ CCG5
Table 40. VCONN Switch AC Specifications
Spec ID
Parameter
Description
Min Typ Max
Unit
µs
Details/Conditions
–
SID.AC.20VCONN.1 TON
VCONN switch turn-on time
VCONN switch turn-off time
–
–
–
–
200
3
SID.AC.20VCONN.2 TOFF
µs
Guaranteed by design
Table 41. VBUS Discharge Specifications
Spec ID
Parameter
Ron1
Description
Min
1500
750
500
375
300
Typ
–
Max
3000
1500
1000
750
Unit
Details/Conditions
SID.VBUS.DISC.1
SID.VBUS.DISC.2
SID.VBUS.DISC.3
SID.VBUS.DISC.4
SID.VBUS.DISC.5
20-V NMOS ON resistance
20-V NMOS ON resistance
20-V NMOS ON resistance
20-V NMOS ON resistance
20-V NMOS ON resistance
–
–
–
–
–
Ron2
Ron3
Ron4
Ron5
–
–
–
–
600
Document Number: 002-17682 Rev. *M
Page 33 of 43
EZ-PD™ CCG5
Ordering Information
Table 42 lists the EZ-PD CCG5 part numbers and features.
Table 42. EZ-PD CCG5 Ordering Information
Dead Battery
Termination
Termination
Resistor
Part Number
Application
Type-C Ports
Role
DRP
DRP
Package
40-pin QFN
96-ball BGA
CYPD5125-40LQXIT[14] Notebooks, Desktops
1
2
Yes
Yes
RP[11], RD[12], RD-DB
[13]
CYPD5225-96BZXI
Notebooks, Desktops
CYPD5225-96BZXIT
RP[11], RD[12], RD-DB
[13]
CYPD5235-96BZXI
Dock, Upstream port
CYPD5235-96BZXIT
[12]
2
2
No
No
RP[11], RD
DRP
DRP
96-ball BGA
96-ball BGA
CYPD5236-96BZXI
Dock, Downstream port
CYPD5236-96BZXIT
RP[11], RD
[12]
Ordering Code Definitions
CY PD XX
XX XX - XX XX
X
I
T
T = Tape and reel
Temperature Grade : I = Industrial
X = Pb-free
Package Type: XX = FN, LQ, BZ; LQ = QFN; BZ = BGA
Number of pins in the package : XX = 40 or 96
Device Role: Unique combination of role and termination
2X = Dead battery termination , 3X = No Dead battery termination
X5 = Notebooks, desktops, dock applications ,
X6 = Docks for downstream port
Number of Type -C Ports: 1 = 1 Port, 2 = 2 Ports
Product Type: 5 = Fifth-generation product family , CCG5
Marketing Code : PD = Power Delivery product family
Company ID: CY = Cypress
Notes
11. Termination resistor denoting a downstream facing port.
12. Termination resistor denoting an accessory or upstream facing port.
13. Termination resistor denoting dead-battery termination.
14. NRND (Not Recommended for New Designs). Refer to the CCG5C Datasheet for pin to pin compatible replacement part.
Document Number: 002-17682 Rev. *M
Page 34 of 43
EZ-PD™ CCG5
Packaging
Table 43. Package Characteristics
Parameter
TA
Description
Conditions
Min
–40
–40
–
Typ
25
25
–
Max
85
Unit
°C
Operating ambient temperature
Operating junction temperature
Package JA (96-ball BGA)
Package JC (96-ball BGA)
Package JA (40-pin QFN)
Package JC (40-pin QFN)
Industrial
TJ
Industrial
100
56
°C
TJA
TJC
TJA
TJC
–
–
–
–
°C/W
°C/W
°C/W
°C/W
–
–
18.5
19.3
13.6
–
–
–
–
Table 44. Solder Reflow Peak Temperature
Package
Maximum Time within 5 °C of Peak
Temperature
Maximum Peak Temperature
96-ball BGA
40-pin QFN
260 °C
260 °C
30 seconds
30 seconds
Table 45. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
96-ball BGA
MSL
MSL 3
MSL 3
40-pin QFN
Figure 12. 40-Pin QFN (6 × 6 × 0.6 mm), LR40A/LQ40A 4.6 × 4.6 E-PAD (Sawn) Package Outline, 001-80659
001-80659 *A
Document Number: 002-17682 Rev. *M
Page 35 of 43
EZ-PD™ CCG5
Figure 13. 96-Ball BGA (6 × 6 × 1.0 mm), Package Outline, 002-10631
E1
2X
0.10 C
(datum B)
A1 CORNER
E
B
A
D
1110 9 8 7
6 5 4 3 2 1
A
7
B
C
D
E
A1 CORNER
6
SD
D1
F
G
H
(datum A)
J
K
L
eD
6
2X
0.10 C
eE
SE
TOP VIEW
BOTTOM VIEW
DETAIL A
0.10 C
A
A1
0.08 C
C
96XØb
5
SIDE VIEW
Ø0.15 M C A B
Ø0.05 M C
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
NOM.
SYMBOL
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
MIN.
MAX.
1.00
-
A
A1
D
-
-
-
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
0.16
6.00 BSC
E
6.00 BSC
5.00 BSC
5.00 BSC
11
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW
11
96
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW
"SD" OR "SE" = 0.
0.30
b
0.25
0.35
eD
eE
SD
SE
0.50 BSC
0.50 BSC
0.00
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
0.00
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
9. JEDEC SPECIFICATION NO. REF. : MO-225.
002-10631 *A
Document Number: 002-17682 Rev. *M
Page 36 of 43
EZ-PD™ CCG5
Table 46. Acronyms Used in this Document (continued)
Acronyms
Acronym
opamp
OCP
OVP
PCB
Description
operational amplifier
Table 46. Acronyms Used in this Document
Acronym
ADC
Description
analog-to-digital converter
overcurrent protection
overvoltage protection
printed circuit board
power delivery
API
Arm®
application programming interface
advanced RISC machine, a CPU architecture
configuration channel
PD
CC
PGA
PHY
programmable gain amplifier
physical layer
BOD
CPU
Brown out Detect
central processing unit
POR
PRES
PSoC®
PWM
RAM
RISC
RMS
RTC
power-on reset
cyclic redundancy check, an error-checking
protocol
CRC
precise power-on reset
Programmable System-on-Chip™
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
CS
current sense
DFP
downstream facing port
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
DIO
DRP
dual role port
electrically erasable programmable read-only
memory
EEPROM
real-time clock
RX
receive
a USB cable that includes an IC that reports cable
characteristics (e.g., current rating) to the Type-C
ports
EMCA
SAR
successive approximation register
I2C serial clock
SCL
EMI
ESD
FPB
FS
electromagnetic interference
electrostatic discharge
flash patch and breakpoint
full-speed
SDA
I2C serial data
S/H
sample and hold
Serial Peripheral Interface, a communications
protocol
SPI
GPIO
IC
general-purpose input/output
integrated circuit
SRAM
SWD
TX
static random access memory
serial wire debug, a test protocol
transmit
IDE
integrated development environment
I2C, or IIC Inter-Integrated Circuit, a communications protocol
a new standard with a slimmer USB connector and
a reversible cable, capable of sourcing up to 100 W
of power
Type-C
ILO
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
input/output, see also GPIO
low-voltage detect
IMO
I/O
Universal Asynchronous Transmitter Receiver, a
communications protocol
UART
USB
LVD
LVTTL
MCU
NC
Universal Serial Bus
low-voltage transistor-transistor logic
microcontroller unit
USB input/output, CCG5 pins used to connect to a
USB port
USBIO
XRES
external reset I/O pin
no connect
NMI
NVIC
nonmaskable interrupt
nested vectored interrupt controller
Document Number: 002-17682 Rev. *M
Page 37 of 43
EZ-PD™ CCG5
Document Conventions
Table 47. Units of Measure (continued)
Symbol Unit of Measure
µW
Units of Measure
Table 47. Units of Measure
microwatt
milliampere
millisecond
millivolt
Symbol
°C
Unit of Measure
mA
ms
mV
nA
ns
degrees Celsius
hertz
Hz
KB
1024 bytes
nanoampere
nanosecond
ohm
kHz
k
kilohertz
kilo ohm
Mbps
MHz
M
Msps
µA
megabits per second
megahertz
pF
ppm
ps
picofarad
parts per million
picosecond
second
mega-ohm
megasamples per second
microampere
microfarad
s
sps
V
samples per second
volt
µF
µs
microsecond
microvolt
µV
Document Number: 002-17682 Rev. *M
Page 38 of 43
EZ-PD™ CCG5
References and Links To Applications Collaterals
Knowledge Base Articles
■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and
■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
CCG5 - KBA210740
■ AN210403 - Hardware Design Guidelines for Dual Role Port
■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™
Applications Using EZ-PD™ USB Type-C Controllers
CCG5 Using PSoC® Programmer and MiniProg3 - KBA96477
■ AN210771 - Getting Started with EZ-PD™ CCG4
■ CCGX Frequently Asked Questions (FAQs) - KBA97244
■ Handling Precautions for CY4501 CCG1 DVK - KBA210560
■ Cypress EZ-PD™ CCGx Hardware - KBA204102
■ Difference between USB Type-C and USB-PD - KBA204033
■ CCGx Programming Methods - KBA97271
Reference Designs
■ EZ-PD™ CCG2 Electronically Marked Cable Assembly
(EMCA) Paddle Card Reference Design
■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution
■ CCG1 USB Type-C to DisplayPort Cable Solution
■ Getting started with Cypress USB Type-C Products -
KBA04071
■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution
■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution
■ Type-C to DisplayPort Cable Electrical Requirements
■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle
Card Reference Design
■ Dead Battery Charging Implementation in USB Type-C
Solutions - KBA97273
■ TerminationResistorsRequiredfortheUSBType-CConnector
– KBA97180
■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card
Reference Schematics
■ VBUS Bypass Capacitor Recommendation for Type-C Cable
and Type-C to Legacy Cable/Adapter Assemblies – KBA97270
■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle
■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution
■ CCG2 20W Power Adapter Reference Design
■ CCG2 18W Power Adapter Reference Design
■ Need for Regulator and Auxiliary Switch in Type-C to
DisplayPort (DP) Cable Solution - KBA97274
■ Need for a USB Billboard Device in Type-C Solutions –
KBA97146
■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference
■ CCG1DevicesinType-CtoLegacyCable/AdapterAssemblies
Design Kit
– KBA97145
Kits
■ Cypress USB Type-C Controller Supported Solutions –
■ CY4501 CCG1 Development Kit
■ CY4502 EZ-PD™ CCG2 Development Kit
■ CY4531 EZ-PD CCG3 Evaluation Kit
■ CY4541 EZ-PD™ CCG4 Evaluation Kit
KBA97179
■ Termination Resistors for Type-C to Legacy Ports – KBA97272
■ Handling Instructions for CY4502 CCG2 Development Kit –
KBA97916
■ Thunderbolt™ Cable Application Using CCG3 Devices -
KBA210976
Datasheets
■ Power Adapter Application Using CCG3 Devices - KBA210975
■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974
■ Device Flash Memory Size and Advantages - KBA210973
■ Applications of EZ-PD™ CCG4 - KBA210739
Application Notes
■ CCG1 Datasheet: USB Type-C Port Controller with Power
Delivery
■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode
Controller on Type-C
■ CCG2: USB Type-C Port Controller Datasheet
■ CCG3: USB Type-C Controller Datasheet
■ AN96527 - Designing USB Type-C Products Using Cypress’s
CCG1 Controllers
■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™
CCG2
Document Number: 002-17682 Rev. *M
Page 39 of 43
EZ-PD™ CCG5
Document History Page
Document Title: EZ-PD™ CCG5, USB Type-C Port Controller
Document Number: 002-17682
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
5528106
SOBI
12/07/2016 New datasheet
Updated EZ-PD™ CCG5, USB Type-C Port Controller and Features.
Updated Logic Block Diagram.
Updated USB-PD Subsystem (SS) and reordered the Functional Overview
section.
*A
5606273
SOBI
01/27/2017
Updated GPIO.
Updated 40-Pin QFN Pin Map (Top View) for CYPD5125-40LQXIT[5].
Changed datasheet status to Preliminary.
Added Errata.
Added Table 4 through Table 7.
Added Table 9 through Table 41 in Device-Level Specifications.
Updated Logic Block Diagram, GPIO, and VBUS Discharge.
Updated Table 2, Table 3, Table 8, and Table 46.
Updated Figure 5 through Figure 9.
*B
5694572
SOBI
06/03/2017
Updated Figure 13 (spec 002-10631 Rev. ** to *A) in Packaging.
Updated compliance with USB spec in Sales, Solutions, and Legal Information.
Updated template.
Updated USB HS Mux and SBU Mux in Functional Overview.
Updated Flash in CPU and Memory Subsystem.
Updated Power System Overview.
Updated description of BGA pin P2.4 to support SCB4 I2C data.
Changed SID.PWR#1_A; VDDD from 3 V to 3.15 V for DFP application.
Changed SID.AC.dpdm.3; Trise_HS from 630 ps max to 300 ps min.
Changed SID.AC.dpdm.4, Tfall_HS from 630 ps max to 300 ps min.
Updated SID.PWR#23 - changed VSYS to VSYS_UFP and changed range to 2.7 to
5.5 V.
Added SID.PWR#23_A for DFP/DRP application.
Changed max value for SID.20VREG.8, VBUSLOADREG, from 0.2 to 0.3.
Updated SID.ADC.2, SID.ADC.4 to ±1.5.
*C
5885413
VGT
09/27/2017 Updated SID.PWR#18 description to extend to SBU, DPDM mux pins.
Updated SID.PWR#2 - changed VDDD_MAX to VSYS_MAX
Removed min value from SID.PWR#14, VDDIO_MAX.
Added min spec of -25mA for SID.PWR#19, Igpio_abs.
Removed ADC.AC spec.
.
Updated SID.DC.20vconn.11, OVP_hysteresis max.
Added SID.DC.20vconn.14, OVP_threshold_on.
Added SID.AC.dpdm.10, SID.AC.dpdm.11.
Changed min value of SID.AC.dpdm.1, BW_3dB_HS from 1000 to 700.
Changed max value of SID.DC.dpdm.12, SID.DC.dpdm.13 from 4 to 3.
Changed max value of SID.DC.dpdm.2, RON_FS to 12.
Corrected values for SID.AC.dpdm.8, SID.AC.dpdm.9.
Added SID.AC.20sbu.6, SID.AC.20sbu.8, and SID.AC.20sbu.8.
Document Number: 002-17682 Rev. *M
Page 40 of 43
EZ-PD™ CCG5
Document Title: EZ-PD™ CCG5, USB Type-C Port Controller
Document Number: 002-17682
Updated SID.DC.20sbu.12, SID.DC.20sbu.15, SID.DC.20sbu.6,
SID.DC.20sbu.7, SID.DC.20sbu.7A, SID.DC.20sbu.8, SID.DC.20sbu.9,
SID.DC.20sbu.10, SID.DC.20sbu.11, SID.DC.20sbu.3, and SID.DC.20sbu.3.
Changed SBU pins ESD voltage to 750 V.
Added new Table 28, new Table 29, Table 43 through Table 45.
Updated Figure 5, Figure 8, Figure 9.
*C
(contd.)
5885413
VGT
09/27/2017
Added Figure 7.
Removed ADC AC specifications and CSA AC specifications (Table 28 and Table
32 from previous revision).
Removed Errata.
Added "Thunderbolt hosts and devices" in Applications.
Updated Figure 1 to correctly depict "2 x ADC" for entire CCG5.
Updated description of VDDD pin in Table 2 and Table 3.
Updated the description for pin P2.4 in Table 3.
Added "CYPD5235-96BZXI" and "CYPD5236-96BZXI" part numbers to the
description of Table 3 and Figure 6.
Updated VBUS_P1_MAX and VBUS_P2_MAX values to 24 in Table 8.
Updated min value of ESD_HBM_SBU spec from 750 to 1100 V in Table 8.
Added "Applicable for all pins except SBU pins" in description of "ESD_HBM"
parameter in Table 8.
Updated description of VGPIO_OVT_ABS in Table 8.
Updated description of ESD_IEC_CON and ESD_IEC_AIR parameters in
Table 8.
Changed SID.PWR#13 min value from 1.7 to VDDD in Table 9.
Updated min value of SID.PWR#23 to 2.75 in Table 9.
Updated pin description, values, and details/conditions of parameters
SID.PWR#1 and SID.PWR#1_A to better define VDDD supply in Table 9.
Replace VDDD with VSYS in supply name and conditions for IDD parameters listed
in Table 9.
*D
5943992
VGT
10/24/2017
Updated Conditions for SID.CLK#4 to “All VDDD” in Table 10.
Removed SID.PWR#20 in Table 10.
Added Guaranteed by Design for SID178 and SID180 in Table 20.
Added description for SID.MEM#8 in Table 20.
Added description for SID.CLK#13 and SID.CLK#13A in Table 24.
Added Guaranteed by Design for SID.DC.cc_shvt.4 in Table 26.
Deleted details and conditions for SID.DC.cc_shvt.14 in Table 26.
Removed SID.DC.cc_SHVT.19 in Table 26.
Updated spec values in Table 32.
Added Guaranteed by Design for SID.AC.PGDO.2 in Table 34.
Added Guaranteed by Design for SID.DC.20sbu.19 through SID.DC.20sbu.22
and removed SID.AC.20sbu.3 in Table 35.
Added Guaranteed by Design for SID.AC.20SBU.5 in Table 36.
Updated max value for SID.AC.20SBU.8 in Table 36.
Removed SID.DC.dpdm.3 and SID.DC.dpdm.4 and added Guaranteed by Design
for SID.DC.dpdm.5 and SID.DC.dpdm.11 through SID.DC.dpdm.13 in Table 37.
Updated SID.DC.dpdm.12 and SID.DC.dpdm.13 max value in Table 37.
Removed SID.AC.dpdm.1, SID.AC.dpdm.2, SID.AC.dpdm.3, and
SID.AC.dpdm.4 in Table 38.
Document Number: 002-17682 Rev. *M
Page 41 of 43
EZ-PD™ CCG5
Document Title: EZ-PD™ CCG5, USB Type-C Port Controller
Document Number: 002-17682
Added Guaranteed by Design for SID.AC.dpdm.6, SID.AC.dpdm.7,
SID.AC.dpdm.8, SID.AC.dpdm.9, SID.AC.dpdm.10, and SID.AC.dpdm.13 in
Table 38.
*D (cont.) 5943992
VGT
10/24/2017 Added Guaranteed by Design for SID.DC.20VCONN.11 in Table 39.
Removed SID.DC.20VCONN.13 in Table 39.
Added Guaranteed by Design for SID.AC.20VCONN.2 in Table 40.
Updated min value of VSYS to 2.75 throughout the document.
Updated Figure 8.
11/16/2017
*E
*F
5968629
6040630
VGT
HPV
Added Figure 10 and Figure 11 and associated content.
02/16/2018 Removed VBUS Regulator DC Specifications.
Updated pin name and description of P2.4 pin in Table 3.
Updated Power System Overview.
Updated pin name of pin K5 in Figure 6.
Updated application diagrams in Figure 8, Figure 10, and Figure 11.
Added SID.PWR#5.
*G
6111610 VGT/AKK 03/27/2018
Added MPN CYPD5135-40LQXIT in Table 42.
Added MPNs CYPD5225-96BZXIT, CYPD5235-96BZXIT and
CYPD5236-96BZXIT in Table 42.
*H
*I
6206852
6212870
VGT
HPV
06/13/2018
06/26/2018 Updated in Typ. value for IDD_DS1 in Table 9.
Updated Figure 8, Figure 9, Figure 10, and Figure 11.
Updated Table 9.
Updated min value for SID.DC.20VCONN.9 in Table 39.
*J
6270910
VGT
09/06/2018
Updated Ordering Code Definitions.
Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated I/O:
Updated Table 11 (Added VOL_I2C_2, VOL_I2C_3, VOL1_20mA parameters and their
*K
6375937
SUDH
11/27/2018
details).
Added Note 10 and referred the same note in max value of VOL_I2C_3 parameter.
Updated Ordering Information:
Updated Table 42 (Updated part numbers).
Updated Table 2 and Table 3: Updated VDDD Description (“VBUS powered - 3.15
V to 3.6 V” as “VBUS powered - 3.15 V to 3.65 V”).
02/19/2019 Updated Table 9: Updated VDDD Spec Limit to 3.65V.
Updated USB HS Mux.
*L
6460196
6503433
SUDH
SUDH
Updated Copyright information.
Updated CYPD5125-40LQXI as Not Recommended for New Designs (NRND).
03/28/2019
*M
Updated References and Links To Applications Collaterals.
Document Number: 002-17682 Rev. *M
Page 42 of 43
EZ-PD™ CCG5
Sales, Solutions, and Legal Information
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Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB
Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify
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NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.
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Document Number: 002-17682 Rev. *M
Revised March 28, 2019
Page 43 of 43
相关型号:
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