CYPD7191-40LDXS [INFINEON]
EZ-PD™ CCG7S CYPD7191-40LDXS is the tray packing type option belonging to EZ-PD™ CCG7S family of Infineon’s highly integrated single-port USB-C Power Delivery (PD) with integrated buck-boost controller for automotive in-cabin charger applications.;
| 型号： | CYPD7191-40LDXS |
| 厂家： | 
Infineon |
| 描述： | EZ-PD™ CCG7S CYPD7191-40LDXS is the tray packing type option belonging to EZ-PD™ CCG7S family of Infineon’s highly integrated single-port USB-C Power Delivery (PD) with integrated buck-boost controller for automotive in-cabin charger applications. 光电二极管 |
| 文件： | 总48页 (文件大小：485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYPD7191-40LDXS
EZ-PD™ CCG7S Automotive single-port USB
Type-C with PD and buck-boost controller
General description
EZ-PD™ CCG7S is a highly integrated single-port USB Type-C Power delivery (PD) solution with an integrated
buck-boost controller. It complies with the latest USB Type-C and PD specifications, and is targeted for
automotive charger applications such as head unit (HU) chargers, rear seat entertainment (RSE) and rear seat
chargers (RSC). Integration offered by EZ-PD™ CCG7S not only reduces the BOM but also provides a footprint
optimized solution for automotive charging needs. It also includes hardware-controlled protection features on
the VBUS. EZ-PD™ CCG7S supports a wide input voltage range (4 V–24 V with 40 V tolerance) and programmable
switching frequency (150 kHz–600 kHz) in an integrated PD solution.
EZ-PD™ CCG7S is the most programmable USBPD solution with an on-chip 32-bit Arm® Cortex®-M0 processor,
128-KB flash, 16-KB RAM and 32-KB ROM that leaves most flash available for user application use. It also includes
various analog and digital peripherals such as ADC, PWMs and timers. The inclusion of a fully programmable MCU
with analog and digital peripherals allows the implementation of custom system management functions such as
power throttling, load sharing, temperature monitoring, and fault logging.
Applications
• Head unit (HU) charger
• Rear seat charger (RSC)
• Rear seat entertainment (RSE)
Features
• USBPD
- Supports one USBPD port
- Supports latest USBPD 3.1 including programmable power supply (PPS) mode
- Extended data messaging
• Type-C
- Configurable resistors Rp and Rd
- VBUS provider NFET Gate driver
- Integrated 100-mW VCONN power supply and control
• 1x buck-boost controller
- 150 kHz to 600 kHz switching frequency
- 4.5 V to 24 V input, 40V tolerant
- 3.3 V to 21.5 V output
- 20-mV voltage and 50-mA current steps for PPS
- Supports selectable pulse skipping mode (PSM) and forced continuous current/conduction mode (FCCM)
- Supports soft start
- Programmable spread spectrum frequency modulation for low EMI
• 1x legacy/proprietary charging block
- Supports Qualcomm QC 2.0/3.0/4.0/5.0, Apple charging 2.4 A, Samsung adaptive fast charging (AFC),
USB BC 1.2
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Features
• System-level fault protection
- On-chip VBUS overvoltage protection (OVP), overcurrent protection (OCP), undervoltage protection (UVP)
- VBUS to CC short protection
- VBAT to GND protection FET gate driver
- Under-voltage lockout (UVLO)
- Supports over-temperature protection through integrated ADC circuit and internal temperature sensor
- Supports connector and board temperature measurement using external thermistors
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0 CPU
- 128-KB Flash
- 16-KB SRAM
- 32-KB ROM
• Peripherals and GPIOs
- Up to 13 GPIOs including two overvoltage GPIOs
- 2x 8-bit ADC
- 8x 16-bit timer/counter/PWMs (TCPWM)
• Communication interfaces
- 3x SCBs (I2C/SPI/UART/LIN)
• Clocks and oscillators
- Integrated oscillator eliminating the need for an external clock
• Power supply
- 4 V to 24 V input (40 V tolerant)
- 3.3 V to 21.5 V output
- Integrated LDO capable of 5 V @ 75 mA
• Packages
- 40-pin QFN, wettable flank, AEC-Q100
- Supports automotive ambient temperature range (–40°C to +105°C) with 125°C operating junction
temperature
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Logic block diagram
Logic block diagram
EZ-PD™ CCG7S: single-port USB Type-C PD and buck-boost controller
MCU subsystem
I/O subsystem
Integrated digital blocks
CC
Arm
8x TCPWM
Cortex -M0
48MHz
VCONN
3x SCB
13x GPIOs
(I2C, SPI, UART, LIN)
Flash (128 KB)
SROM (32 KB)
SRAM (16 KB)
CRYPTO (TRNG)
USBPD subsystem
VCONN OCP, UV
Baseband MAC & PHY
V
Bus to CC short-
Hi-Voltage LDO (24 V)
8-bit SAR ADC
circuit protection
2x VCONN FETs
System
resources
V
Bus OVP, OCP, SCP
NFET load switch
gate driver
protection
VBATT to GND short -
circuit protection
Buck-boost controller
Functional block diagram
COMP
BST1
HGT1
SW1
LG1
BST2
HGT2
SW2 LG2
CSPO
CSNO
VBUS_CTRL
CSPI
CSNI
Input current
sense amplifier
(CSA), Slope
Error
amplifier
(CV)
Error
amplifier
(CC)
GDRV (Buck)
GDRV (Boost)
Slew rate control
NGATE driver
High-side
CSA
High-side
Low-side driver
(LSDR)
High-side
Low-side driver
(LSDR)
driver (HSDR)
driver (HSDR)
compensation
CSNO
VBUS_C
discharge discharge
Zero crossing
detect (ZCD)
Zero crossing
detect (ZCD)
Charge control
Charge control
CC reference
CC1
V5V
CC2
HV regulator
(VIN → 5 V)
BMC
Reference
and IDAC
VIN
VDDD
VCCD
VCONN
PHY
Pulse-width
modulator
(PWM)
MCU subsystem
Cortex-M0
Charger
detect
DP
DM
2x 8-bit ADC
13x GPIOs
8x TCPWM
LV regulator
(5 V → 1.8 V)
3x SCB
(I2C/SPI/
UART/LIN)
Flash
(128 KB)
SROM
(32 KB)
SRAM
(16 KB)
XRES
POR/RESET
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Table of contents
Table of contents
General description ...........................................................................................................................1
Applications......................................................................................................................................1
Features ...........................................................................................................................................1
Logic block diagram ..........................................................................................................................3
Functional block diagram...................................................................................................................3
Table of contents...............................................................................................................................4
1 Functional overview .......................................................................................................................5
1.1 MCU subsystem.......................................................................................................................................................5
1.2 USBPD subsystem...................................................................................................................................................5
1.3 Buck-boost subsystem ...........................................................................................................................................8
1.4 Buck-boost controller operation regions ............................................................................................................10
1.5 Analog blocks ........................................................................................................................................................12
1.6 Integrated digital blocks.......................................................................................................................................12
1.7 I/O subsystem .......................................................................................................................................................13
1.8 System resources..................................................................................................................................................14
2 Power subsystem..........................................................................................................................15
2.1 VIN under-voltage lockout (UVLO) .......................................................................................................................16
2.2 Using external VDDD supply.................................................................................................................................16
2.3 Power modes ........................................................................................................................................................16
3 Pin list .........................................................................................................................................17
4 EZ-PD™ CCG7S programming and bootloading ................................................................................20
4.1 Programming the device flash over SWD interface.............................................................................................20
5 Applications .................................................................................................................................21
6 Electrical specifications.................................................................................................................28
6.1 Absolute maximum ratings ..................................................................................................................................28
6.2 Device-level specifications ...................................................................................................................................29
6.3 Digital peripherals.................................................................................................................................................33
6.4 System resources..................................................................................................................................................35
7 Ordering information ....................................................................................................................41
7.1 Ordering code definitions.....................................................................................................................................41
8 Packaging ....................................................................................................................................42
8.1 Package diagrams.................................................................................................................................................43
9 Acronyms.....................................................................................................................................45
10 Document conventions................................................................................................................46
10.1 Units of measure .................................................................................................................................................46
Revision history ..............................................................................................................................47
Datasheet
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Functional overview
1
Functional overview
MCU subsystem
CPU
1.1
1.1.1
The Cortex-M0 in EZ-PD™ CCG7S devices is a 32-bit MCU, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. It
also includes a hardware multiplier, which provides a 32-bit result in one cycle. It includes an Interrupt controller
(the NVIC block) with 32 interrupt inputs and a wakeup interrupt controller (WIC), which can wake the processor
up from deep sleep mode.
1.1.2
Flash ROM and SRAM
EZ-PD™ CCG7S devices have 128-KB flash and 32-KB ROM for non-volatile storage. ROM stores libraries for
authentication and device drivers such as I2C, SPI, and so on. That spares flash for user application. Flash provides
the flexibility to store code for any customer feature and allows firmware upgrades to meet the latest USB power
delivery specifications and application needs.
The 16-KB RAM is used under software control to store the temporary status of system variables and parameters.
A supervisory ROM that contains boot and configuration routines is provided.
1.2
USBPD subsystem
This subsystem provides the interface to the Type-C USB port. This subsystem comprises:
• USBPD physical layer
• VCONN switches and 100mW VCONN source
• Undervoltage protection (UVP), overvoltage protection (OVP) on VBUS
• Output high-side current sense amplifier (HS CSA) for VBUS
• VBUS discharge control
• Gate driver for VBUS provider NFET
• Charger detection block for legacy charging (for example: BC1.2, Apple charging, and so on)
• VBAT to ground short-circuit protection
• VBUS to CC short-circuit protection
1.2.1
USBPD physical layer
The USBPD subsystem contains the USBPD physical layer block and supporting circuits. The USBPD physical
layer consists of a transmitter and receiver that communicate BMC encoded data over the CC channel per the PD
3.1 standard. All communication is half-duplex. The physical layer or PHY implements collision avoidance to
minimize communication errors on the channel. The USBPD block includes all termination resistors (Rp and Rd)
and their switches as required by the USB Type-C spec. Rp and Rd resistors are required to implement connection
detection, plug orientation detection and for the establishment of the USB source/sink roles. The Rp resistor is
implemented as a current source.
The CCG7S device family along with the accompanying firmware is fully complaint with revision 3.1 of the USB
Power delivery specification. The device supports programmable power supply (PPS) operation at all valid
voltages from 3.3 V to 21 V.
EZ-PD™ CCG7S devices support Rp under HW control in unconnected (standby) state to minimize standby power.
EZ-PD™ CCG7S devices support USBPD extended messages containing data of up to 260 bytes. The extended
messages are larger than expected by USBPD 2.0 hardware. As per the USBPD protocol specification, USBPD 3.1
compliant devices implement a chunking mechanism; messages are limited to revision 2.0 sizes unless both
source and sink confirm and negotiate compatibility with longer message lengths.
Datasheet
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buck-boost controller
Functional overview
1.2.2
VCONN switches
EZ-PD™ CCG7S’ internal LDO voltage regulator is capable of powering a 100mW VCONN supply for electronically
marked cable assemblies (EMCA), VCONN-powered devices (VPD), and VCONN-powered accessories (VPA) as
defined in the USB Type-C specification. All circuitry including VCONN switches and overcurrent protection is
integrated in the device. In the event the VCONN current exceeds the VCONN OCP limit, CCG7S can be configured
to shut down the Type-C port after a certain number of user configurable retries. The port can be re-enabled after
a physical disconnect.
1.2.3
VBUS UVP and OVP
VBUS under-voltage and overvoltage faults are monitored using internal resistor dividers. The fault thresholds
and response times are user configurable. Refer to the EZ-PD™ configuration utility for more details. In the event
of a UVP or OVP, EZ-PD™ CCG7S can be configured to shut down the Type-C port after a certain number of user
configurable retries. The port can be re-enabled after a physical disconnect.
1.2.4
VBUS OCP and SCP
VBUS overcurrent and short-circuit faults are monitored using internal current sense amplifiers. Similar to OVP
and UVP, the OCP and SCP fault thresholds and response times are configurable as well. Refer to the
EZ-PD™ configuration utility for more details. In the event of OCP or SCP, CCG7S can be configured to shut down
the Type-C port after a certain number of user configurable retries. The port can be re-enabled after a physical
disconnect.
1.2.5
HS-CSA for VBUS
EZ-PD™ CCG7S device family supports VBUS current measurement and control using an external resistor (5mΩ)
in series with the VBUS path. The voltage drop across this resistor is used to measure the average output current.
The same resistor is also used to sense and precisely control the output current in the PPS current foldback mode
of operation.
1.2.6
VBUS discharge control
The chip supports high-voltage (21.5 V) VBUS discharge circuitry. Upon the detection of device disconnection,
faults, or hard resets, the chip will discharge the output VBUS terminals to vSafe5V and/or vSafe0V within the time
limits specified in the USBPD specification.
1.2.7
Gate driver for VBUS provider NFET
EZ-PD™ CCG7S devices have an integrated high-voltage gate driver to drive the gate of an external high-side NFET
on the VBUS provider path. The gate driver drives the load switch that controls the connection between CSNO
and VBUS_C. VBUS_CTRL is the output of this gate driver. To turn off the external NFET, the gate driver drives
CSNO low to 0 V. To turn on the external NFET, it drives the gate to CSNO + 8 V. There is an optional slow turn-on
feature which reduces the high-current spikes on the output. For a typical gate capacitance of 3 nF, a slow turn-on
time of 2 ms to 10 ms is configurable using firmware.
1.2.8
Legacy charge detection and support
EZ-PD™ CCG7S implements battery charger emulation and detection (source and sink) for USB BC.1.2, legacy
Apple charging, Qualcomm quick charge 2.0/3.0/4.0/5.0, and Samsung AFC protocols.
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Functional overview
1.2.9
VBAT to ground short protection
EZ-PD™ CCG7S devices can protect against high currents through the Type-C return (ground) path. A NFET and a
current sense resistor are placed in series with the ground return path from the Type-C connector as shown in
Figure 1. This resistor senses the current, and if it exceeds the firmware-configured threshold, the NFET is turned
off to interrupt the current. This protects against overcurrent conditions caused by external faults (for example,
if the Type-C connector ground is accidentally connected to the car’s battery). The current sense can be
implemented with either a single-ended connection (referenced to internal ground) or with a true differential
connection (see CSN connection in Figure 1). The differential connection provides better current measurement
accuracy but uses an extra GPIO pin. In the event of VBAT to ground short protection, EZ-PD™ CCG7S can be
configured to shut down the series FET between the Type-C receptacle ground and the system ground. The
recovery and retry mechanism can be customized using application firmware.
PGND
CSN
(optional)
5 m
GND
CSP
GPIO
Figure 1
VBUS to ground short circuit protection
1.2.10
VBUS to CC short protection
CC pins have integrated protection from accidental shorts to high-voltage VBUS and VBAT. EZ-PD™ CCG7S
devices can handle up to 24 V external voltage on its CC pins without damage. In the event, an overvoltage is
detected on the CC pin, it can be configured to shut down the Type-C port completely. The port will resume
normal operation once the CC voltage detected is within normal range.
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Functional overview
1.3
Buck-boost subsystem
The buck-boost subsystem in EZ-PD™ CCG7S devices can be configured to operate in buck-boost mode,
buck-only mode or boost-only mode. While buck-boost mode requires four external switching FETs, buck-only
and boost-only modes require only two FETs. Buck-only mode is useful when EZ-PD™ CCG7S device’s port is used
for USB Type-A only applications. Figure 2 shows the buck-boost subsystem’s main external components and
connections.
5 m
5 m
VIN
VOUT
CSR1
CSR2
VDDD
VDDD
CYPD719X
Figure 2
Buck-boost schematic showing external components
Buck-boost subsystem in EZ-PD™ CCG7S devices have the following key functional blocks:
• High side (cycle-by-cycle) current sense amplifier
• High side and low side gate driver
• Pulse width modulator
• Error amplifier
1.3.1
High side (cycle-by-cycle) current sense amplifier (CSA)
EZ-PD™ CCG7S device’s buck-boost controller implements peak current control in both boost and buck modes.
A high side current sense amplifier (CSA) is used for peak current sensing through an external resistor (5mΩ; see
CSR1 in Figure 2) placed in series with the buck control FET. This current sense amplifier has a high bandwidth
and a very wide common mode range. This current sense resistor is connected to the CSA block through pins CSPI
and CSNI as shown in Figure 2. This block implements slope compensation to avoid sub-harmonic oscillation for
the internal current loop. In addition to peak current sensing, it provides a current limit comparator for shutting
off the buck-boost converter if the current hits an upper threshold which is programmable.
1.3.2
High-side gate driver and low-side gate driver (HG/LG)
EZ-PD™ CCG7S’ buck-boost controller provides four N-channel MOSFET gate drivers: two floating high-side gate
drivers at the HG1 and HG2 pins, and two ground referenced low-side drivers at the LG1 and LG2 pin. The high
side gate drivers drive the high side external FET with a nominal VGS of 5V. The High-side gate driver has a
programmable drive strength to drive external FET. An external capacitor and Schottky diode form a bootstrap
network to collect and store the high voltage source (VIN + ~5 V for HG1 and VBUS + ~5 V for HG2) needed to drive
the high-side FET. The low side gate driver drives the low side external FET with a nominal VGS of 5 V using energy
sourced from EZ-PD™ CCG7S’ internal LDO regulator and stored in the capacitor between PVDD and PGND.
Low-side gate driver has programmable drive strength to drive external FET. In addition to drive strength, the
high-side gate driver and the low-side gate driver have programmable options for deadtime control and
zero-crossing levels. High-side gate driver and low-side gate driver blocks include zero-crossing detector (ZCD)
to implement discontinuous-conduction mode (DCM) mode with diode emulation.
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Functional overview
The gate drivers for the switching FETs function at their nominal drive voltage levels (5 V) provided the VIN voltage
is between 4.5 V and 24 V.
1.3.3
Error amplifier (EA)
EZ-PD™ CCG7S’ buck-boost controller contains two error amplifiers for output voltage and current regulation.
The error amplifier is a trans-conductance type amplifier with single compensation pin (COMP) to ground for both
the voltage and current loops. In voltage regulation, the output voltage is compared with the internal reference
voltage and the output of EA is fed to the PWM block. In current regulation, the average current is sensed by VBUS
high side current sense amplifier through the external resistor. The output of the VBUS CSA is compared with an
internal reference in error amplifier block and EA output is fed to the PWM block. EZ-PD™ CCG7S firmware
configures and controls the integrated programmable error amplifier circuit for achieving the required VBUS
voltage output from the power section.
1.3.4
Pulse width modulator (PWM)
EZ-PD™ CCG7S device family’s PWM block generates the control signals for the gate drivers driving the external
FETs in peak current mode control. There are many programmable options for minimum/maximum pulse width,
minimum/maximum period, frequency and pulse skip levels to optimize the system design.
EZ-PD™ CCG7S devices have two firmware-selectable operating modes to optimize efficiency and reduce losses
under light load conditions: pulse skipping mode (PSM) and forced continuous conduction mode (FCCM).
1.3.5
Pulse skipping mode (PSM)
In pulse skipping mode, the controller reduces the total number of switching pulses without reducing the active
switching frequency by working in "bursts" of normal nominal-frequency switching interspersed with intervals
without switching. The output voltage thus increases during a switching burst and decreases during a quiet
interval. This mode results in minimal losses at the cost of higher output voltage ripple. When in this mode,
EZ-PD™ CCG7S devices monitor the voltage across the buck or boost sync FET to detect when the inductor current
reaches zero; when this occurs, the EZ-PD™ CCG7S devices switch off the buck or boost sync FET to prevent
reverse current flow from the output capacitors (i.e. diode emulation mode). Several parameters of this mode
are programmable through firmware, allowing the user to strike their own balance between light load efficiency
and output ripple.
1.3.6
Forced continuous conduction mode (FCCM)
In Forced continuous conduction mode (FCCM), the nominal switching frequency is maintained at all times, with
the inductor current going below zero (i.e. “backwards” or from the output to the input) for a portion of the
switching cycle as necessary to maintain the output voltage and current. This keeps the output voltage ripple to
a minimum at the cost of light-load efficiency.
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Functional overview
1.4
Buck-boost controller operation regions
The input-side CSA’s output is compared with the output of the error amplifier to determine the pulse width of
the PWM. PWM block compares the input voltage and output voltage to determine the buck, boost, and
buck-boost regions. The switching time/period of the four gate drivers (HG1, LG1, HG2, LG2) depends upon the
region in which the block is operating as well as the mode such as DCM or FCCM. The exact VIN vs VOUT thresholds
for transitions into and out of each region are adjustable in firmware including the hysteresis.
1.4.1
Buck region operation (VIN >> VBUS)
When the VIN voltage is significantly higher than the required VBUS voltage, EZ-PD™ CCG7S devices operate in
the buck region. In this region, the boost side FETs are inactivated, with the boost control FET (connected to LG2)
turned off and the boost sync FET (connected to HG2) turned on. The buck side FETs are controlled as a buck
converter with synchronous rectification as shown in Figure 3.
ON
HG1
(Buck
Control)
OFF
ON
LG1 (Buck
Sync)
OFF
ON
LG2
(Boost
Control)
OFF
ON
HG2
(Boost
Sync)
OFF
Inductor
Current
0
t
Figure 3
Buck operation waveforms
1.4.2
Boost region operation (VIN << VBUS)
When the VIN voltage is significantly lower than the required VBUS voltage, EZ-PD™ CCG7S devices operate in the
boost region. In this region, the buck side FETs are inactivated, with the sync FET turned off and the buck control
FET turned on. The boost side FETs are controlled as a boost converter with synchronous rectification as shown
in Figure 4.
ON
HG1
(Buck
Control)
OFF
ON
LG1 (Buck
Sync)
OFF
ON
LG2
(Boost
Control)
OFF
ON
OFF
Inductor
Current
0
t
Figure 4
Boost operation waveforms
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Functional overview
1.4.3
Buck-boost region 1 operation (VIN ~> VBUS)
When the VIN voltage is slightly higher than the required VBUS voltage, EZ-PD™ CCG7S devices operate in the
buck-boost region 1. In this region, the boost side works at a fixed 20% duty cycle (programmable) while the buck
side (LG1 / HG1) duty cycle is modulated to control the output voltage. All four FETs are switching every cycle in
this operating region as shown in Figure 5.
ON
HG1
(Buck
Control)
OFF
ON
LG1 (Buck
Sync)
OFF
ON
LG2
(Boost
Control)
OFF
ON
HG2
(Boost
Sync)
OFF
Inductor
Current
0
t
Figure 5
Buck-boost region 1 (VIN ~> VBUS) operation waveforms
1.4.4
Buck-boost region 2 operation (VIN ~< VBUS)
When the VIN voltage is slightly lower than the required VBUS voltage, EZ-PD™ CCG7S devices operate in the
buck-boost region 2. In this region, the buck side works at a fixed 80% duty cycle (programmable) while the boost
side (LG2) duty cycle is modulated to control the output voltage. All four FETs are switching every cycle in this
operating region as shown in Figure 6.
ON
HG1
(Buck
Control)
OFF
ON
LG1 (Buck
Sync)
OFF
ON
LG2
(Boost
Control)
OFF
ON
HG2
(Boost
Sync)
OFF
Inductor
Current
0
t
Figure 6
Buck-boost region 2 (VIN ~< VBUS) operation waveforms
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Functional overview
1.4.5
Switching frequency and spread spectrum
EZ-PD™ CCG7S devices offer programmable switching frequency between 150 kHz and 600 kHz. The controller
supports spread spectrum clocking within the operating frequency range in all operating modes. Spread
spectrum is essential for charging applications to meet EMC/EMI requirements by spreading emissions caused
by switching over a wide spectrum instead of a fixed frequency, thereby reducing the peak energy at any
particular frequency. Both the switching frequency and the spread spectrum span are firmware programmable.
1.5
Analog blocks
ADC
1.5.1
EZ-PD™ CCG7S devices have two 8-bit SAR ADCs for general purpose A-D conversion applications in the chip. The
ADCs can be accessed from the GPIOs through an on-chip analog mux. See Table 27 for detailed specs on the
ADCs.
1.6
Integrated digital blocks
1.6.1
Serial communication block (SCB)
EZ-PD™ CCG7S devices have three SCB blocks that can be configured for I2C, SPI, UART or LIN. These blocks
implement full multi-master and slave I2C interfaces capable of multi-master arbitration. This I2C implemen-
tation is compliant with the standard Philips I2C specification v3.0. These blocks operate at speeds of up to 1
Mbps and have flexible buffering options to reduce interrupt overhead and latency for the CPU. The SCB blocks
support 8-byte deep FIFOs for receive and transmit, which, by increasing the time given for the CPU to read data,
greatly reduces the need for clock stretching caused by the CPU not having read data on time. The I2C port I/Os
for SCB0 are overvoltage tolerant (OVT). The I2C ports for SCB1-2 are not OVT tolerant.
1.6.2
Timer, counter, pulse-width modulator (TCPWM)
The TCPWM block of EZ-PD™ CCG7S devices support eight timers or counters or pulse-width modulators. These
timers are available for internal timer use by firmware or for providing PWM-based functions on the GPIOs.
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Functional overview
1.7
I/O subsystem
The EZ-PD™ CCG7S devices have 13 GPIOs including the I2C and SWD pins which can also be used as GPIOs. The
GPIO block implements the following:
• Eight output drive modes
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Disabled
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL)
• Individual control of input and output disables
• Hold mode for latching previous state (used for retaining I/O state in deep sleep mode)
• Selectable slew rates for dV/dt related noise control.
• Overvoltage tolerance (OVT) on one pair of GPIOs
During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex
between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals such as USB
Type-C port are also fixed in order to reduce internal multiplexing complexity. Data output registers and pin state
register store, respectively, the values to be driven on the pins and the states of the pins themselves.
The configuration of the pins can be done by the programming of registers through software for each digital I/O
port. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and
interrupt service routine (ISR) vector associated with it.
The I/O ports can retain their state during deep sleep mode or remain ON. If the operation is restored using reset,
then the pins shall go the high-Z state. If operation is restored by an interrupt event, then the pin drivers shall
retain their state until firmware chooses to change it. The IOs (on data bus) do not draw current on power down.
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buck-boost controller
Functional overview
1.8
System resources
Watchdog timer
1.8.1
EZ-PD™ CCG7S devices have a watchdog timer running from the internal low-speed oscillator (ILO). This allows
Watchdog operation during Deep sleep and generate a watchdog reset if not serviced before the timeout occurs.
The watchdog reset is recorded in the reset cause register.
1.8.2
Reset
EZ-PD™ CCG7S devices can be reset from a variety of sources including a software reset. Reset events are
asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is
preserved through reset and allows application firmware to determine the cause of the reset. XRES pin is the
dedicated pin for asserting an external hardware reset.
1.8.3
Clock system
EZ-PD™ CCG7S devices have a fully integrated clock with no external crystal required. EZ-PD™ CCG7S device’s
clock system is responsible for providing clocks to all sub-systems that require clocks (SCB and PD) and for
switching between different clock sources.
The HFCLK signal can be divided down as shown to generate synchronous clocks for the digital peripherals. The
clock dividers have 8-bit, 16-bit and 16-bit fractional divide capability. The 16-bit capability allows a lot of
flexibility in generating fine-grained frequency values. The clock dividers generate either enabled clocks (that is,
1 in N clocking where N is the divisor) or an approximately 50% duty cycle clock (exactly 50% for even divisors,
one clock difference in the high and low values for odd divisors).
In Figure 7, PERXYZ_CLK represents the clocks for different peripherals.
IMO
HFCLK
Pre-divider
ILO
LFCLK
HFCLK
Prescaler
SYSCLK
HALFSYSCLK
/2
Peripheral
dividers
PERXYZ_CLK
Figure 7
Clocking architecture of EZ-PD™ CCG7S devices
1.8.4
IMO clock source
The internal main oscillator is the primary source of internal clocking in EZ-PD™ CCG7S devices. IMO default
frequency for EZ-PD™ CCG7S devices is 48 MHz+/-2%.
1.8.5
ILO clock source
The internal low-power oscillator is a very low power, relatively inaccurate, oscillator, which is primarily used to
generate clocks for peripheral operation in USB suspend (deep sleep) mode.
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buck-boost controller
Power subsystem
2
Power subsystem
Figure 8 shows an overview of the power subsystem architecture for EZ-PD™ CCG7S devices. The power
subsystem of EZ-PD™ CCG7S devices operate from VIN supply which can vary from 4 V to 24 V. The VDDD pin, the
output of an internal 5V LDO, gets input from VIN supply. The current capability of the VDDD pin is up to 75mA
including internal as well as external loads. EZ-PD™ CCG7S devices have two different power modes: Active and
Deep sleep, transitions between which are managed by the power system. The VCCD pin, the output of the core
(1.8 V) regulator, is brought out for connecting a 0.1-µF capacitor for the regulator stability only. This pin is not
supported as a power supply for external load.
CSNO
VBUS_C
PVDD
Buck-boost
LS driver
NGDO
1µF
PGND
VIN
VDDD
CC2
LDO
10 µF
CC1
Core regulator
VCCD
GND
0.1 µF
1 x CC
Tx/Rx
GPIOs
Core
Figure 8
Power system requirement block diagram
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buck-boost controller
Power subsystem
2.1
VIN under-voltage lockout (UVLO)
EZ-PD™ CCG7S supports UVLO to allow the device to shut down when the input voltage is below the reliable level.
It guarantees predictable behavior when the device is up and running.
2.2
Using external VDDD supply
By default, external VDDD is not supported for EZ-PD™ CCG7S devices. However, usage of external VDDD supply
can be enabled using firmware. The prerequisite for enabling external forcing of VDDD is to always maintain VIN
higher than VDDD.
2.3
Power modes
The Power modes of the device accessible and observable by the user are listed in Table 1.
Table 1
Power modes
Description
Mode
Power is valid and XRES is not asserted. An internal reset source is asserted or Sleep controller is
sequencing the system out of reset.
RESET
ACTIVE
SLEEP
Power is valid and CPU is executing instructions.
Power is valid and CPU is not executing instructions. All logic that is not operating is clock gated to save
power.
Main regulator and most hard-IP are shut off. Deep sleep regulator powers logic, but only low-frequency
clock is available.
DEEP SLEEP
XRES
Power is valid and XRES is asserted. Core is powered down.
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Pin list
3
Pin list
Table 2
Automotive 40-QFN package pinout
Absolute
Absolute
Sl# Pin name
minimum
(V)
Description
maximum (V)
Buck high side gate driver output.
Connect to the buck (input) side control (high side) FET gate. Use a wide
trace to minimize inductance of this connection. Absolute min and max
are with respect to SW1 pin.
[1, 2, 3]
1
2
HG1
SW1
-0.5
PVDD+0.5
Negative power rail of the buck high side gate driver.
This is also connected to one input terminal of zero current detection
of buck low side gate driver.
-0.7
35
Connect to the switch node (inductor) on the buck (input) side. Use a
short and wide trace to minimize the inductance and resistance of this
connection.
Buck low side gate driver output.
[1]
3
4
5
6
LG1
PGND
PVDD
LG2
-0.5
-0.3
–
PVDD+0.5
Connect to the buck (input) side sync (low side) FET gate. Use a wide
trace to minimize inductance of this connection.
Ground of low side gate driver. This is also connected to one input
terminal of zero current detection of buck low side gate driver.
Connect directly to the port’s board ground plane.
0.3
Supply of low side gate driver.
VDDD
Connect to VDDD. Use 1 μF and 0.1 μF bypass capacitors as close to the
EZ-PD™ CCG7S IC as possible.
Boost low side gate driver output.
[1]
-0.5
PVDD+0.5
Connect to the boost (output) side control (low side) FET gate. Use a
wide trace to minimize inductance of this connection.
Output of the Buck-boost converter. This is also connected to one input
terminal of reverse current protection of Boost high side gate driver.
Connect to the boost sync (high side) FET’s drain. Use a dedicated
(Kelvin) trace for this connection.
7
8
VOUT
SW2
-0.3
24
24
Negative power rail of the boost high side gate driver. This is also
connected to one input terminal of reverse current protection of boost
high side gate driver.
-0.3
-0.5
Connect to the switch node (inductor) on the boost (output) side. Use a
short and wide trace to minimize the inductance and resistance of this
connection.
Boost high side gate driver output.
[1, 4]
9
HG2
PVDD+0.5
Connect to the boost (output) side sync (high side) FET gate. Use a wide
trace to minimize inductance of this connection.
Boosted power supply of the boost high side gate driver. Bootstrap
capacitor node. Connect Schottky diode from VDDD to BST2. Also,
connect a bootstrap capacitor from this pin to SW2.
[1, 4]
10
BST2
–
PVDD+0.5
11 VBUS_CTRL
-0.5
-0.5
32
VBUS NFET gate driver output. Connect to the provider NFET’s gate.
Error amplifier output pin. Connect a compensation network to GND.
Contact Infineon® for assistance in designing the compensation
network.
[1]
12
13
COMP
PVDD+0.5
Type-C connector VBUS voltage.
VBUS_C
CSNO
-0.3
-0.3
24
24
Connect to the Type-C connector’s VBUS pin.
Negative input of output current sensing amplifier.
14
Connect to negative terminal of the output current sense resistor.
Notes
1. Maximum voltage must not exceed 6 V.
2. Maximum absolute voltage w.r.t GND must not exceed 40 V.
3. The absolute maximum value is with respect to SW1.
4. The absolute maximum value is with respect to SW2.
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Pin list
Table 2
Automotive 40-QFN package pinout (continued)
Absolute
Absolute
Sl# Pin name
minimum
(V)
Description
maximum (V)
Positive input of output current sensing amplifier. Connect to positive
terminal of the output current sense resistor.
15
16
CSPO
CC2
-0.3
24
Type-C connector configuration channel 2. Connect directly to the CC2
pin on the port’s Type-C connector. Also connect a 390-pF capacitor to
ground.
-0.5
24
24
Type-C connector configuration channel 1. Connect directly to the CC1
pin on the port’s Type-C connector. Also connect a 390-pF capacitor to
ground.
17
CC1
-0.5
-0.5
USB D+/GPIO: D+ for implementing BC 1.2, AFC, QC or Apple charging.
EZ-PD™ CCG7S does not support USB data transmission on this pin.
[1]
18 DP_GPIO0
19 DM_GPIO1
PVDD+0.5
USB D-/GPIO: D- for implementing BC 1.2, AFC, QC or Apple charging.
EZ-PD™ CCG7S does not support USB data transmission on this pin.
[1]
-0.5
–
PVDD+0.5
20
VDDD
6
5-V LDO output. Connect a 1-μF ceramic bypass capacitor to this pin.
GPIO/ positive input terminal of VBAT – GND protection circuit.
Connect to the positive terminal of the VBAT – GND short protection
current sense resistor.
[1]
21 CSP_GPIO2
-0.5
PVDD+0.5
GPIO/negative input terminal of VBAT – GND protection circuit/hot plug
detect.
Connect to the negative terminal of the VBAT – GND short protection
current sense resistor. For single-ended current sensing, this pin need
not be connected to the current sense resistor. For applications
supporting DisplayPort (for example, Rear seat entertainment (RSE)),
this is the Hotplug Detect output pin.
[1]
22 CSN_GPIO3
-0.5
PVDD+0.5
[1]
23
24
25
26
27
28
29
30
31
32
33
34
35
GPIO4
CGND
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
XRES
-0.5
-0.3
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
–
PVDD+0.5
GPIO/VBAT to GND protection FET gate drive.
0.5
CC block ground. Connect to the exposed pad (EPAD).
[1]
PVDD+0.5
GPIO
[1]
PVDD+0.5
GPIO
[1]
PVDD+0.5
GPIO
[1]
PVDD+0.5
GPIO/SWD programming and debug data signal.
[1]
PVDD+0.5
GPIO/SWD programming and debug clock signal.
[1]
PVDD+0.5
GPIO
[1]
PVDD+0.5
External reset – active low. Contains a 3.5-KΩ to 8.5-KΩ internal pull-up.
[1]
GPIO11
GPIO12
GND
PVDD+0.5
GPIO
[1]
PVDD+0.5
GPIO
–
6
Chip ground. Connect to the exposed pad (EPAD).
5-V LDO output. Connect a 10-μF bypass capacitor to this pin.
VDDD
–
1.8-V core LDO output. Connect a 0.1-μF bypass capacitor to ground. Do
36
37
VCCD
VIN
–
–
not connect anything else to this pin.
4V–24V input supply. Connect a ceramic bypass capacitor to GND close
to this pin.
-0.3
40
Positive input of input current sense amplifier. Connect to the positive
terminal of the input current sense resistor. Use a dedicated (Kelvin)
connection.
38
CSPI
-0.3
40
Notes
1. Maximum voltage must not exceed 6 V.
2. Maximum absolute voltage w.r.t GND must not exceed 40 V.
3. The absolute maximum value is with respect to SW1.
4. The absolute maximum value is with respect to SW2.
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Pin list
Table 2
Automotive 40-QFN package pinout (continued)
Absolute
Absolute
Sl# Pin name
minimum
(V)
Description
maximum (V)
Negative input of Input current sense amplifier.
Connect to the negative terminal of the input current sense resistor. Use
a dedicated (Kelvin) connection.
39
40
CSNI
-0.3
40
Boosted power supply of the buck high side gate driver. Bootstrap
capacitor node.
[1, 2, 3]
BST1
EPAD
–
–
PVDD+0.5
Connect Schottky diode from VDDD to BST1. Also, connect a bootstrap
capacitor from this pin to SW1.
–
–
Exposed ground pad. Connect directly to pin 36 and pin 22.
Notes
1. Maximum voltage must not exceed 6 V.
2. Maximum absolute voltage w.r.t GND must not exceed 40 V.
3. The absolute maximum value is with respect to SW1.
4. The absolute maximum value is with respect to SW2.
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
GPIO10
GPIO9
GPIO8
HG1
SW1
LG1
PGND
PVDD
LG2
VOUT
SW2
GPIO7
GPIO6
GPIO5
EPAD
CGND
GPIO4
CSN_GPIO3
CSP_GPIO2
HG2
BST2
Figure 9
EZ-PD™ CCG7S 40-QFN pinout
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buck-boost controller
EZ-PD™ CCG7S programming and bootloading
4
EZ-PD™ CCG7S programming and bootloading
There are two ways to program application firmware into a EZ-PD™ CCG7S device:
1. Programming the device flash over SWD Interface
2. Application firmware update over specific interfaces (CC, I2C)
Generally, the EZ-PD™ CCG7S devices are programmed over SWD interface only during development or during
the manufacturing process of the end-product. Once the end-product is manufactured, the EZ-PD™ CCG7S
device's application firmware can be updated via the appropriate bootloader interface. By default, the EZ-PD™
CCG7S devices ship with a combined I2C/CC bootloader. Infineon® strongly recommends customers to use the
EZ-PD™ configuration utility to turn off the application FW update over CC or I2C interface in the firmware that
is updated into EZ-PD™ CCG7S's flash before mass production. This prevents unauthorized firmware from being
updated over CC interface in the field. If you desire to retain the application firmware update over CC/ I2C inter-
faces feature post-production for on-field firmware updates, contact Infineon Sales for further guidelines.
4.1
Programming the device flash over SWD interface
The EZ-PD™ CCG7S family of devices can be programmed using the SWD interface. Infineon® provides
programming hardware called CY8CKIT-005 MiniProg4 kit, which can be used to program the flash as well as
debug firmware. The flash is programmed by downloading the information from a hex file.
As shown in the block diagram (see Figure 10), the SWD_DAT and SWD_CLK pins are connected to the host
programmer’s SWDIO (data) and SWDCLK (clock) pins respectively. During SWD programming, the device can be
powered by the host programmer by connecting its VTARG (power supply to the target device) to VDDD pins of
EZ-PD™ CCG7S device. If the EZ-PD™ CCG7S device is powered using an on-board power supply, it can be
programmed using the “reset programming” option. For more details, refer the CCGx (CYPDxxxx) programming
specifications.
3.3 V
VDD
Host Programmer
VTARG
VDDD
VDDD
10µF
1µF
0.1µF
0.1µF
SWDCLK
SWDIO
XRES
SWD_CLK
SWD_DAT
XRES
VCCD
0.1µF
GND
GND
GND
Figure 10
Connecting the programmer to CYPD7XXX device
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Applications
5
Applications
Figure 11 shows a typical head unit charger application block diagram using the EZ-PD™ CCG7S device. A head
unit charger (also known as center stack) is located prominently in the center of the dashboard or console. They
are powered by the car battery and are used for charging the mobile/tablet and for media transfer using USB data
communications. In this application, EZ-PD™ CCG7S is always in DFP role supporting the charging of the device.
It negotiates the power with the connected device and uses the integrated buck-boost controller to supply the
required voltage and current.
The DP/DM lines of the Type-C receptacles are connected to the host processor/hub, for data connectivity to the
head unit. These pins are also connected to EZ-PD™ CCG7S to support legacy charging protocol BC v1.2 CDP. The
I2C interface is used to interface with the host processor/hub, to support host processor interface (HPI)
commands, provide status to the head unit, and support FW updates. Note that per the battery charging specifi-
cation 1.2, other legacy charging protocols other than BC v1.2 CDP cannot be supported in conjunction with USB
data communication.
EZ-PD™ CCG7S measures various temperatures using external NTC thermistors. EZ-PD™ CCG7S throttles the
output power based on temperature and/or shuts off the power under critical conditions. It also monitors the
battery voltage and lowers the output power if the battery voltage is lower than the user-configured threshold.
When no load is connected to the USB Type-C port, EZ-PD™ CCG7S remains in standby mode without switching
on the buck-boost controller.
(USB PD, 3.3-21 V,
5A)
Battery input
(9 V-18 V)
5 m
5 m
VIN
VBUS
VDDD
VDDD
0.1 μF
1
40
2
3
6
10
8
9
7
15
HG1
VOUT
CSPO
14
11
13
17
CSNO
39
CSNI
38
37
VBUS_CTRL
VBUS_C
CC1
CSPI
VIN
36
CC1
VCCD
0.1 μF
390-pF
390-pF
16
18
CC2
CC2
VDDD
NTC
DP
DP_GPIO0
22
CSN_GPIO3
DM
19
23
21
DM_GPIO1
GPIO4
CYPD7191-40LDXS
25
26
27
GPIO5
GPIO6
GPIO7
CE
GND
CSP_GPIO2
5 m
41
24
GND (EPAD)
CGND
20
35
VDDD
VDDD
VDDD
0.1 μF
10 μF
1
2
VDDD
AGND
34
0.1 μF
1 μF
GND
31
28
29
3
XRES
XRES
GPIO8
GPIO9
HPI_CLK
HPI_DAT
SWD_CLK
SWD_DAT
4
5
PVDD PGND
COMP
12
GPIO12 GPIO11 GPIO10
HPI_CLK
HPI_DAT
Programming header
– not needed for final
production
5
4
33
32
30
HPI_INT
VDDD
Host procesor
1μF
HPI_ADDR
Figure 11
EZ-PD™ CCG7S head unit (HU) charger application diagram
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Applications
Table 3 provides the head unit GPIO pin mapping for the application diagram in Figure 11.
Table 3
Pin #
Head unit (HU) GPIO pin mapping
Pin name
GPIO
HU
Function
18
19
DP_GPIO0 USB DP of Type-C port. Supports BC 1.2, QC, Apple charging and AFC
P0.0
DP
DM_GPIO1 USB DM of Type-C port. Supports BC 1.2, QC, Apple charging and AFC
P0.1
DM
CSP pin on ground side to implement VBAT to GND short circuit
21
22
CSP_GPIO2
protection
P0.2
P0.3
VBATT_CSP
NTC
CSN_GPIO3 Thermistor
23
GPIO4
GPIO to control the FET for VBAT to GND short circuit protection
P0.5
VBATT_FET
25
26
27
GPIO5
GPIO6
GPIO7
Free GPIO
P1.4
P1.3
P1.2
GPIO
CE
Chip enable from external hardware
Free GPIO
GPIO
Connect to the host programmer’s SWDCLK (clock) for programming the
EZ-PD™ CCG7S device. This pin is also connected to the HPI CLK pin of
the external host processor.
28
GPIO8
P1.1
HPI_SCL
Connect to the host programmer’s SWDIO (data) for programming the
EZ-PD™ CCG7S device. This pin is also connected to the HPI DATA pin of
the external host processor.
29
30
GPIO9
P1.0
P2.2
HPI_SDA
HPI_INT
GPIO10
HPI interrupt
32
33
GPIO11
GPIO12
Free GPIO
P3.0
P3.1
GPIO
HPI address detection pin
HPI_ADDR
Datasheet
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buck-boost controller
Applications
Figure 12 shows a typical rear seat charger (RSC) application block diagram using EZ-PD™ CCG7S device. This
application is similar to the head unit charger application without the hub and data communications. There is no
host processor/hub in this application. This application can be configured to support the legacy charging
protocols - BC1.2 DCP, Qualcomm QC2.0/3.0, Apple charging, and Samsung AFC.
See Figure 14 for an example of an RSC application in which only step-down (buck) conversion is required. The
boost side FETs are removed and the boost side pins are terminated as required.
(USB PD, 3.3-21 V, 5 A)
5 m
5 m
Battery input
(9 V-18 V)
VIN
VBUS
VDDD
VDDD
0.1 μF
40
2
3
6
10
8
9
7
15
1
HG1
14
11
13
17
CSNO
39
CSNI
38
37
VBUS_CTRL
VBUS_C
CC1
CSPI
VIN
36
CC1
VCCD
0.1 μF
390 pF
390 pF
16
18
CC2
CC2
VDDD
NTC
DP
DP_GPIO0
22
CSN_GPIO3
DM
19
23
21
DM_GPIO1
GPIO4
CYPD7191-40LDXS
LIN_TXR_EN
LIN_RX
25
26
27
GPIO5
GPIO6
GPIO7
LIN
transceiver
GND
CSP_GPIO2
LIN_TX
5 m
41
24
GND (EPAD)
CGND
20
35
VDDD
VDDD
VDDD
0.1 μF
10 μF
1
2
VDDD
AGND
34
0.1 μF
1 μF
GND
31
28
29
3
XRES
XRES
GPIO8
GPIO9
HPI_CLK
HPI_DAT
SWD_CLK
SWD_DAT
4
5
PVDD PGND
COMP
12
GPIO12 GPIO11 GPIO10
33 32 30
Programming header
– not needed for final
production
5
4
VDDD
HPI_INT
1 μF
I2CM_SCL
Figure 12
EZ-PD™ CCG7S rear seat charger (RSC) application diagram
Datasheet
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EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Applications
Table 4 provides the RSC GPIO pin mapping for the application diagram in Figure 12 and Figure 14.
Table 4
Pin #
Rear seat charger (RSC) GPIO pin mapping
Pin name
GPIO
RSC
Function
USB DP of Type-C port. Supports BC 1.2, QC, Apple charging
and AFC
18
19
DP_GPIO0
DM_GPIO1
P0.0
DP
USB DM of Type-C port. Supports BC 1.2, QC, Apple charging
and AFC
P0.1
DM
CSP pin on ground side to implement VBAT to GND short
circuit protection
21
22
23
CSP_GPIO2
CSN_GPIO3
GPIO4
P0.2
P0.3
P0.5
VBATT_CSP
NTC
Thermistor
GPIO to control the FET for VBAT to GND short circuit
protection
VBATT_FET
25
26
27
GPIO5
GPIO6
GPIO7
LIN trans receiver enable
LIN RX pin
P1.4
P1.3
P1.2
LIN_TXR_EN
LIN_RX
LIN TX pin
LIN_TX
Connect to the host programmer’s SWDCLK (clock) for
programming the EZ-PD™ CCG7S device. This is also the HPI
slave SCL pin for implementing load sharing between two
EZ-PD™ CCG7S devices.
Connect to the host programmer’s SWDDAT (data) for
programming the EZ-PD™ CCG7S device. This is also the HPI
slave SDA pin for implementing load sharing between two
EZ-PD™ CCG7S devices.
28
29
GPIO8
GPIO9
P1.1
P1.0
HPI_SCL
HPI_SDA
30
32
GPIO10
GPIO11
HPI interrupt
P2.2
P3.0
HPI_INT
Master I2C SDA for implementing load sharing between two
EZ-PD™ CCG7S devices
I2CM_SDA
Master I2C SCL for implementing load sharing between two
EZ-PD™ CCG7S devices
33
GPIO12
P3.1
I2CM_SCL
Figure 13 shows the connections required for implementing load sharing between the two EZ-PD™ CCG7S
devices for the RSC application.
VDDD
28
29
28
29
GPIO8
GPIO9
GPIO8
GPIO9
CYPD7191-40LDXS
CYPD7191-40LDXS
(Slave)
(Master)
30
32
33
HPI_INT
HPI_DAT
30
32
33
GPIO10
GPIO11
GPIO10
GPIO11
GPIO12
HPI_CLK
GPIO12
Figure 13
Load sharing between two EZ-PD™ CCG7S devices
Datasheet
24
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Applications
(USB PD, 3.3-21 V, 5 A)
VBUS
Battery input
(9 V-18 V)
5 m
5 m
VIN
VDDD
VDDD
10
0.1 μF
40
2
3
8
7
15
1
14
11
13
17
CSNO
39
CSNI
38
37
VBUS_CTRL
VBUS_C
CSPI
VIN
36
CC1
CC2
CC1
CC2
VCCD
0.1 μF
390 pF
390 pF
16
18
VDDD
NTC
DP
DP_GPIO0
22
CSN_GPIO3
DM
19
23
21
DM_GPIO1
GPIO4
CYPD7191-40LDXS
LIN_TXR_EN
LIN_RX
25
26
27
GPIO5
GPIO6
GPIO7
LIN
transceiver
GND
CSP_GPIO2
LIN_TX
5 m
41
24
GND (EPAD)
CGND
20
35
VDDD
VDDD
VDDD
0.1μF
10 μF
1
2
VDDD
AGND
34
0.1μF
1 μF
GND
31
28
29
3
XRES
XRES
GPIO8
GPIO9
HPI_CLK
HPI_DAT
SWD_CLK
SWD_DAT
4
5
PVDD PGND
COMP
12
GPIO12 GPIO11 GPIO10
33 32 30
Programming header
– not needed for final
production
5
4
VDDD
HPI_INT
1 μF
I2CM_SCL
Figure 14
EZ-PD™ CCG7S rear seat charger (RSC) application diagram - Step-down (buck) conversion
only
Datasheet
25
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Applications
Figure 15 shows the rear seat entertainment (RSE) application block diagram using EZ-PD™ CCG7S. In this appli-
cation, the port is used for charging and streaming video content from a DisplayPort source (for example, a
mobile phone, PC, or a tablet) to a monitor. EZ-PD™ CCG7S supports DisplayPort Alternate mode as a sink and
controls the external DisplayPort Multiplexer through I2C. EZ-PD™ CCG7S also communicates with the system’s
SoC over I2C.
(USB PD, 3.3-21 V, 5 A)
5 m
5 m
Battery Input
(9V-18V)
VIN
VBUS
VDDD
VDDD
0.1 μF
40
2
3
6
10
8
9
7
15
1
HG1
VOUT
CSPO
14
11
13
17
CSNO
39
CSNI
38
37
VBUS_CTRL
VBUS_C
CC1
CSPI
VIN
36
CC1
VCCD
0.1 μF
390 pF
390 pF
16
18
CC2
CC2
22
HPD
CSN_GPIO3
DM_GPIO1
VDDD
NTC
DP
DP_GPIO0
19
25
DM
CYPD7191-40LDXS
LIN_TXR_EN
23
21
GPIO5
GPIO6
GPIO7
GPIO4
LIN
transceiver
LIN_RX
LIN_TX
26
27
GND
CSP_GPIO2
5 m
41
24
GND (EPAD)
CGND
20
35
VDDD
VDDD
VDDD
0.1 μF
10 μF
1
2
VDDD
AGND
34
0.1 μF
1 μF
GND
31
28
29
3
XRES
XRES
GPIO8
GPIO9
HPI_CLK
HPI_DAT
SWD_CLK
SWD_DAT
4
5
PVDD PGND
COMP
12
GPIO12 GPIO11 GPIO10
HPI_CLK
HPI_DAT
Programming header
– not needed for final
production
5
4
33
32
30
HPI_INT
VDDD
Host procesor
1 μF
Display port
Mux
Figure 15
EZ-PD™ CCG7S rear seat entertainment (RSE) application diagram
Datasheet
26
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Applications
Table 5 provides the RSE GPIO pin mapping for the application diagram in Figure 15.
Table 5
Pin #
18
Rear seat entertainment (RSE) GPIO pin mapping
Pin name
GPIO
P0.0
P0.1
RSE
GPIO
NTC
Function
Free GPIO
Thermistor
DP_GPIO0
DM_GPIO1
19
CSP pin on ground side to implement VBAT to GND short
circuit protection
21
22
23
CSP_GPIO2
CSN_GPIO3
GPIO4
P0.2
P0.3
P0.5
VBATT_CSP
HPD
Hot Plug Detect
GPIO to disable the FET for VBAT to GND short circuit
protection
VBATT_FET
25
26
27
GPIO5
GPIO6
GPIO7
LIN transceiver enable
LIN RX pin
P1.4
P1.3
P1.2
LIN_TXR_EN
LIN_RX
LIN TX pin
LIN_TX
Connect to the host programmer’s SWDCLK (clock) for
programming the EZ-PD™ CCG7S
28
29
GPIO8
GPIO9
P1.1
P1.0
HPI_SCL
HPI_SDA
Connect to the host programmer’s SWDIO (data) for
programming the EZ-PD™ CCG7S
30
32
33
GPIO10
GPIO11
GPIO12
HPI Interrupt
P2.2
P3.0
P3.1
HPI_INT
I2CM_SDA
I2CM_SCL
Master I2C SDA to control the display port mux
Master I2C SCL to control the display port mux
Datasheet
27
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6
Electrical specifications
6.1
Table 6
Absolute maximum ratings
Absolute maximum ratings[5]
Parameter
Description
Maximum input supply voltage
Min Typ
Max
40
6
Unit Details/conditions
V
–
–
–
–
–
–
–
–
–
–
–
–
–
IN_MAX
V
Maximum supply voltage relative to V
Maximum supply voltage relative to V
DDD_MAX
SS
V
–
6
5V_MAX
SS
V
Max V
(P0/P1) voltage relative to Vss
BUS_C
–
24
24
V
–
–
–
–
–
BUS_C_MAX
CC_PIN_ABS
V
Max voltage on CC1 and CC2 pins
Inputs to GPIO
–
V
–0.5
–0.5
–25
V
+ 0.5
GPIO_ABS
DDD
V
OVT GPIO voltage
6
GPIO_OVT_ABS
I
Maximum current per GPIO
25
GPIO_ABS
mA
V
GPIO injection current, max for V > V
,
DDD
Absolute max,
IH
I
–0.5
–
–
–
0.5
–
GPIO_INJECTION
and min for V < V
current injected per pin
IL
SS
ESD_HBM
Electrostatic discharge human body model 2000
All pins.
Electrostatic discharge charged device
Charged device model
ESD
ESD_CDM
LU
500
–
model
Pin current for latch-up
Junction temperature
–100
–40
–
–
100
125
mA
°C
–
–
T
J
Note
5. Usage above the absolute maximum conditions listed in Table 6 may cause permanent damage to the device. Exposure
to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage tem-
perature is 150°C in compliance with JEDEC Standard JESD22-A103, high temperature storage life. When used below
absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Datasheet
28
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.2
Device-level specifications
All specifications are valid for –40°C ≤ TA ≤ 105°C and TJ ≤ 125°C, except where noted. Specifications are valid for
3.0 V to 5.5 V except where noted.
6.2.1
DC specifications
Table 7
DC Specifications (Operating conditions)
Spec ID
Parameter
Description
Min
Typ Max Unit Details/conditions
SID.PWR#1
V
Input supply voltage
4.0
–
24
–
IN
Buck-boost operating
input supply voltage
SID.PWR#1A
V
4.5
–
24
–
IN_BB
VDDD output with
VIN 5.5 V to 24 V,
max load = 75 mA
SID.PWR#2
V
4.6
–
5.5
5.5
–
–
DDD_REG
VDDD output with
VIN 4.5 V to 5.5 V,
max load = 75 mA
V
SID.PWR#2A
V
V -0.7
IN
DDD_BYPASS
VDDD output with VIN 4 V to
4.5 V, max load = 20mA
SID.PWR#3
SID.PWR#20
SID.PWR#5
V
V - 0.2
–
–
–
21.5
–
–
–
–
DDD_MIN
IN
VBUS
VBUS_C valid range
3.3
–
Regulated output voltage
(for core Logic)
V
1.8
CCD
External regulator voltage
bypass for VCCD
SID.PWR#16
SID.PWR#17
SID.PWR#18
C
80
–
100
10
120
–
nF
µF
EFC_VCCD
EXC_VDDD
Power supply decoupling
C
X5R ceramic
capacitor for V
DDD
Bootstrap supply capacitor
(BST1, BST2)
C
–
0.1
–
EXV
T = 25 °C, VIN = 12 V. CC IO IN
A
transmit or receive, no I/O
sourcing current, No VCONN
Supply current at 0.4 MHz
switching frequency
SID.PWR#24
I
–
50
–
mA load current, CPU at 24 MHz,
PD port active. Buck-boost
converter on, 3-nF gate driver
capacitance.
DD_ACT
Deep Sleep mode
Type-C not attached, CC
enabled for wakeup. R
p
V
= 12 V. CC wakeup on,
IN
connection should be enabled
SID_DS1
I
I
Type-C not connected,
Source mode
–
–
80
50
–
–
DD_DS1
DD_DS2
for the PD port. T = 25°C. All
A
faults disabled including
VBAT-GND short protection.
USBPD disabled. Wake-up
SID_DS2
SID_DS3
VIN = 12 V, GPIO wake-up
from GPIO.T = 25 °C. All faults
A
µA
disabled.
Type-C not attached, CC
enabled for wakeup. R
p
VIN = 12 V. CC wakeup on,
Type-C not connected,
Source mode
connection should be enabled
for the PD port.
I
–
300
–
DD_DS3
T = 25°C. All faults disabled
A
except VBAT-GND short
protection.
Datasheet
29
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.2.2
CPU
Table 8
CPU specifications
Spec ID
Parameter
Min
Typ Max Unit
Details/conditions
Description
–40°C ≤ T ≤ +105°C,
A
SID.CLK#4
F
CPU input frequency
–
–
48
MHz
CPU
all V
DDD
SID.PWR#19
SYS.XRES#5
T
Wake-up from Deep Sleep mode
External reset pulse width
–
5
35
–
–
–
DEEPSLEEP
µs
–
T
XRES
6.2.3
GPIO
Table 9
GPIO DC specifications
Spec ID
Parameter
Min
Typ
–
Max
Unit
Description
Details/conditions
SID.GIO#9
SID.GIO#10
SID.GIO#11
SID.GIO#12
V
Input voltage high threshold
Input voltage low threshold
LVTTL input
0.7 × V
–
0.3 × V
–
IH_CMOS
DDD
CMOS input
V
–
2.0
–
–
IL_CMOS
DDD
V
–
–40°C ≤ TA ≤ +105°C
–40°C ≤ TA ≤ +105°C
IH_TTL
V
LVTTL input
–
0.8
V
IL_TTL
I
= –4 mA,
OH
SID.GIO#7
V
Output voltage high level
V
– 0.6
–
–
OH_3V
DDD
–40°C ≤ T ≤ +105°C
A
I
= 10 mA,
OL
SID.GIO#8
SID.GIO#2
SID.GIO#3
V
Output voltage low level
–
–
0.6
8.5
8.5
OL_3V
–40°C ≤ T ≤ +105°C
A
Rpu
Pull-up resistor when enabled
3.5
3.5
5.6
5.6
k –40°C ≤ T ≤ +105°C
A
Pull-down resistor when
enabled
Rpd
Input leakage current
(absolute value)
SID.GIO#4
SID.GIO#5
SID.GIO#6
I
–
–
–
–
3
2
22
7
nA +25 °C T , 3-V V
A DDD
IL
–40°C ≤ T ≤ +105°C,
A
C
Max pin capacitance
capacitance on DP, DM
pins
PIN_A
pF
–40°C ≤ T ≤ +105°C,
A
C
Max pin capacitance
–
PIN
all V , all other I/Os
DDD
Input hysteresis, LVTTL,
DDD
SID.GIO#13
SID.GIO#14
V
100
–
–
–
–
V
–
> 2.7 V
DDD
HYSTTL
V
> 2.7 V
mV
V
Input hysteresis CMOS
0.1 × V
DDD
HYSCMOS
Table 10
GPIO AC specifications
Spec ID
Parameter
Description
Min
Typ Max Unit Details/conditions
SID.GIO#16
SID.GIO#17
SID.GIO#18
SID.GIO#19
T
Rise time in fast strong mode
Fall time in fast strong mode
Rise time in slow strong mode
Fall time in slow strong mode
2
2
–
–
–
–
12
12
60
60
RISEF
FALLF
RISES
FALLS
T
T
T
ns
10
10
C
= 25 pF,
load
–40°C ≤ T ≤ +105°C
A
GPIO F ; 3.0 V V
5.5 V.
OUT
DDD
SID.GIO#20
SID.GIO#21
SID.GIO#22
F
F
–
–
–
–
–
–
16
7
GPIO_OUT1
Fast strong mode.
GPIO F ; 3.0 V V
5.5 V.
OUT
DDD
MHz
GPIO_OUT2
Slow strong mode.
GPIO input operating frequency;
3.0 V V 5.5 V.
F
16
–40°C ≤ T ≤ +105°C
A
GPIO_IN
DDD
Datasheet
30
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
Table 11
GPIO OVT DC specifications
Parameter
Details/
Spec ID
Description
Min
Typ Max Unit
conditions
Max / min current in
to any input or
GPIO_20VT latch up
current limits
SID.GPIO_20VT_GIO#4
GPIO_20VT_I_LU
-140
–
140 mA
8.5
output, pin-to-pin,
pin-to-supply
GPIO_20VT pull-up
resistor value
–40°C ≤ T ≤ +105°C,
A
SID.GPIO_20VT_GIO#5
SID.GPIO_20VT_GIO#6
GPIO_20VT_RPU
GPIO_20VT_RPD
3.5
3.5
–
–
all V
DDD
kΩ
GPIO_20VT
pull-down resistor
value
–40°C ≤ T ≤ +105°C,
A
8.5
all V
DDD
GPIO_20VT input
leakage current
(absolute value)
SID.GPIO_20VT_GIO#16
GPIO_20VT_IIL
–
–
2
nA +25°C T , 3-V V
A DDD
GPIO_20VT pin
capacitance
–40°C ≤ T ≤ +105°C,
A
SID.GPIO_20VT_GIO#17
SID.GPIO_20VT_GIO#33
SID.GPIO_20VT_GIO#36
GPIO_20VT_CPIN
GPIO_20VT_Voh
GPIO_20VT_Vol
–
–
–
–
–
–
–
10
–
pF
all V
DDD
GPIO_20VT output
voltage high level
VDDD-0.6
I
I
= -4 mA
= 8 mA
OH
GPIO_20VT output
voltage low level
–
2
0.6
–
OL
V
GPIO_20VT LVTTL
input
–40°C ≤ T ≤ +105°C,
A
SID.GPIO_20VT_GIO#41 GPIO_20VT_Vih_LVTTL
SID.GPIO_20VT_GIO#42 GPIO_20VT_Vil_LVTTL
SID.GPIO_20VT_GIO#43 GPIO_20VT_Vhysttl
all V
DDD
GPIO_20VT LVTTL
input
–40°C ≤ T ≤ +105°C,
A
–
0.8
–
all V
DDD
GPIO_20VT input
hysteresis LVTTL
–40°C ≤ T ≤ +105°C,
A
100
mV
all V
DDD
GPIO_20VT
V (GPIO_20VT pin) >
DDD
SID.GPIO_20VT_GIO#45 GPIO_20VT_ITOT_GPIO maximum total sink
pin current to ground
–
–
95 mA
V
Datasheet
31
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
Table 12
GPIO OVT AC specifications
Parameter
Details/
Spec ID
Description
Min Typ Max Unit
conditions
GPIO_20VT rise time in
fast strong mode
SID.GPIO_20VT_70
SID.GPIO_20VT_71
GPIO_20VT_TriseF
GPIO_20VT_TfallF
GPIO_20VT_TriseS
GPIO_20VT_TfallS
1
1
–
–
–
–
15
15
70
70
GPIO_20VT fall time in
fast strong mode
ns
GPIO_20VT rise time in
slow strong mode
SID.GPIO_20VT_GIO#46
SID.GPIO_20VT_GIO#47
10
10
All V
load
,
DDD
GPIO_20VT Fall time in
slow strong mode
C
= 25 pF
GPIO_20VT GPIO Fout;
SID.GPIO_20VT_GIO#48 GPIO_20VT_FGPIO_OUT1 3 V V
5.5 V. Fast
–
–
–
–
–
–
33
7
DDD
strong mode.
GPIO_20VT GPIO Fout;
SID.GPIO_20VT_GIO#50 GPIO_20VT_FGPIO_OUT3 3 VV 5.5V. Slow
MHz
DDD
strong mode.
GPIO_20VT GPIO input
SID.GPIO_20VT_GIO#52 GPIO_20VT_FGPIO_IN operating frequency;
8
All V
DDD
3 V V
5.5 V
DDD
Datasheet
32
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.2.4
XRES
Table 13
XRES DC specifications
Details/
Spec ID
Parameter Description
Min
Typ
Max
Unit
conditions
Input voltage high
SID.XRES#1
SID.XRES#2
SID.XRES#3
SID.XRES#4
V
0.7 × V
–
–
IH_XRES
DDD
threshold on XRES pin
V
CMOS input
Input voltage low
V
–
–
–
–
–
0.3 × V
IL_XRES
IN_XRES
HYSXRES
DDD
threshold on XRES pin
Input capacitance on
XRES pin
C
7
–
pF
–
–
Input voltage hysteresis
on XRES pin
V
0.05 × V
mV
DDD
6.3
Digital peripherals
The following specifications apply to the timer/counter/PWM peripherals in the timer mode.
6.3.1
Pulse width modulation (PWM) for GPIO pins
Table 14
PWM AC specifications
Spec ID
Parameter
Min Typ Max Unit
Description
Details/conditions
SID.TCPWM.1 TCPWM
Operating frequency
–
–
Fc
MHz Fc max = CLK_SYS
FREQ
Minimum possible width of
overflow, underflow, and CC
(Counter equals compare value)
outputs
SID.TCPWM.3
T
Output trigger pulse width 2/Fc
–
–
PWMEXT
ns
Minimum time between successive
counts
SID.TCPWM.4
SID.TCPWM.5
T
Resolution of counter
PWM resolution
1/Fc
1/Fc
–
–
–
–
CRES
Minimum pulse width of PWM
output
PWM
RES
6.3.2
Table 15
I2C
Fixed I2C AC specifications
Spec ID
Parameter
Min Typ Max Unit
Mbps –
Description
Bit rate
Details/conditions
SID153
F
–
–
1
I2C1
6.3.3
UART
Table 16
Fixed UART AC specifications
Spec ID
Parameter
Min Typ Max Unit
Mbps –
Description
Bit rate
Details/conditions
SID162
F
–
–
1
UART
Datasheet
33
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.3.4
SPI
Table 17
Fixed SPI AC specifications
Spec ID
Parameter
Min Typ Max Unit
MHz –
Description
SPI operating frequency
(master; 6X oversampling)
Details/conditions
SID166
F
–
–
8
SPI
Table 18
Spec ID
Fixed SPI master mode AC specifications
Parameter
Min Typ Max Unit
Description
Details/conditions
MOSI valid after SClock
driving edge
SID167
SID168
SID169
T
–
20
0
–
–
–
15
–
–
DMO
MISO valid before SClock
capturing edge
T
ns Full clock, late MISO sampling
Referred to slave capturing edge
DSI
Previous MOSI data hold
time
T
–
HMO
Table 19
Spec ID
Fixed SPI Slave Mode AC Specifications
Details/
Parameter
Min Typ
Max
Unit
Description
conditions
MOSI valid before Sclock capturing
edge
SID170
SID171
SID171A
T
40
–
–
–
–
–
48 + (3 × T
48
–
DMI
T
MISO valid after Sclock driving edge
)
T
–
= 1/F
CPU CPU
DSO
CPU
MISO valid after Sclock driving edge
in ext clk mode
ns
T
T
–
DSO_EXT
SID172
T
Previous MISO data hold time
SSEL valid to first SCK valid edge
0
–
–
–
–
–
–
HSO
SID172A
100
SSELSCK
6.3.5
Memory
Table 20
Flash AC specifications
Spec ID
Parameter
Description
Min Typ Max Unit Details/conditions
Row (block) write time (Erase and
program)
SID.MEM#2
SID.MEM#1
FLASH_WRITE
–
–
20
–40°C ≤ T ≤ +85°C,
A
all V
FLASH_ERASE Row erase time
–
–
–
–
–
–
–
–
15.5
7
DDD
ms
SID.MEM#5 FLASH_ROW_PGM Row program time after erase
SID178
SID180
T
Bulk erase time (32 KB)
35
BULKERASE
-
T
Total device program time
7.5
s
DEVPROG
25°C ≤ T ≤ 55°C,
A
SID.MEM#6
SID182
FLASH_
Flash write endurance
100k
20
–
–
–
–
–
–
cycles
ENPB
all V
DDD
Flash retention, T ≤ 55°C,
A
F
F
–
RET1
100K P/E cycles
years
Flash retention, T ≤ 85°C,
A
SID182A
10
–
RET2
10K P/E cycles
Datasheet
34
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.4
System resources
6.4.1
Power-on-reset (POR) with brown out
Table 21
Imprecise power-on reset (IPOR)
Spec ID
Parameter
Min Typ Max Unit
Description
Details/conditions
Power-on reset (POR) rising trip
voltage
SID185
SID186
V
V
0.80
0.70
–
–
1.50
1.4
RISEIPOR
FALLIPOR
–40°C ≤T ≤ +105°C,
A
V
all V
DDD
POR falling trip voltage
Table 22
Precise POR
Parameter
Spec ID
Min Typ Max Unit
Description
Details/conditions
Brown-out detect (BOD) trip
voltage in active/sleep modes
SID190
V
1.48
1.1
–
–
1.62
1.5
FALLPPOR
–40°C ≤T ≤ +105°C,
A
V
all V
DDD
BOD trip voltage in deep sleep
mode
SID192
V
FALLDPSLP
6.4.2
SWD interface
Table 23
SWD interface specifications
Details/
Spec ID
Parameter
F_SWDCLK1 3.0 V V
Min
Typ
Max Unit
Description
conditions
SID.SWD#1
SID.SWD#2
SID.SWD#3
SID.SWD#4
SID.SWD#5
5.5 V
–
–
–
–
–
–
14
MHz –
DDIO
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
0.25 × T
–
0.25 × T
–
0.50 × T
–
ns
–
–
1
6.4.3
Internal main oscillator
Table 24
IMO AC specifications
Spec ID
Parameter
Description
Min Typ Max Unit Details/conditions
Frequency variation at 48 MHz
(trimmed)
3.0 V ≤ V
< 5.5 V.
DDD
A
SID.CLK#13
F
–
–
±2
%
IMOTOL
–40°C ≤ T ≤ 105°C
SID226
T
IMO start-up time
IMO frequency
–
–
–
7
µs
STARTIMO
–40°C ≤ T ≤ +105°C,
A
all V
DDD
SID.CLK#1
F
24
48
MHz
IMO
6.4.4
Internal low-speed oscillator
Table 25
ILO AC specifications
Details/
Spec ID
Parameter
Min
Typ Max Unit
Description
conditions
SID234
SID238
T
ILO start-up time
ILO duty cycle
ILO frequency
–
–
2
ms
%
STARTILO1
–40°C ≤ T ≤ +105°C,
A
all V
DDD
T
40
20
50
40
60
80
ILODUTY
SID.CLK#5
F
kHz
–
ILO
Datasheet
35
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.4.5
PD
Table 26
PD DC specifications
Details/
Spec ID
Parameter
Description
Min
Typ Max Unit
conditions
SID.DC.cc_shvt.1
SID.DC.cc_shvt.2
SID.DC.cc_shvt.3
SID.DC.cc_shvt.4
vSwing
vSwing_low
zDriver
Transmitter output high voltage
Transmitter output low voltage
Transmitter output impedance
Receiver input impedance
1.05
–
–
–
–
1.2
0.075
75
–
V
–
–
–
33
10
W
zBmcRx
M
Source current for USB standard
advertisement
SID.DC.cc_shvt.5
SID.DC.cc_shvt.6
SID.DC.cc_shvt.7
Idac_std
Idac_1p5a
Idac_3a
64
–
–
–
96
–
–
–
Source current for 1.5A at 5V
advertisement
166
304
194
356
µA
Source current for 3A at 5V adver-
tisement
Pull down termination resistance
when acting as UFP (upstream
facing port)
SID.DC.cc_shvt.8
SID.DC.cc_shvt.10
Rd
4.59
–
5.61
–
k
CC impedance to ground when
disabled
zOPEN
108
–
–
–
–
CC voltages on DFP side-standard
USB
SID.DC.cc_shvt.11 DFP_default_0p2
0.15
0.25
SID.DC.cc_shvt.12
SID.DC.cc_shvt.13
SID.DC.cc_shvt.14
DFP_1.5A_0p4 CC voltages on DFP side-1.5A
0.35
0.75
2.45
–
–
–
0.45
0.85
2.75
–
–
–
DFP_3A_0p8
DFP_3A_2p6
CC voltages on DFP side-3A
CC voltages on DFP side-3A
V
CC voltages on UFP side-standard
USB
SID.DC.cc_shvt.15 UFP_default_0p66
0.61
–
0.7
–
SID.DC.cc_shvt.16 UFP_1.5A_1p23 CC voltages on UFP side-1.5A
1.16
0.3
10
–
–
–
–
1.31
0.6
–
–
–
–
SID.DC.cc_shvt.17
SID.DC.cc_shvt.18
SID.DC.cc_shvt.19
Vattach_ds
Rattach_ds
VTX_step
Deep sleep attach threshold
Deep sleep pull-up resistor
TX drive voltage step size
%
50
k
mV
80
120
6.4.6
Analog-to-digital converter
Table 27
ADC DC specifications
Spec ID
Parameter
Resolution ADC resolution
Min
Typ
Max
Unit
Description
Details/conditions
SID.ADC.1
–
8
–
Bits –
Reference voltage generated
from bandgap.
SID.ADC.2
SID.ADC.3
SID.ADC.4
SID.ADC.5
SID.ADC.6
INL
Integral non-linearity
Differential non-linearity
–1.5
–2.5
–1.5
–
–
1.5
Reference voltage generated
DNL
2.5
1.5
LSB
V
from V
.
DDD
Reference voltage generated
from bandgap.
Gain Error Gain error
–
Reference voltage generated
VREF_ADC1 Reference voltage of ADC V
VREF_ADC2 Reference voltage of ADC
–
V
DDDmax
DDDmin
from V
.
DDD
Reference voltage generated
from Deep sleep reference.
1.96
2.0
2.04
Datasheet
36
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.4.7
HS CSA
Table 28
HS CSA DC specifications
Details/
Spec ID
Parameter
Description
Min Typ Max Unit
conditions
SID.HSCSA.1
SID.HSCSA.2
SID.HSCSA.3
SID.HSCSA.4
Csa_Acc1
Csa_Acc2
Csa_Acc3
Csa_Acc4
CSA accuracy 5 mV < Vsense < 10 mV –15
CSA accuracy 10 mV < Vsense < 15 mV –10
CSA accuracy 15 mV < Vsense < 25 mV –5
–
–
–
–
15
10
5
CSA accuracy 25 mV < Vsense
–3
3
CSA SCP at 6A with 5-mΩ sense
SID.HSCSA.7
SID.HSCSA.8
SID.HSCSA.9
SID.HSCSA.10
Csa_SCP_Acc1
Csa_SCP_Acc2
Csa_OCP_1A
Csa_OCP_5A
–10
–
–
10
10
resistor
%
Active mode
CSA SCP at 10A with 5-mΩ sense
–10
resistor
CSA OCP at 1A with 5-mΩ sense
104 130 156
123 130 137
resistor
CSA OCP for 5A with 5-mΩ sense
resistor
Table 29
Spec ID
HS CSA AC specifications
Parameter
Min Typ Max Unit
Description
Details/conditions
Delay from SCP threshold trip to
external NFET power gate turn
off
SID.HSCSA.AC.1
SID.HSCSA.AC.2
T
–
–
3.5
8
–
–
1nF NFET gate
3nF NFET gate
SCP_GATE
µs
Delay from SCP threshold trip to
external NFET power gate turn
off
T
SCP_GATE_1
6.4.8
UV/OV
Table 30
UV/OV specifications
Spec ID
Parameter
Min Typ Max Unit
Description
Details/conditions
Overvoltage threshold Accuracy,
4 V to 11 V
SID.UVOV.1
SID.UVOV.2
SID.UVOV.3
SID.UVOV.4
SID.UVOV.5
VTHOV1
–3
–3.2
–4
–
–
–
–
–
3
3.2
4
Overvoltage threshold Accuracy,
11 V to 21.5 V
VTHOV2
VTHUV1
VTHUV2
VTHUV3
Undervoltage threshold
Accuracy, 3 V to 3.3 V
%
Active mode
Undervoltage threshold
Accuracy, 3.3 V to 4.0 V
–3.5
–3
3.5
3
Undervoltage threshold
Accuracy, 4.0 V to 21.5 V
Datasheet
37
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.4.9
VCONN switch
Table 31
VCONN switch DC specifications
Spec ID
Parameter
Min Typ Max Unit
Description
Details/conditions
VCONN output voltage with 20 mA
load current
DC.VCONN.1
DC.VCONN.2
DC.VCONN.3
VCONN_OUT
4.5
–
–
–
5.5
10
V
–
I
Connector side pin leakage current
µA
–
–
LEAK
VCONN overcurrent protection
threshold
I
22.5 30 42.5 mA
OCP
Table 32
VCONN switch AC specifications
Spec ID
Parameter
Min Typ Max Unit
Description
Details/conditions
AC.VCONN.1
AC.VCONN.2
T
VCONN switch turn-on time
VCONN switch turn-off time
–
–
–
–
600
10
–
–
ON
µs
T
OFF
6.4.10
Table 33
Spec ID
VBUS
VBUS discharge specifications
Parameter
Min Typ Max Unit
Details/conditions
Description
20-V NMOS ON resistance for
DS = 1
SID.VBUS.DISC.1
SID.VBUS.DISC.2
SID.VBUS.DISC.3
SID.VBUS.DISC.4
SID.VBUS.DISC.5
R1
500
250
125
62.5
31.25
–
–
–
–
–
–
–
2000
1000
500
250
125
10
20-V NMOS ON resistance for
DS = 2
R2
R4
20-V NMOS ON resistance for
DS = 4
Measured at 0.5 V.
20-V NMOS ON resistance for
DS = 8
R8
20-V NMOS ON resistance for
DS = 16
R16
Error percentage of final VBUS
value from setting
When VBUS is
SID.VBUS.DISC.6 Vbus_stop_error
%
discharged to 5 V.
6.4.11
Voltage regulation
Table 34
Voltage regulation DC specifications
Spec ID
Parameter
Min Typ Max Unit
Description
Details/conditions
SID.DC.VR.1
VOUT
CSNO output voltage range
3.3
–
21.5
V
–
CSNO voltage regulation
accuracy
SID.DC.VR.2
VR
–
±3
±5
%
–
–
VIN supply below which chip
will get reset
SID.DC.VR.3
VIN_UVLO
1.7
–
3.0
V
Table 35
Voltage regulator specifications
Spec ID
Parameter
Description
Total startup time for the
regulator supply outputs
Min Typ Max Unit Details/conditions
200 µs
SID.VREG.1
T
–
–
–
START
Datasheet
38
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.4.12
VBUS gate driver
Table 36
VBUS gate driver DC specifications
Details/
Spec ID
Parameter
Description
Min Typ Max Unit
conditions
Gate to source overdrive during ON
condition
SID.GD.1
GD_VGS
4.5
5
10
2
V
NFET driver is ON.
Applicable on
SID.GD.2
GD_RPD
GD_drv
Resistance when pull-down enabled
Programmable typical gate current
–
–
–
k VBUS_CTRL to turn
off external NFET.
SID.GD.5
Table 37
Spec ID
0.3
9.75 µA
–
VBUS gate Driver AC specifications
Details/
Parameter
Min Typ Max Unit
Description
conditions
VBUS_CTRL low to high (1V to VBUS + 1 V)
with 3 nF external capacitance
SID.GD.3
SID.GD.4
T
2
–
5
7
10
–
ms CSNO = 5 V
ON
VBUS_CTRL high to low (90% to 10%)
with 3 nF external capacitance
T
µs CSNO = 21.5 V
OFF
6.4.13
PWM controller
Table 38
Buck-boost PWM controller specifications
Details/
Spec ID
PWM.1
PWM.2
Parameter
Min Typ Max Unit
Description
conditions
F
Switching frequency
150
–
–
600 kHz –
SW
Spread spectrum frequency dithering
span
FSS
10
–
%
–
PWM.3
PWM.4
Ratio_buck_BB Buck to buck boost ratio
Ratio_boost_BB Boost to buck boost ratio
–
–
1.16
0.84
–
–
–
–
V/V
6.4.14
NFET gate driver
Table 39
Buck-boost NFET gate driver specifications
Details/
Spec ID
DR.1
Parameter
R_HS_PU
R_HS_PD
R_LS_PU
R_LS_PD
Min Typ Max Unit
Description
conditions
Top-side gate driver on-resistance-gate
pull-up
–
–
–
–
2
–
–
–
–
–
–
–
–
Top-side gate driver on-resistance-gate
pull-down
DR.2
1.5
2
Ω
Bottom-side gate driver on-resis-
tance-gate pull-up
DR.3
Bottom-side gate driver on-resis-
tance-gate pull-down
DR.4
1.5
DR.5
DR.6
DR.7
DR.8
DR.9
DR.10
Dead_HS
Dead_LS
Tr_HS
Dead time before high-side rising edge
Dead time before low-side rising edge
Top-side gate driver rise time
–
–
–
–
–
–
30
30
25
20
25
20
–
–
–
–
–
–
–
–
–
–
–
–
ns
Tf_HS
Top-side gate driver fall time
Tr_LS
Bottom-side gate driver rise time
Bottom-side gate driver fall time
Tf_LS
Datasheet
39
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Electrical specifications
6.4.15
LS-SCP
Table 40
LS-SCP DC specifications
Spec ID
SID.LSSCP.DC.1
Parameter
Min Typ Max Unit
Description
Short circuit current detect
@ 6A
Details/conditions
Using differential inputs
(CSP_GPIO2, CSN_GPIO3)
SCP_6A
5.4
4.5
9
6
6.6
7.5
11
Using single ended inputs
(CSP_GPIO2) and internal
ground
Short circuit current detect
@ 6A
SID.LSSCP.DC.1A SCP_6A_SE
6
A
Short circuit current detect
@10A
Using differential inputs
(CSP_GPIO2, CSN_GPIO3)
SID.LSSCP.DC.2
SCP_10A
10
Using single ended inputs
(CSP_GPIO2) and internal
ground
Short circuit current detect
@10A
SID.LSSCP.DC.2A SCP_10A_SE
7.5
10 12.5
6.4.16
Thermal
Table 41
Thermal specifications
Spec ID
SID.OTP.1
Parameter
Min Typ Max Unit
120 125 130 °C
Description
Thermal shutdown
Details/conditions
–
OTP
Datasheet
40
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Ordering information
7
Ordering information
Table 42 lists the EZ-PD™ CCG7S part numbers and features.
Table 42
EZ-PD™ CCG7S ordering information
Termination
Switching
frequency
MPN
Application
Role
Package type
resistor
CYPD7191-40LDXS
CYPD7191-40LDXST
Rear-seat and
DFP
R
150 kHz–600 kHz
40-pin QFN
P
head unit charger
(Power source only)
7.1
Ordering code definitions
CY
PD
XX
-
X
X
X
XX XX
X
X
T = Tape and reel (Optional)
Temperature grade: S = Automotive grade
Lead: X = Pb-free
Package type: LD = QFN wettable flank
Number of pins in the package
Application and feature combination designation
Number of Type-C ports: 1 = 1 Port
Product type: 7 = Seventh-generation product family
Marketing code: PD = Power delivery product family
Company ID: CY = CYPRESS (an Infineon Company)
Datasheet
41
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Packaging
8
Packaging
Table 43
Package characteristics
Parameter Description
Operating junction temperature
Conditions
–
Min
–40
–
Typ
25
–
Max
125
Unit
T
°C
J
T
T
Package
Package
15.45
4.4
JA
JC
JA
JC
–
°C/W
–
–
Table 44
Table 45
Solder reflow peak temperature
Maximum time within 5°C
of peak temperature
Package
Maximum peak temperature
40-QFN
260°C
30 seconds
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2
Package
MSL
40-QFN
MSL 3
Datasheet
42
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Packaging
8.1
Package diagrams
NOTES:
DIMENSIONS
SYMBOL
e
N
ND
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. N IS THE TOTAL NUMBER OF TERMINALS.
MIN.
0.30
NOM.
0.50 BSC
40
10
0.40
MAX.
0.50
3
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
L
b
D2
E2
D
0.18
4.50
4.50
0.25
4.60
4.60
0.30
4.70
4.70
4
5
6
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK
SLUG AS WELL AS THE TERMINALS.
6.00 BSC
E
A
A1
A3
R
6.00 BSC
7. PLEASE REFER TO WETTABLE FLANK DESIGN BETWEEN OPTION 1 AND
OPTION 2.
8. JEDEC SPECIFICATION NO. REF. : N/A.
-
-
-
0.60
0.05
0.00
0.152 REF
0.20 TYP
0.20 MIN
0.125
K
0.115
0.135
L1
002-33635 *A
Figure 16
40-QFN package outline
Datasheet
43
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Packaging
4.00 0.10
(Po)
0.30 0.05
(T)
2.00 0.10
(P2)
+0.10
-0.00
1.50
(Do)
12.00 0.10
(P1)
1.60 0.10(D1)
"A"
0.18
6.30 0.10
(Ao/BOTTOM)
R0.25
DETAIL "A" (5/1)
002-19972 **
Figure 17
Carrier Tape dimensions
Datasheet
44
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Acronyms
9
Acronyms
Table 46
Acronyms used in this document
Acronym
Description
ADC
AFC
Arm
analog-to-digital converter
Samsung adaptive fast charging
advanced RISC machine, a CPU architecture
central processing unit
CPU
CSA
current sense amplifier
DAC
digital-to-analog converter
forced continuous current/conduction mode
general-purpose input/output
high-side driver
FCCM
GPIO
HSDR
2
I C, or IIC
inter-integrated circuit, a communications protocol
current DAC
IDAC
I/O
input/output, see also GPIO
low-side driver
LSDR
MCU
OCP
OVP
microcontroller unit
overcurrent protection
overvoltage protection
PD
power delivery
POR
PSoC
PSM
PWM
RAM
SPI
power-on reset
programmable system-on-chip
pulse skipping mode
pulse-width modulator
random-access memory
serial peripheral interface, a communications protocol
static random access memory
timer/counter/PWM
SRAM
TCPWM
a new standard with a slimmer USB connector and a reversible cable, capable of sourcing up to 100 W of
power
Type-C
UART
UFP
UVP
USB
UVLO
VPA
universal asynchronous transmitter receiver, a communications protocol
upstream facing port
undervoltage protection
universal serial bus
under-voltage lockout
VCONN powered accessories
zero crossing detector
ZCD
Datasheet
45
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Document conventions
10
Document conventions
10.1
Units of measure
Table 47
Units of measure
Symbol
Unit of measure
°C
degrees Celsius
hertz
Hz
KB
kHz
k
Mbps
MHz
M
Msps
µA
1024 bytes
kilohertz
kilo ohm
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
microsecond
microvolt
µF
µs
µV
µW
mA
m
ms
mV
nA
microwatt
milliampere
milliohm
millisecond
millivolt
nanoampere
nanosecond
ohm
ns
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
sps
samples per second
Datasheet
46
002-33534 Rev. *F
2023-01-30
EZ-PD™ CCG7S Automotive single-port USB Type-C with PD and
buck-boost controller
Revision history
Revision history
Document
Date
Description of changes
revision
*F
2023-01-30
Post to external web.
Datasheet
47
002-33534 Rev. *F
2023-01-30
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contact your nearest Infineon Technologies office
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Edition 2023-01-30
Published by
Infineon Technologies AG
81726 Munich, Germany
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values stated herein and/or any information
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without limitation warranties of non-infringement of Technologies office.
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Document reference
002-33534 Rev. *F
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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