CYPD6125-40LQXI [INFINEON]
EZ-PD™ CCG6 One-Port USB-C & PD Controller;
| 型号： | CYPD6125-40LQXI |
| 厂家： | 
Infineon |
| 描述： | EZ-PD™ CCG6 One-Port USB-C & PD Controller 光电二极管 |
| 文件： | 总39页 (文件大小：784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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EZ-PD™ CCG6
USB Type-C Port Controller
General Description
EZ-PD™ CCG6 is a one-port USB Type-C controller that complies with the latest USB Type-C and PD specifications. CCG6 provides
a complete USB Type-C and USB-Power Delivery port control solution for PCs and notebooks. CCG6 includes a VBUS provider path
load switch controller, True Random Number Generator for authentication, a 32-bit, 48-MHz Arm® Cortex®-M0 processor with 128-KB
flash integrates a complete Type-C Transceiver including the Type-C termination resistors Rp, Rd, and dead battery Rd termination.
CCG6 is available in a 40-pin QFN package.
■ Gate Driver, tolerant to 24 V, to drive external VBUS PFET on
the consumer path
Applications
■ PCs and Notebooks
■ Configurable hardware-controlled VBUS overvoltage,
undervoltage, overcurrent, short circuit, and reverse current
protection
■ Thunderbolt hosts, non-Thunderbolt hosts and devices/docks
Features
■ VBUS high-side current sense amplifier capable of measuring
current across 5-m series resistance
USB-PD
■ In response to Fast Role Swap request, turns off consumer
PFET and turns on provider PFET
■ Supports latest USB PD 3.0 specification
■ Fast Role Swap (FRS)
■ Extended Data Messaging
LDO
■ Integrated high-voltage LDO operational up to 21.5 V for dead
battery mode operation
Type-C
■ Integrated current sources for DFP[1] role (Rp).
❐ Default current at 500 / 900 mA
❐ 1.5 A
❐ 3 A
■ Integrated Rd resistor for UFP[2] role
■ Integrated VCONN FETs to power EMCA cables
■ Integrated dead battery termination
32-bit MCU Subsystem
■ 48-MHz Arm Cortex-M0 CPU
■ 128-KB Flash
■ 12-KB SRAM
Integrated Digital Blocks
■ Two integrated timers and counters to meet response times
required by the USB-PD protocol
■ Four run-time serial communication blocks (SCBs) with
■ Integrated high-voltage protection on CC and SBU pins to
protectagainstaccidentalshortstotheVBUSpinontheType-C
connector
reconfigurable I2C, SPI, or UART functionality
Authentication
Legacy Charging (source and sink)
■ True Random Number Generator
■ BCv1.2
■ Apple
Clocks and Oscillators
■ Integrated oscillator eliminating the need for an external clock
Operating Range
■ VSYS (2.75 V–5.5 V)
■ VBUS (4 V–21.5 V)
Mux
■ Integrated USB2.0Analog Mux for USB 2.0 HS data and UART
data
■ Integrated SBU analog Mux for alternate modes (Display port
and Thunderbolt)
Hot-Swappable I/Os
■ I2C pins from SCB1 are hot-swappable
Integrated VBUS Load Switch Controller
Packages
■ Supports up to 20 V on VBUS Provider path
■ 6.0 mm 6.0 mm, 0.6 mm, 40-pin QFN
■ Supports industrial temperature range (–40 °C to +85 °C)
■ Slew rate controlled Gate Driver, tolerant to 24 V, to drive
external VBUS PFET on the provider path
Notes
1. DFP refers to power source.
2. UFP refers to power sink.
Cypress Semiconductor Corporation
Document Number: 002-23191 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 26, 2021
EZ-PD™ CCG6
Logic Block Diagram
CCG6: Single--Chip Type- C Controller
MCU Subsystem
I/O Subsystem
CC
Integrated Digital Blocks
2x TCPWM
ARM
CORTEX-M0
48 MHz
4x SCB
(I2 C, SPI, UART)
VCONN
17 GPIO
Pins
Authentication
Flash
(128KB)
True Random Number
Generator (TRNG)
SRAM
(12KB)
USB PD Subsystem
Baseband MAC
2x VCONN FETs
VCONN OCP
Protection
System
Resources
Baseband PHY
HV Protection
on CC & SBU
Hi-Voltage LDO
(21.5V)
SBU Analog
Mux Switch
Gate Driver
Consumer PFET
8-bit SAR ADC
USB Analog
HS Mux Switch
Load Switch Controller for Provider path
(UVP/OVP/SCP/RCP/OCP)
USB Charger
Detect Source and
Sink
Document Number: 002-23191 Rev. *G
Page 2 of 38
EZ-PD™ CCG6
CCG6 Functional Diagram
PFET Load Switch
CONSUMER PATH
TO
BATTERY
PFET Load Switch
5 mΩ
VBUS
FROM
BATTERY
PROVIDER PATH
VSYS
(2.75V-5.5V)
CSN
VBUS_C_CTRL
VBUS (4V-21.5V)
Discharge
CSP
VBUS_P_CTRL
VDDIO
(1.8V – 5.5V)
Load Switch Controller includes
1. OC, RC, SC, OV and UV Protection
2. Slew-Rate controlled gate driver
3. Fast Role Swap
LDO
Dynamic
Gate
Driver
VDDD
(2.75V-5.5V)
VCCD (1.8V)
VCONN
SWITCH
LDO
V5V (5V)
CC1
CC2
LSRX/GPIO14
LSTX/GPIO15
AUX_P
BMC
PHY
Reset
XRES
SCB (4x),
AMUX &
GPIO
ADC
GPIO1-13
SBU1
SBU2
AUX_N
MCU Subsystem
Cortex-M0
UART_RX/GPIO16
Flash (128KB)
SRAM (12 KB)
2x TCPWM
UART_TX/GPIO17
DP_SYS
DP1
DP2
DM1
DM_SYS
DM2
Charger Detect
VSS
Document Number: 002-23191 Rev. *G
Page 3 of 38
EZ-PD™ CCG6
Contents
Functional Overview ........................................................5
USB-PD Subsystem (SS) ............................................5
True Random Number Generator ...............................8
CPU and Memory Subsystem .....................................8
Power System Overview ..................................................9
Peripherals ................................................................10
Timer/Counter/PWM Block (TCPWM) .......................10
GPIO .........................................................................10
Pinouts ............................................................................11
Application Diagrams .....................................................15
Electrical Specifications ................................................16
Absolute Maximum Ratings .......................................16
Device-Level Specifications ......................................17
Digital Peripherals .....................................................20
System Resources ....................................................22
Ordering Information ......................................................32
Ordering Code Definitions .........................................32
Packaging ........................................................................33
Acronyms ........................................................................34
Document Conventions .................................................35
Units of Measure .......................................................35
References and Links to Applications Collateral .......36
Document History Page .................................................37
Sales, Solutions, and Legal Information ......................38
Worldwide Sales and Design Support .......................38
Products ....................................................................38
PSoC® Solutions ......................................................38
Cypress Developer Community .................................38
Technical Support .....................................................38
Document Number: 002-23191 Rev. *G
Page 4 of 38
EZ-PD™ CCG6
The Rd resistor is used to identify CCG6 as a Sink in a DRP
application. The dead battery Rd resistor on CC pins is required
when the part is not powered for dead battery termination
detection and charging.
Functional Overview
USB-PD Subsystem (SS)
USB-PD Physical Layer
To support the latest USB-PD 3.0 specification, CCG6 includes
Fast Role Swap (FRS). The FRS feature enables externally
powered docks and hubs to rapidly switch to bus power when
their external power supply is removed. CCG6 also supports
FRS detection in DeepSleep mode.
The CCG6 USB-PD subsystem, as shown in Figure 1, consists
of the USB-PD physical layer (PHY) block and supporting
circuits. The PHY consists of a transmitter and receiver that
communicates using BMC and 4b/5b encoded/decoded data
over the CC channel based on the PD 3.0 specification. All
communication is half-duplex. The PHY practices collision
avoidance to minimize communication errors on the channel.
For more details about FRS, refer to Section 6.3.17 in the
USB-PD 3.0 specification.
CCG6 is designed to be fully interoperable with revision 3.0 of
the USB Power Delivery specification as well as revision 2.0 of
the USB Power Delivery specification.
In addition, the CCG6 USB-PD block includes all termination
resistors (Rp and Rd) and their switches as required by the USB
Type-C specification. Rp and Rd resistors are required for
connection detection, plug orientation detection, and for
establishing the USB source/sink roles.
CCG6 supports Extended Messages containing data of up to
260 bytes. The Extended Messages will be larger than expected
by the USB-PD 2.0 hardware. To accommodate Revision 2.0
based systems, a Chunking mechanism is implemented such
that messages are limited to Revision 2.0 sizes unless it is
discovered that both systems support longer message lengths.
The integrated Rp resistor enables CCG6 to be configured as a
Source. The Rp resistor is implemented as a current source and
can be programmed to support the complete range of current
capacity on the VBUS defined in the USB Type-C Spec.
Figure 1. USB-PD Subsystem
To/From System Resources
vref
iref
To/ from AHB
From AMUX
8-bit ADC
VCONN FET Enable
TxRx Enable
V5V
VCONN
FETs
Digital Baseband PHY
Tx_data
Enable Logic
from AHB
Tx
SRAM
4b5b
Encoder
BMC
Encoder
SOP
Insert
Rp
TX
CC1
RD1
CC2
CRC
Rx_data
to AHB
RX
Rx
4b5b
SOP
BMC
SRAM
Decoder
Detect
Decoder
Ref
DB
Rd
Comp
RD2
Active
Rd
CC control
CC detect
Analog Baseband PHY
Deep Sleep Reference Enable
Functional, Wakeup Interrupts
Deep Sleep Vref &
Iref Gen
RD1 is shorted to CC1 and RD2 is shorted to CC2 for DRP applications using
bondwire. For source applications, RD1 and RD2 are not shorted to CC1 and
CC2. Dead Battery (DB) RD termination is removed after MCU boots up
vref, iref
Document Number: 002-23191 Rev. *G
Page 5 of 38
EZ-PD™ CCG6
VCONN FET
input of the comparator is from a 4-input multiplexer. The four
inputs of the multiplexer are a pair of global analog multiplex
busses, an internal bandgap voltage, and an internal voltage
proportional to the absolute temperature. All GPIOs on the chip
have access to the ADC through the chip-wide analog mux bus.
The CC1 and CC2 pins are not available to connect to the mux
bus.
CCG6 has a power supply input, V5V, for providing power to
EMCA cables through integrated VCONN FETs. There are two
VCONN FETs to power either CC1 or CC2 pins. These FETs can
provide 1.5-W power over VCONN on the CC1 and CC2 pins for
the active EMCA cables. CCG6 also includes overcurrent
protection (OCP) on VCONN.
SBU Mux
ADC
CCG6 integrates SBU 4x2 Mux that enables selection between
the Display Port or Thunderbolt alternate mode and Type-C
orientation as shown in Figure 2. Type-C facing SBU pins are
protected from accidental short to high-voltage VBUS.
The USB-PD subsystem contains one 8-bit successive
approximation register analog-to-digital converter (SAR ADC).
The ADC includes an 8-bit DAC and a comparator. The DAC
output forms the positive input of the comparator. The negative
Figure 2. CCG6 SBU Crossbar Switch Block Diagram
Flip
orientation
DP or TBT
LSTx
LSRx
SBU_1
SBU_2
24V
Protection
DP_AUX_P
DP_AUX_N
SBU Cross Bar Switch Internal Block Diagram
USB 2.0 Mux
To meet the HS eye diagram requirements with sufficient margin,
follow these guidelines:
The HS mux contains a 2 2 cross bar switch to route the system
DPLUS and DMINUS lines to the Type-C top or bottom port
based on the CC (Type-C plug) orientation. The unused DPLUS
and DMINUS top or bottom lines can be connected to a UART
(Debug) port. The maximum operating frequency of UART must
be 1 Mbps.
■ It is recommended to keep the total USB HS signal trace
lengths (USB 2.0 host to CCG6 + CCG6 to Type-C connector
pins) to 4 inches.
■ Total USB HS signal trace lengths can be increased up to 8
inches by adjusting the drive strength on the USB 2.0 host.
The USB 2.0 mux also contains charger detection/emulation for
detecting USB BC1.2 and Apple terminations. The charger
detection block is connected to the DPLUS and DMINUS from
the system as shown in Figure 3.
■ The differential impedance across the DPLUS/DMINUS signal
traces shall be 90 Ω.
■ Trace width shall be 6 mils.
■ Air Gap (distance between lines) shall be 8 mils.
Figure 3. CCG6 DPLUS/DMINUS Switch Block Diagram
Charger
Detect
2
2
2
2
2
DPLUS_SYS / DMINUS_SYS
DPLUS_TOP / DMINUS_TOP
DPLUS_BOT / DMINUS_BOT
2
UART_TX / UART_RX
VBUS Discharge
VBUS Regulator
CCG6 also has integrated VBUS discharge circuit. It is used to
discharge VBUS to meet the USB-PD specification timing on a
detach condition and negative voltage transition.
CCG6 can operate from two power supplies – VSYS and VBUS.
CCG6 integrates the regulator (that supports up to 21.5 V) to
derive operating supply voltage. The VSYS always takes priority
over VBUS. In the absence of VSYS, the regulator powers CCG6
from VBUS.
Document Number: 002-23191 Rev. *G
Page 6 of 38
EZ-PD™ CCG6
Gate Driver for VBUS PFET on Consumer Path
VBUS Load Switch Controller for Provider Path
CCG6 has an integrated PFET gate driver to drive external
PFETs on the VBUS consumer path. The gate driver can drive
only low or high-Z, thus requiring an external pull-up. This pin is
VBUS voltage-tolerant.
The load switch controller supports up to 20 V on the VBUS
Provider Path.
RCP
CCG6 integrates the Reverse Current Protection (RCP) circuitry
that has the capability of sensing reverse current that lasts for
more than 10 µs and protects the system by shutting down the
Gate automatically upon detection of such events.
Charger Detect
CCG6 integrates battery charger emulation and detection for
USB BC.1.2 and Apple charge.
CCG6 provides RCP circuitry that can detect reverse current
flow from connector VBUS_C to provider VBUS_P.
High-Voltage Tolerant SBU and CC Lines
The chip supports high-voltage tolerant SBU and CC lines. In the
case of SBU/CC short to VBUS through connectors, these lines
will be protected internally.
The RCP event is recognized whenever VBUS_C > VBUS_P
while provider FET is ON, causing current to flow from connector
VBUS to provider VBUS. After recognizing the RCP event, the
provider FET is shut down thus isolating the provider and
connector VBUS.
CCG6 has three distinct mechanisms to detect the reverse
current as shown in Figure 4.
Figure 4. RCP Mechanism
V
comp_rcp
V
csa_rcp
VBUS_P
VBUS to Type -C
Connector
Provider side
Regulator
VBUS_C
VBUS_P_CTRL
CSP
CSN
VBUS
RCP2
RCP1
RCP detect
comparator
(DC.RCP.45)
RCP detect
(DC.RCP.44)
RCP3
Vref
Vbux _max_det
(DC.RCP.46)
CCG6
■ Mechanism 1: A comparator senses the voltage drop across
external Rsense through pins CSP and CSN. This comparator
signals an RCP event whenever CSN > CSP by the Vcsa_rcp
voltage given in Table 36. The output of this comparator RCP1
is shown in Figure 4.
When any one of the three comparator outputs show an RCP
event, then the provider FET is turned OFF. The firmware has an
option to enable or disable the individual mechanism depending
on the application.
CSA
■ Mechanism 2: A comparator senses the voltage drop across
provider FET through CSN and VBUS pin of CCG6. This
comparator signals an RCP event whenever VBUS > CSN by
the Vcomp_rcp voltage given in Table 36. The output of this
comparator RCP2 is shown in Figure 4.
The CCG6 chip has an integrated high-side current sense
amplifier that is capable of detecting current in the order of
100 mA across a 5-mΩ external resistor in the provider path.
This is used to monitor the current load and detect system faults
such as OCP and SCP while sourcing VBUS to the Sink on the
Type C port so that the PD controller can shut down the Provider
FET to protect devices.
■ Mechanism 3: A comparator senses the 20% voltage of the
CSN pin and compares it against Vref = 1.15 V for 5-V provider
VBUS application. This comparator signals an RCP event
whenever CSN voltage goes above Vbus_max_det voltage
given in Table 36 for a 5-V application. The output of this
comparator RCP3 is shown in Figure 4. Note that Vref Is
programmable and the voltage divider has an option to use
10% or 20% value. For a higher voltage of the provider, the
VBUS device automatically adjusts this threshold.
Slew-Rate Controllable Gate Driver
CCG6 has a programmable slew-rate controllable Gate Driver,
which can help in limiting the in-rush currents during connect
events.
Document Number: 002-23191 Rev. *G
Page 7 of 38
EZ-PD™ CCG6
Overvoltage and Undervoltage Protection on VBUS
CPU and Memory Subsystem
CCG6 implements an undervoltage/overvoltage (UVOV)
detection circuit for the VBUS supply. The threshold for OV and
UV detection can be set independently. Both UV and OV
detectors have programmable thresholds and are controlled by
the firmware. The inputs to the OV comparator are a division (8%
or 10%) of VBUS supply voltage and a reference voltage. The
reference voltage is configurable in the range (200 mV to
2190 mV) in steps of 10 mV.
CPU
The Cortex-M0 CPU in EZ-PD CCG6 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating.
The CPU also includes a serial wire debug (SWD) interface,
which is a 2-wire form of JTAG. The debug configuration used for
EZ-PD CCG6 has four break-point (address) comparators and
two watchpoint (data) comparators.
The inputs to the UV comparator are a division (10% or 20%) of
VBUS supply voltage and a reference voltage. The reference
voltage is configurable in the range (200 mV to 2190 mV) in
steps of 10 mV.
Flash
The EZ-PD CCG6 device has a 128-KB flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The flash block is designed to
deliver two wait-states (WS) access time at 48 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash module can be used
to emulate EEPROM operation if required.
Overcurrent Protection on VBUS
CCG6 integrates a high-side current sense amplifier to detect
overcurrent on the VBUS. Overcurrent protection is sensed
using an external 5-m sense resistor connected between the
“CSP” and “CSN” pins. The OCP detector threshold is program-
mable and controlled by the firmware.
SROM
Asupervisory ROM that contains boot and configuration routines
is provided.
True Random Number Generator
In notebook designs, CCG6’s TRNG block is used to authen-
ticate connected devices such as Power Adapter or Dock that
include support for USB Type-C Authentication Specification
(USBTCAS). CCG6, within the notebook application, will
implement the initiator-role as defined in USBTCAS while the
connected device implements the responder-role. USBTCAS
provides a means for authenticating Type-C devices with regard
to identification and configuration.
SRAM
CCG6 supports 12-KB SRAM.
Document Number: 002-23191 Rev. *G
Page 8 of 38
EZ-PD™ CCG6
Power System Overview
Table 1. CCG6 Power Modes
Mode
Figure 5 provides an overview of the EZ-PD CCG6 power
system. CCG6 can operate from two possible external supply
sources: VBUS (4 V to 21.5 V) or VSYS (2.75 V to 5.5 V). The
VBUS supply is regulated inside the chip with a LDO. The
switched supply, VDDD, is used directly inside some analog
blocks and further regulated down to VCCD, which powers
majority of the core. CCG6 has two different power modes:
Active and Deep Sleep. Transitions between these power modes
are managed by the power system. A separate power domain,
VDDIO, is provided for the GPIOs. The VDDD and VCCD pins,
both outputs of regulators, are brought out for connecting a 1-µF
and 0.1-µF capacitor respectively for the regulator stability only.
The VCCD pin is not supported as a power supply. VDDD can
source 2 mA (max) for external load. In CCG6, VDDD shall be
shorted to VDDIO on PCB.
Description
RESET
Power is valid and XRES is not asserted. An
internal reset source is asserted or Sleep
Controller is sequencing the system out of reset.
ACTIVE
Power is valid and CPU is executing instructions.
DEEP SLEEP Main regulator and most blocks are shut off.
DeepSleep regulator powers logic, but only the
low-frequency clock is available.
Figure 5. EZ-PD CCG6 Power System
LDO
VDDD
VBUS
VSYS
CC1
CC2
V5V
Core Regulator
(SRSS-Lite)
VDDIO
VCCD
VSS
CC
Tx/Rx
GPIOs
Core
Document Number: 002-23191 Rev. *G
Page 9 of 38
EZ-PD™ CCG6
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(essentially adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block
can use the FIFO.
Peripherals
CCG6 has four SCBs, which can each implement an I2C, UART,
or SPI interface.
I2C Mode: The hardware I2C block implements
a full
Timer/Counter/PWM Block (TCPWM)
multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. The FIFO
mode is available in all channels and is very useful in the
absence of DMA.
The I2C peripheral is compatible with the I2C Standard-mode,
Fast-mode, and Fast-Mode Plus devices as defined in the NXP
I2C bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes. The I2C bus
uses open-drain drivers for clock and data with pull-up resistors
on the bus for clock and data connected to all nodes. The
required Rise and Fall times for different I2C speeds are
guaranteed by using appropriate pull-up resistor values
depending on VDDD, Bus Capacitance, and resistor tolerance.
CCG6 has two TCPWM blocks. Each TCPWM block consists of
four 16-bit counters with user-programmable period length.
There is a Capture register to record the count value at the time
of an event (which may be an I/O event), a period register which
is used to either stop or auto-reload the counter when its count
is equal to the period register, and compare registers to generate
compare value signals which are used as PWM duty cycle
outputs. The block also provides true and complementary
outputs with programmable offset between them to allow use as
deadband programmable complementary PWM outputs. It also
has a Kill input to force outputs to a predetermined state; for
example, this is used in motor drive systems when an
overcurrent state is indicated and the PWMs driving the FETs
need to be shut off immediately with no time for software
intervention.
For detailed information on how to calculate the optimum pull-up
resistor value for your design, refer to the UM10204 I2C bus
specification and user manual (the latest revision is available at
www.nxp.com).
CCG6 is not completely compliant with the I2C spec for the
following:
GPIO
CCG6 has 17 GPIOs that includes the SCB and SWD pins,
which can also be used as GPIOs. The I2C pins from only SCB
1 are overvoltage-tolerant. The GPIO block implements the
following:
■ Only SCB1 is overvoltage-tolerant. SCB2, SCB3, and SCB4
GPIO cells are not overvoltage-tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
■ Seven drive strength modes:
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
■ Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the Bus Load.
■ Input threshold select (CMOS or LVTTL)
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
One of the SCB (typically SCB1) blocks is used to implement the
Host Processor Interface (HPI) slave, which allows an external
MCU to control the firmware operation.
■ Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
The HPI I2C Slave address is configurable using the
I2C_CFG_EC pin as shown in the following table.
Table 2. I2C Slave Address Configuration
■ Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal
multiplexing complexity.
I2C_CFG_EC Configuration
Floating
I2C Slave
0x08
Pulled up with 1 k
Pulled down with 1 k
0x42
0x40
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (6 for CCG6 since it has
6 ports).
Document Number: 002-23191 Rev. *G
Page 10 of 38
EZ-PD™ CCG6
Pinouts
Table 3. Pinout for CYPD6125-40LQXIT and CYPD6137-40LQXIT
Group Name
Pin Name
Port
Pin
Description
USB Type-C
CC1
Analog
9
Connect to Type-C CC1 pin. Filter noise with 390-pF cap
to GND.
CC2
Analog
7
Connect to Type-C CC2 pin. Filter noise with 390-pF cap
to GND.
Mux
DPLUS_SYS
DMINUS_SYS
UART_TX/GPIO
Analog
Analog
P4.0
23
24
29
Connect to USB 2.0 DP from Host side.
Connect to USB 2.0 DM from Host side.
Connect to Debug port UART_TX (optional) from host
side or can be used as GPIO. If unused, leave floating.
UART_RX/GPIO
DPLUS_BOT
DMINUS_BOT
DMINUS_TOP
DPLUS_TOP
P4.1
30
26
25
27
28
Connect to Debug port UART_RX (optional) from host
side or can be used as GPIO. If unused, leave floating.
Analog
Analog
Analog
Analog
Connect to Type-C DP1 pin. Keep trace length less than
2".
Connect to Type-C DM1 pin. Keep trace length less than
2".
Connect to Type-C DM2 pin. Keep trace length less than
2".
Connect to Type-C DP2 pin. Keep trace length less than
2".
SBU2
SBU1
Analog
Analog
Analog
34
35
36
Connect to Type-C SBU2 pin.
Connect to Type-C SBU1 pin.
AUX_P
Connect to Auxiliary signal P from Display Port
Controller. If not used, leave floating.
AUX_N
Analog
P0.0
37
38
Connect to Auxiliary signal N from Display Port
Controller. If not used, leave floating.
LSTX/GPIO
Connect to UART_TX (LSTX) signal from Thunderbolt
Port Controller or can be used as GPIO. If not used,
leave floating
LSRX/GPIO
P0.1
39
11
Connect to UART_RX (LSRX) signal from Thunderbolt
Port Controller or can be used as GPIO. If not used,
leave floating
VBUS Control
VBUS OCP
VBUS_P_CTRL
Analog
Slew Rate controlled I/O for enabling/disabling Provider
side PFET
0: Path ON
High Z: Path OFF
VBUS_C_CTRL
Analog
12
Pin for enabling/disabling Consumer side PFET
0: Path ON
High Z: Path OFF
CSP
CSN
Analog
Analog
1
Current Sense Positive Input
Current Sense Negative Input
40
Document Number: 002-23191 Rev. *G
Page 11 of 38
EZ-PD™ CCG6
Table 3. Pinout for CYPD6125-40LQXIT and CYPD6137-40LQXIT (continued)
Group Name
Pin Name
Port
P1.4
P1.0
Pin
6
Description
GPIOs and
Serial
Interfaces
SWD_IO/TBT_RST/GPIO
SWD_CLK/I2C_CFG_EC/ GPIO
SWD I/O/GPIO
2
SWD Clock/ I2C config line.
I2C config line is used to select the I2C address of HPI
interface. The state of line decides the 7 bit I2C address
for HPI.
I2C Config Line Floating: 0x08
Pulled up with 1 K: 0x42
Pulled down with 1 K: 0x40
I2C_SDA_SCB2_TBT/GPIO
I2C_SCL_SCB2_TBT/GPIO
I2C_INT_TBT/GPIO
P1.1
P1.2
P1.3
P2.1
3
4
SCB2 I2C Data/GPIO
SCB2 I2C Clock/GPIO
5
TBT interrupt for port 1/GPIO
VBUS overvoltage output indicator/SCB4 I2C Data
VBUS undervoltage or OCP Output Indicator/SCB4 I2C
Clock/GPIO
OVP_TRIP/I2C_SDA_SCB4/GPIO
14
13
UV_OCP_TRIP/I2C_SCL_SCB4/GPIO P2.0
I2C_SDA_SCB1_EC/GPIO
I2C_SCL_SCB1_EC/GPIO
I2C_INT_EC/GPIO
P5.0
P5.1
P2.2
P3.0
P3.1
16
17
15
18
20
SCB1 I2C Data/GPIO
SCB1 I2C Clock/GPIO
Embedded Controller interrupt/GPIO
HPD/GPIO
Hot Plug Detect I/O/GPIO
SCB3 I2C Data or GPIO or voltage selection control for
VBUS
I2C_SDA_SCB3 / GPIO / VSEL_2
I2C_SCL_SCB3 / GPIO /VSEL_1
P3.2
21
SCB3 I2C Clock or GPIO or voltage selection control for
VBUS
Reset
Power
XRES
VBUS
Analog
Power
10
22
Reset input (Active LOW)
Supply input (4 V–21.5 V) for VBUS to 3.3-V Regulator.
This pin also discharges VBUS using internal pull-down
and also has monitors for overvoltage and undervoltage
conditions.
VSYS
VDDD
Power
Power
19
31
Supply input (2.75 V–5.5 V) for PD subsystem and
System resources.
Output of VBUS to 3.3-V regulator or connected to
VSYS using switch. Bypass with cap to gnd. This pin can
drive 2-mA external load.
VDDIO
VCCD
V5V
Power
Power
Power
32
33
8
This pin can be shorted to VDDD or an independent
supply can be given.
1.8-V regulator output for filter capacitor. This pin cannot
drive external load.
4.85-V to 5.5-V supply input to power EMCA cables.
Connected to CC1 or CC2 using low impedance
switches.
Ground
VSS
Ground EPAD Ground
Document Number: 002-23191 Rev. *G
Page 12 of 38
EZ-PD™ CCG6
Figure 6. 40-Pin QFN Pin Map (Top View) for CYPD6125-40LQXIT and CYPD6137-40LQXIT
1
2
3
CSP
I2C_CFG_EC
UART_RX
30
29
28
27
SWD_CLK/
_
UART TX
_
I2C_SDA_SCB2 TBT
_
DPLUS TOP
_
_
4
_
I2C SCL SCB2 TBT
_
DMINUS TOP
_
_
I2C INT
TBT
5
6
_
DPLUS BOT
26
SWD_IO/TBT_RST
EPAD
_
DMINUS BOT
25
24
23
7
8
9
CC2
V5V
_
DMINUS SYS
_
DPLUS SYS
CC1
XRES
VBUS
22
10
_
21 I2C_SCL_SCB3
1
/VSEL
Document Number: 002-23191 Rev. *G
Page 13 of 38
EZ-PD™ CCG6
Table 4 through Table 7 provide the various configuration options for the serial interfaces.
Table 4. Serial Communication Block (SCB1) Configuration
QFN Pin
UART
SPI
I2C
GPIO Functionality
16
17
18
15
UART_RTS_SCB1
UART_TX_SCB1
UART_RX_SCB1
UART_CTS_SCB1
SPI_MOSI_SCB1
SPI_MISO_SCB1
SPI_CLK_SCB1
SPI_SEL_SCB1
I2C_SDA_SCB1
GPIO
I2C_SCL_SCB1
GPIO
–
–
HPD/GPIO
I2C_INT_EC/GPIO
Table 5. Serial Communication Block (SCB2) Configuration
QFN Pin
UART
SPI Master
I2C Slave
GPIO Functionality
2
3
4
5
UART_RX_SCB2
UART_TX_SCB2
UART_CTS_SCB2
UART_RTS_SCB2
SPI_SEL_SCB2
SPI_MOSI_SCB2
SPI_MISO_SCB2
SPI_CLK_SCB2
–
SWD_CLK/I2C_CFG_EC/GPIO
I2C_SDA_SCB2_TBT/GPIO
I2C_SCL_SCB2_TBT/GPIO
I2C_INT_TBT/GPIO
I2C_SDA_SCB2
I2C_SCL_SCB2
–
Table 6. Serial Communication Block (SCB3) Configuration
QFN Pin
UART
SPI Master
I2C Slave
GPIO Functionality
20
21
29
30
UART_CTS_SCB3
UART_RTS_SCB3
UART_TX_SCB3
UART_RX_SCB3
SPI_SEL_SCB3
SPI_MOSI_SCB3
SPI_MISO_SCB3
SPI_CLK_SCB3
I2C_SDA_SCB3 VSEL_2/GPIO
I2C_SCL_SCB3 VSEL_1/GPIO
–
–
UART_TX/GPIO
UART_RX/GPIO
Table 7. Serial Communication Block (SCB4) Configuration
QFN Pin
UART
SPI Master
I2C Slave
GPIO Functionality
13
14
38
39
UART_CTS_SCB4
UART_RTS_SCB4
UART_TX_SCB4
UART_RX_SCB4
SPI_SEL_SCB4
SPI_MOSI_SCB4
SPI_MISO_SCB4
SPI_CLK_SCB4
I2C_SCL_SCB4 GPIO
I2C_SDA_SCB4 GPIO
–
–
LSTX/GPIO
LSRX/GPIO
Document Number: 002-23191 Rev. *G
Page 14 of 38
EZ-PD™ CCG6
Application Diagrams
Figure 7 illustrates a Type-C port Thunderbolt Notebook DRP application diagram using CCG6. The Type-C port can be used as a
power provider or a power consumer.
The CCG6 device communicates with the embedded controller (EC), which manages the Battery Charger Controller (BCC) to control
the charging and discharging of the internal battery. It also updates the Thunderbolt Controller via I2C to route the HighSpeed signals
coming from the Type-C port to the USB host (during normal mode) or the Graphics processor unit (during Display port Alternate
mode) or the Thunderbolt Host (during Thunderbolt Alternate mode) based on the alternate mode negotiation.
The CCG6 device controls the transfer of USB 2.0 DPLUS and DMINUS lines from the top and bottom of the Type-C receptacle to
the DPLUS and DMINUS lines of the USB Host controller. CCG6 also handles the routing of SBU1 and SBU2 lines from the Type-C
receptacle to the Thunderbolt controller for the Link management. CCG6 offers VBUS Short protection on SBU and CC lines.
The CCG6 device has integrated VCONN FETs for applications that need to provide power for accessories and cables using the
VCONN pin of the Type-C receptacle. VBUS FETs are also used for providing power over VBUS and for consuming power over VBUS.
The 5-m resistor between the 5-V supply and provider FETs is used for overcurrent detection on the VBUS. The VBUS_P_CTRL
pin of CCG6 has an in-built VBUS monitoring circuit that can detect OVP and UVP on VBUS.
Figure 7 illustrates a Single Port Thunderbolt Notebook DRP application diagram using CYPD6125-40LQXIT.
Figure 7. CCG6 in a Single Port Notebook Application using CYPD6125-40LQXIT
VBUS_OUT
5 V
8
7
8
7
6
5
0.005
Provider Path
CxNote [3]
3
2
1
3
2
1
6
5
10 µF
50 V
Power
Subsystem
49.9K
1%
4
4
Consumer Path
8
7
8
7
3
2
1
3
2
1
Note:
6
5
6
5
40
CSN
1
1µF
35V
CCG6 device s I2C address is determined by SWD_CLK pin.
1K resistors not populated = I2C address 0x08 (default)
1K resistor connected to GND = I2C address 0x40
1K resistor connected to VDDD = I2C address 0x42
VDDD
1 K
11
CSP
VBUS_P_CTRL
VBUS_C_CTRL
49.9K
1%
4
4
2
SWD_CLK/I2C_CFG_EC/P1.0
1 K
12
VDDD
31
VDDD
VBUS
1µF
10 µF
50 V
0.1 µF
32
19
VDDIO
3.3 V
VSYS
VCCD
1 µF
29
30
0.1 µF
UART_TX/P4.0
UART_RX/P4.1
X
X
33
0.1 µF
34
35
28
B8
A8
5 V (from System)
VBUS_OUT
SBU2
SBU1
D+
SBU2
SBU1
8
VCONN_V5V
VBUS
A6
A7
B6
B7
VDDD
4.7 K
0.1µF
DPLUS_TOP
22
10
27
DMINUS_TOP
DPLUS_BOT
3.3 V
D-
CCG6
(CYPD6125-40LQXIT)
40-QFN
26
25
XRES
D+
DMINUS_BOT
D-
2.2 K
B5
A5
7
9
CC2
CC1
CC2
CC1
2.2 K
2.2 K
15
I2C_INT_EC/P2.2
3.3 V
EMBEDDED
CONTROLLER
17
16
390 pF
390 pF
I2C_SCL_SCB1_EC/P5.1
I2C_SDA_SCB1_EC/P5.0
TYPE-C
RECEPTACLE
10 K
DNP
18
HPD/P3.0
20
100 K
X
I2C_SDA_SCB3/VSEL_2/P3.1
I2C_SCL_SCB3/VSEL_1/P3.2
3.3 V
21
14
X
3.3V
I2C_SDA_SCB4/OVP_TRIP/P2.1
X
13
2.2 K
I2C_SCL_SCB4/UV_OCP_TRIP/P2.0
X
DPSRC_HPD
100 K
10 K
2.2 K
2.2 K
8
6
SWD_IO/TBT_RST/P1.4
AUX_N
4
3
RESET_N
I2C_SCL_SCB2_TBT/P1.2
I2C_SDA_SCB2_TBT/P1.1
37
DPSRC_AUX_N
Data Lines
0.1 µF
0.1 µF
36
38
39
GND
AUX_P
DPSRC_AUX_P
LSTX
5
I2C_INT_TBT/P1.3
EPAD
LSTX / P0.0
41
Thunderbolt Controller
LSRX / P0.1
LSRX
DPLUS_SYS
23
DMINUS_SYS
24
100 K
Note:
Route D+ and D - Host lines to system
USB Host Controller
X
X
Note:
Follow recommendations from manufacturer for
Thunderbolt Controller connections
Note
3. Refer to AN210403 for the capacitor guidelines.
Document Number: 002-23191 Rev. *G
Page 15 of 38
EZ-PD™ CCG6
Electrical Specifications
Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings[4]
Parameter
VSYS_MAX
Description
Min
–
Typ
–
Max
Unit
V
Details/Conditions
Supply relative to VSS
6
–
V5V_MAX
Max supply voltage relative to VSS
Max VBUS voltage relative to Vss
Max supply voltage relative to VSS
–
–
6
24
V
VBUS_MAX
VDDIO_MAX
VGPIO_ABS
–
–
V
–
–
VDDD
V
Inputs to GPIO, DP/DM mux (UART,
SYS,DP/DM_top/botpins),SBUmux
(SBU1/2 pins)
–0.5
–
VDDIO + 0.5
V
IGPIO_ABS
Maximum current per GPIO
–25
–
–
25
mA
mA
–
IGPIO_INJECTION
GPIO injection current, Max for VIH
VDDD, and Min for VIL < VSS
>
–0.5
0.5
Absolute max, current
injected per pin
ESD_HBM
Electrostatic discharge human body
model
2200
1100
500
–
–
–
–
–
–
V
V
V
–
ESD_HBM_SBU
ESD_CDM
Electrostatic discharge human body
model for SBU1, SBU2 pins
Only applicable to SBU1,
SBU2 pins
Electrostatic discharge charged
device model
–
LU
Pin current for latch-up
–200
–
–
–
–
–
200
24
24
6
mA
V
–
–
VCC_PIN_ABS
VSBU_PIN_ABS
Max voltage on CC1 and CC2 pins
Max voltage on SBU1 and SBU2 pins
–
V
VGPIO_OVT_ABS OVT pins (16, 17) voltage
–0.5
V
–
Note
4. Usage above the absolute maximum conditions listed in Table 8 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-23191 Rev. *G
Page 16 of 38
EZ-PD™ CCG6
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V
except where noted.
DC Specifications
Table 9. DC Specifications (Operating Conditions)
Spec ID
Parameter
Description
Min
2.75
3
Typ Max
Unit
V
Details/Conditions
UFP applications
SID.PWR#23
VSYS
–
–
–
–
5.5
5.5
SID.PWR#23_A VSYS
V
DFP/DRP applications
SID.PWR#22
SID.PWR#1
VBUS
VDDD
4
21.5
VSYS
V
–
–
Regulated output voltage when
VSYS
–
V
VSYS powered
0.05
SID.PWR#1_A
VDDD
Regulated output voltage when
VBUS powered
3
–
3.65
V
–
–
SID.PWR#26
SID.PWR#13
V5V
4.85
–
–
5.5
V
V
VDDIO
VDDD
VDDD
At system-level short the VDDIO
to VDDD
SID.PWR#24
SID.PWR#15
SID.PWR#16
VCCD
CEFC
CEXC
Regulatedoutputvoltage(forCore
Logic)
–
–
–
1.8
100
1
–
–
–
V
–
Regulator bypass capacitor for
VCCD
nF X5R ceramic
µF
Regulator bypass capacitor for
VDDD
Active Mode, VSYS = 2.75 V to 5.5 V. Typical values measured at VSYS = 3.3 V
SID.PWR#4
IDD12
Supply current
–
10
–
mA TA = 25 °C, CC I/O IN Transmit or
Receive, no I/O sourcing current,
CPU at 24 MHz, PD port active
Deep Sleep Mode, VSYS = 2.75 V to 3.6 V
SID34
IDD29
VSYS = 2.75 to 3.6 V, I2C, wakeup
and WDT on.
–
–
150
100
–
–
µA VSYS = 3.3 V, TA = 25 °C,
SID_DS1
IDD_DS1
VSYS = 3.3 V, CC wakeup on,
Type-C not connected.
µA Power source = VSYS, Type-C
not attached, CC enabled for
wakeup, RpandRd connectedat
70-ms intervals by CPU.
SID_DS3
IDD_DS2
VSYS = 3.3 V, CC wakeup on,
DP/DM, SBU ON with
ADC/CSA/UVOV On
–
–
500
50
–
–
µA IDD_DS1 + DP/DM, SBU, CC
ON, ADC/CSA/UVOV ON
XRES Current
SID307
IDD_XR
Supply current while XRES
asserted
µA Power Source = VSYS = 3.3 V,
Type-C Not Attached, TA = 25 °C
Document Number: 002-23191 Rev. *G
Page 17 of 38
EZ-PD™ CCG6
CPU
Table 10. CPU Specifications (Guaranteed by Characterization)
Spec ID
Parameter
FCPU
Description
Min
–
Typ
–
Max Unit
Details/Conditions
SID.CLK#4
CPU input frequency
48
–
MHz All VDDD
µs Guaranteed by
SID.PWR#21 TDEEPSLEEP Wakeup from Deep Sleep mode
–
35
–
characterization
SYS.XRES#5 TXRES
External reset pulse width
5
–
µs
SYS.FES#1
T_PWR_RDY
Power-up to “Ready to accept
I2C/CC command”
–
5
25
ms
GPIO
Table 11. GPIO DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max Unit
Details/Conditions
SID.GIO#37
VIH_CMOS
Input voltage HIGH threshold
0.7 ×
VDDIO
–
–
V
V
V
V
CMOS input
SID.GIO#38
SID.GIO#39
SID.GIO#40
VIL_CMOS
Input voltage LOW threshold
–
–
–
–
0.3 ×
VDDIO
CMOS input
VIH_VDDIO2.7- LVTTL input, VDDIO < 2.7 V
VIL_VDDIO2.7- LVTTL input, VDDIO < 2.7 V
0.7 ×
VDDIO
–
–
–
–
0.3 ×
VDDIO
SID.GIO#41
SID.GIO#42
SID.GIO#33
VIH_VDDIO2.7+ LVTTL input, VDDIO 2.7 V
VIL_VDDIO2.7+ LVTTL input, VDDIO 2.7 V
2.0
–
–
–
–
–
0.8
–
V
V
V
–
–
VOH
VOH
VOL
Output voltage HIGH level
VDDIO
0.6
–
IOH = –4 mA at 3-V VDDIO
SID.GIO#34
SID.GIO#35
Output voltage HIGH level
VDDIO
0.5
–
–
–
–
V
IOH = –1mA at 1.8-V VDDIO
Output voltage LOW level
Output low voltage
Output low voltage
Output low voltage
–
0.6
0.4
0.6[5]
V
V
V
V
IOL = 4 mA at 1.8-V VDDIO
IOL = 3 mA, VDDIO > 2 V
IOL = 6 mA, VDDIO > 1.71 V
SID.GIO#35A VOL_I2C_2
SID.GIO#35B VOL_I2C_3
SID.GIO#35C VOL1_20mA
0.4
IOL = 20 mA, VDDIO > 3.0 V,
Applicable for
overvoltage-tolerant pins only
SID.GIO#36
VOL
Output voltage LOW level
–
–
0.6
V
IOL = 10 mA (IOL_LED) at 3-V
VDDIO
SID.GIO#5
SID.GIO#6
SID.GIO#16
Rpu
Rpd
IIL
Pull-up resistor when enabled
Pull-down resistor when enabled
3.5
3.5
–
5.6
5.6
–
8.5
8.5
2
k +25 °C TA, All VDDIO
k +25 °C TA, All VDDIO
nA +25 °C TA, 3-V VDDIO
Input leakage current
(absolute value)
SID.GIO#17
SID.GIO#43
CPIN
Max pin capacitance
–
3
7
–
pF
–
VHYSTTL
Input hysteresis, LVTTL
15
40
mV VDDIO > 2.7 V. Guaranteed by
characterization.
SID.GIO#44
VHYSCMOS
Input hysteresis CMOS
0.05 ×
VDDIO
–
–
mV VDDIO < 4.5 V
Note
5. To drive full bus load at 400 kHz, 6-mA I is required at 0.6-V V . Parts not meeting this specification can still function, but not at 400 kHz and 400 pF.
OL
OL
Document Number: 002-23191 Rev. *G
Page 18 of 38
EZ-PD™ CCG6
Table 11. GPIO DC Specifications (continued)
Spec ID Parameter Description
SID.GIO#44A VHYSCMOS55 Input hysteresis CMOS
Min
Typ
Max Unit
Details/Conditions
200
–
–
mV VDDIO > 4.5 V
Table 12. GPIO AC Specifications (Guaranteed by Characterization)
Spec ID
SID70
SID71
Parameter
TRISEF
TFALLF
Description
Min
2
Typ
–
Max
12
Unit
Details/Conditions
Rise time in Fast Strong mode
Fall time in Fast Strong mode
Rise time in Slow Strong mode
Fall time in Slow Strong mode
ns 3.3-V VDDIO, Cload = 25 pF
ns 3.3-V VDDIO, Cload = 25 pF
ns 3.3-V VDDIO, Cload = 25 pF
ns 3.3-V VDDIO, Cload = 25 pF
MHz 90/10%, 25-pF load
2
–
12
SID.GIO#46 TRISES
SID.GIO#47 TFALLS
SID.GIO#48 FGPIO_OUT1
10
10
–
–
60
–
60
GPIO FOUT; 3.3 VVDDIO5.5 V.
Fast Strong mode.
–
16
SID.GIO#49 FGPIO_OUT2
SID.GIO#50 FGPIO_OUT3
SID.GIO#51 FGPIO_OUT4
SID.GIO#52 FGPIO_IN
GPIO FOUT; 1.7 VVDDIO3.3 V.
–
–
–
–
–
–
–
–
16
7
MHz 90/10%, 25-pF load
MHz 90/10%, 25-pF load
MHz 90/10%, 25-pF load
MHz 90/10% VIO
Fast Strong mode.
GPIO FOUT; 3.3 VVDDIO5.5 V.
Slow Strong mode.
GPIO FOUT; 1.7 VVDDIO3.3 V.
Slow Strong mode.
3.5
16
GPIO input operating frequency;
1.7 VVDDIO5.5 V.
XRES
Table 13. XRES DC Specifications
Spec ID Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
CMOS input
SID.XRES#1 VIH
Input voltage HIGH threshold
0.7 ×
VDDIO
–
–
–
–
V
SID.XRES#2 VIL
Input voltage LOW threshold
–
0.3 ×
VDDIO
V
CMOS input
–
SID.XRES#3 CIN
Input capacitance
–
–
7
–
pF
SID.XRES#4 VHYSXRES
Input voltage hysteresis
0.05 ×
VDDIO
mV Guaranteed by characterization
Document Number: 002-23191 Rev. *G
Page 19 of 38
EZ-PD™ CCG6
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for GPIO Pins
Table 14. PWM AC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID.TCPWM.3 TCPWMFREQ Operating frequency
–
–
Fc
MHz Fc max = CLK_SYS.
Maximum = 48 MHz.
SID.TCPWM.4 TPWMENEXT Input trigger pulse width
2/Fc
2/Fc
–
–
–
–
ns
ns
For all trigger events
SID.TCPWM.5 TPWMEXT
Output trigger pulse width
Minimum possible width of
Overflow, Underflow, and CC
(Counter equals Compare value)
outputs
SID.TCPWM.5A TCRES
SID.TCPWM.5B PWMRES
SID.TCPWM.5C QRES
Resolution of counter
PWM resolution
1/Fc
1/Fc
1/Fc
–
–
–
–
–
–
ns
ns
ns
Minimum time between successive
counts
Minimum pulse width of PWM
output
Quadrature inputs resolution
Minimum pulse width between
quadrature-phase inputs
I2C
Table 15. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
FI2C1
Bit rate
–
–
1
Mbps –
UART
Table 16. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID
SID162
Parameter
Description
Description
Min
Typ
Max
Unit
Details/Conditions
Details/Conditions
FUART
Bit rate
–
–
1
Mbps –
SPI
Table 17. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID
SID166
Parameter
FSPI
Min
Typ
Max
Unit
SPI operating frequency (Master; 6X
oversampling)
–
–
8
MHz
–
Table 18. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
SID167
Parameter
TDMO
Description
Min
–
Typ
–
Max
15
–
Unit
Details/Conditions
MOSI valid after SClock driving edge
ns
–
SID168
TDSI
MISO valid before SClock capturing
edge
20
–
ns Full clock, late MISO
sampling
SID169
THMO
Previous MOSI data hold time
0
–
–
ns Referred to slave capturing
edge
Document Number: 002-23191 Rev. *G
Page 20 of 38
EZ-PD™ CCG6
Table 19. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
SID170
Parameter
TDMI
Description
Min Typ
Max
Unit
Details/Conditions
MOSI valid before Sclock capturing
edge
40
–
–
ns
–
T
–
SID171
TDSO
MISO valid after Sclock driving edge
–
–
48 + (3
× TSCB
ns
ns
SCB = TCPU
)
SID171A
TDSO_EXT
MISO valid after Sclock driving edge
in Ext Clk mode
–
–
48
SID172
THSO
Previous MISO data hold time
0
–
–
–
–
ns
ns
–
–
SID172A
TSSELSCK
SSEL valid to first SCK Valid edge
100
Memory
Table 20. Flash AC Specifications
Spec ID Parameter
Description
Min Typ Max
Unit
Details/Conditions
SID.MEM#4 TROW_WRITE
Row (Block) write time (erase and
program)
–
–
20
ms
–
–
SID.MEM#3 TROW_ERASE
Row erase time
–
–
–
–
–
–
–
–
13
7
ms
ms
SID.MEM#8 TROWPROGRAM Row program time after erase
25 °C to 55 °C, All VDDD
SID178
SID180
TBULKERASE
TDEVPROG
Bulk erase time (128 KB)
Total device program time
Flash endurance
–
35
25
–
ms
Guaranteed by design
–
s
Guaranteed by design
SID.MEM#6 FEND
100k
20
cycles
years
–
–
SID182
FRET1
FRET2
FRET3
Flash retention, TA ≤ 55 °C,
100K P/E cycles
–
SID182A
SID182B
Flash retention, TA ≤ 85 °C,
10K P/E cycles
10
3
–
–
–
–
years
years
–
–
Flash retention, TA ≤ 105 °C,
10K P/E cycles
Document Number: 002-23191 Rev. *G
Page 21 of 38
EZ-PD™ CCG6
System Resources
Power-on-Reset (POR) with Brown Out
Table 21. Imprecise Power On Reset (IPOR)
Spec ID
SID185
SID186
Parameter
VRISEIPOR
VFALLIPOR
Description
Rising trip voltage
Falling trip voltage
Min
0.80
0.70
Typ
–
Max
1.50
1.4
Unit
V
Details/Conditions
Guaranteed by
characterization
–
V
Table 22. Precise Power On Reset (POR)
Spec ID Parameter
SID190 VFALLPPOR
Description
Min
Typ
Max
Unit
Details/Conditions
Brown-out Detect (BOD) trip voltage 1.48
in active/sleep modes
–
1.62
V
Guaranteed by
characterization
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep mode 1.1
–
1.5
V
SWD Interface
Table 23. SWD Interface Specifications
Spec ID
Parameter
Description
3.3 V VDDIO 5.5 V
Min
Typ
Max
Unit
Details/Conditions
SID.SWD#1
F_SWDCLK1
–
–
14
MHz SWDCLK 1/3 CPU
clock frequency
SID.SWD#2
F_SWDCLK2
1.8 V VDDIO 3.3 V
–
–
7
MHz SWDCLK 1/3 CPU
clock frequency
SID.SWD#3
SID.SWD#4
SID.SWD#5
SID.SWD#6
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
0.25 × T
–
–
–
–
–
–
ns Guaranteed by
characterization
0.25 × T
ns
–
1
0.50 × T ns
–
ns
Internal Main Oscillator
Table 24. IMO AC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID.CLK#13 FIMOTOL
Frequency variation at 48 MHz
(trimmed)
–
–
±2
%
2.7 V ≤ VDDD < 5.5 V. –
25 °C ≤ TA ≤ 85 °C
SID226
TSTARTIMO
FIMO
IMO start-up time
IMO frequency
–
–
–
7
–
µs
–
–
SID.CLK#1
48
MHz
Internal Low-speed Oscillator
Table 25. ILO AC Specifications
Spec ID
SID234
Parameter
TSTARTILO1
TILODUTY
FILO
Description
ILO start-up time
ILO duty cycle
Min
–
Typ
–
Max
2
Unit
Details/Conditions
ms Guaranteed by
characterization
SID238
40
20
50
40
60
80
%
SID.CLK#5
ILO frequency
kHz
–
Document Number: 002-23191 Rev. *G
Page 22 of 38
EZ-PD™ CCG6
PD
Table 26. PD DC Specifications
Spec ID
Parameter
Description
Min
Typ
–
Max
1.2
Unit
V
Details/Conditions
SID.DC.cc_shvt.1 vSwing
SID.DC.cc_shvt.2 vSwing_low
SID.DC.cc_shvt.3 zDriver
SID.DC.cc_shvt.4 zBmcRx
SID.DC.cc_shvt.5 Idac_std
Transmitter Output High Voltage
Transmitter Output Low Voltage
Transmitter output impedance
Receiver Input Impedance
1.05
–
–
–
–
0.075
75
V
33
10
64
–
Ω
–
MΩ Guaranteed by design
Source current for USB standard
advertisement
–
96
µA
µA
µA
kΩ
–
–
–
–
SID.DC.cc_shvt.6 Idac_1p5a
SID.DC.cc_shvt.7 Idac_3a
SID.DC.cc_shvt.8 Rd
Source current for 1.5A at 5 V
advertisement
165.6
303.6
4.59
–
–
–
194.4
356.4
5.61
Source current for 3A at 5 V
advertisement
Pull down termination resistance
when acting as UFP (upstream
facing port)
SID.DC.cc_shvt.9 Rd_db
SID.DC.cc_shvt.10 zOPEN
Pull down termination resistance
when acting as UFP, with dead
battery
4.08
108
–
6.12
kΩ
–
CC impedance to ground when
disabled
–
–
kΩ
V
–
–
SID.DC.cc_shvt.11 DFP_default_0p2 CCvoltagesonDFPside-Standard 0.15
USB
0.25
SID.DC.cc_shvt.12 DFP_1.5A_0p4
SID.DC.cc_shvt.13 DFP_3A_0p8
SID.DC.cc_shvt.14 DFP_3A_2p6
CC voltages on DFP side-1.5A
CC voltages on DFP side-3A
CC voltages on DFP side-3A
0.35
0.75
2.45
–
–
–
–
0.45
0.85
2.75
0.7
V
V
V
V
–
–
–
–
SID.DC.cc_shvt.15 UFP_default_0p66 CCvoltagesonUFPside-Standard 0.61
USB
SID.DC.cc_shvt.16 UFP_1.5A_1p23
SID.DC.cc_shvt.17 Vattach_ds
SID.DC.cc_shvt.18 Rattach_ds
SID.DC.cc_shvt.30 FS_0p53
CC voltages on UFP side-1.5A
Deep sleep attach threshold
Deep sleep pull-up resistor
1.16
0.3
–
–
–
–
1.31
0.6
V
%
kΩ
V
–
–
–
–
10
50
Voltage threshold for Fast Swap
Detect
0.49
0.58
Analog-to-Digital Converter
Table 27. ADC DC Specifications
Spec ID
SID.ADC.1
Parameter
Resolution
Description
ADC resolution
Min
–
Typ
8
Max
–
Unit Details/Conditions
Bits
–
SID.ADC.2
SID.ADC.3
SID.ADC.4
SID.ADC.5
INL
Integral non-linearity
Differential non-linearity
Gain error
–1.5
–2.5
–1.5
VDDDmin
–
1.5
LSB –
LSB –
LSB –
DNL
–
2.5
Gain Error
VREF_ADC1
–
1.5
Reference voltage of ADC
–
VDDDmax
V
Reference voltage
generated from VDDD
SID.ADC.6
VREF_ADC2
Reference voltage of ADC
1.96
2.0
2.04
V
Reference voltage
generated from deep
sleep reference
Document Number: 002-23191 Rev. *G
Page 23 of 38
EZ-PD™ CCG6
Charger Detect
Table 28. Charger Detect DC Specifications
Spec ID
Parameter
VDAT_REF
Description
Min Typ Max Unit Details/Conditions
DC.CHGDET.1
Data detect voltage in charger detect 250
mode
–
–
–
–
–
400
700
700
175
175
13
mV
mV
mV
µA
–
–
–
–
–
DC.CHGDET.2
DC.CHGDET.3
DC.CHGDET.4
DC.CHGDET.5
VDM_SRC
VDP_SRC
IDM_SINK
IDP_SINK
Dn voltage source in charger detect 500
mode
Dp voltage source in charger detect 500
mode
Dn sink current in charger detect
mode
25
Dp sink current in charger detect
mode
25
µA
DC.CHGDET.6
DC.CHGDET.32
DC.CHGDET.31
DC.CHGDET.29
DC.CHGDET.34
DC.ccg6.dpdm.14
IDP_SRC
RDM_UP
RDM_DWN
RDAT_LKG
VSETH
Data contact detect current source
Dp/Dn pull-up resistance
Dp/Dn pull-down resistance
Data line leakage on Dp/Dn
Logic Threshold
7
0.9
–
–
–
–
–
–
µA
–
–
–
–
–
1.575 kΩ
14.25
300
1.26
–
24.8
500
1.54
40
kΩ
kΩ
V
RDCP_DAT
Dedicated charging port resistance
across DP and DN
Ω
VSYS Switch
Table 29. VSYS Switch Specifications
Spec ID Parameter
Description
Min Typ Max Unit
1.5
Details/Conditions
SID.DC.VDDDSW.1 Res_sw
Resistance from supply input to
output supply VDDD
–
–
Ω
Measured with a load
current of 5 mA to 10 mA
on VDDD
.
CSA
Table 30. CSA DC Specifications
Spec ID
DC.csa_scp.42
DC.csa_scp.43
OP.csa_scp.11
Parameter
SCP_6A
Description
Min Typ Max Unit
Details/Conditions
Short circuit current detect @ 6A
Short circuit current detect @10A
External sense register
–
–
–
±10
±10
5
–
–
–
%
%
–
–
SCP_10A
Rsense
m 1% accuracy
1APD contracts OCPset
%
OCP Trip threshold for 1A with
Rsense = 5 mΩ
130
Iocp_1A
Iocp_1A
–
–
–
–
at130%ofcontractvalue
or user programmable
±20%
DC.csa_scp.44
1APD contracts OCPset
at130%ofcontractvalue
or user programmable
OCP Trip threshold for 1A with
Rsense = 10 mΩ
130
±10%
%
2A, 3A, 4A, and 5A PD
contracts OCP set at
130% of contract value
OR user programmable
OCP Trip threshold for 2A, 3A, 4A
and 5A contracts with Rsense =
5/10 mΩ
130
±10%
DC.csa_scp.45
Iocp_5A
–
–
%
DC.rcp_scp.7a
DC.rcp_scp.6a
I_csainn_lk
I_csainp_lk
CSP pin input leakage when RCP
and CSA blocks are OFF
10
80
µA For provider VBUS = 5 V
CSN pin input leakage when RCP
and CSA blocks are OFF
µA For provider VBUS = 5 V
Document Number: 002-23191 Rev. *G
Page 24 of 38
EZ-PD™ CCG6
Table 30. CSA DC Specifications (continued)
Spec ID Parameter
DC.sys.1 I_CSP_RCP_ON CSP pin current when RCP block is
Description
Min Typ Max Unit
Details/Conditions
20
100
30
µA For provider VBUS = 5 V
µA For provider VBUS = 5 V
µA For provider VBUS = 5 V
µA For provider VBUS = 5 V
_CSA_OFF
ON and SCP is OFF
DC.sys.2
DC.sys.3
DC.sys.4
DC.sys.5
DC.sys.6
I_CSN_RCP_ON CSN pin current when RCP block is
_CSA_OFF ON and SCP is OFF
I_CSP_CSA_ON CSP pin current when RCP block is
OFF and SCP is ON
I_CSN_CSA_ON CSN pin current when RCP block is
OFF and SCP is ON
100
50
I_CSP_RCP_ON CSP pin current when RCP block is
µA For provider VBUS = 5 V.
Guaranteed by design.
_CSA_ON
ON and SCP is ON
I_CSP_RCP_ON CSN pin current when RCP block is
120
µA For provider VBUS = 5 V.
Guaranteed by design.
_CAS_ON
ON and SCP is ON
VBUS UV/OV
Table 31. VBUS UV/OV Specifications
Spec ID
Parameter
Description
Min Typ Max Unit
Details/Conditions
SID.UVOV.1
VTHUVOV1
Voltage threshold accuracy in active
mode using bandgap reference
–
±3
±5
–
–
%
–
–
–
SID.UVOV.2
VTHUVOV2
Voltage threshold accuracy in deep
sleep mode using deep sleep reference
–
–
%
SID.COMP_ACC
COMP_ACC Comparator input offset at 4s
–15
15
mV
Consumer Side PFET Gate Driver
Table 32. Consumer Side PFET Gate Driver DC Specifications
Spec ID
Parameter
Rpd
Description
Min Typ Max Unit
Details/Conditions
SID.DC.PGDO.1
Resistance when “pull_dn” enabled
–
–
–
2
5
–
kΩ
µA
–
–
DC.pgdo_pd_isnk.12 iout_0
DC.pgdo_pd_isnk.13 iout_1
DC.pgdo_pd_isnk.14 iout_2
DC.pgdo_pd_isnk.15 iout_3
DC.pgdo_pd_isnk.16 iout_4
DC.pgdo_pd_isnk.17 iout_5
DC.pgdo_pd_isnk.18 iout_6
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
1
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
2
–
–
–
–
–
–
4
8
–
–
–
–
–
–
µA
µA
µA
µA
µA
µA
–
–
–
–
–
–
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
4
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
8
16
32
63
126
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
16
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
32
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
64
Document Number: 002-23191 Rev. *G
Page 25 of 38
EZ-PD™ CCG6
Table 32. Consumer Side PFET Gate Driver DC Specifications (continued)
Spec ID
Parameter
Description
Min Typ Max Unit
Details/Conditions
DC.pgdo_pd_isnk.19 iout_7
DC.pgdo_pd_isnk.20 iout_8
DC.pgdo_pd_isnk.21 iout_9
DC.pgdo_pd_isnk.22 iout_10
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
128
–
–
–
–
252
–
–
–
–
µA
µA
µA
µA
–
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
256
504
–
–
–
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
512
1008
2016
Sink current through iref_out at iref_c-
trl_lv < 11 LOW and iref_ctrl_lv < 10:0
1024
Table 33. Consumer Side PFET Gate Driver AC Specifications
Spec ID
SID.ac.pgdo.2
Parameter
Description
Min Typ Max Unit
Details/Conditions
Tr_discharge Discharge Rate of output node
–
–
–
5
5
–
V/µs Guaranteed by design
ms
SID.ac.pgdo.sys_1
Tsoft_on
Consumer FET turn-ON delay for soft
start
–
Provider Side PFET Gate Driver
Table 34. Provider Side PFET Gate Driver DC Specifications
Spec ID
Parameter
Description
Min
Typ Max Unit
Details/Conditions
DC.pgdo_pu_1
Rpd
Pull-downresistancewhenenabledusing
strongest pull-down strength, using the
“STRONG_EN =1” field in the USBPD_P-
GDO_PD_ISNK_CFG register
–
–
2
kΩ
DC.pgdo_pu.2
Rpu
Pull-up resistance
–
–
1
2
–
kΩ
–
DC.pgdo_pd_isnk.1 Rpd_0
DC.pgdo_pd_isnk.2 Rpd_1
DC.pgdo_pd_isnk.3 Rpd_2
DC.pgdo_pd_isnk.4 Rpd_3
DC.pgdo_pd_isnk.5 Rpd_4
DC.pgdo_pd_isnk.6 Rpd_5
DC.pgdo_pd_isnk.7 Rpd_6
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 1
6830
Ω
–
–
–
–
–
–
–
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 2
–
–
–
–
–
–
3760
1900
1000
660
–
–
–
–
–
–
Ω
Ω
Ω
Ω
Ω
Ω
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 4
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 8
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 16
Resistance of iref_out to ground,
en_lv=HIGH, iref_ctrl_lv<11HIGHand
iref_ctrl_lv < 10:0 32
1700
900
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 64
Document Number: 002-23191 Rev. *G
Page 26 of 38
EZ-PD™ CCG6
Table 34. Provider Side PFET Gate Driver DC Specifications (continued)
Spec ID
Parameter
Description
Min
Typ Max Unit
Details/Conditions
DC.pgdo_pd_isnk.8 Rpd_7
DC.pgdo_pd_isnk.9 Rpd_8
DC.pgdo_pd_isnk.10 Rpd_9
DC.pgdo_pd_isnk.11 Rpd_10
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 128
–
630
560
530
520
–
–
–
–
Ω
Ω
Ω
Ω
–
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 256
–
–
–
–
–
–
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 512
Resistance of iref_out to ground, en_lv =
HIGH, iref_ctrl_lv < 11 HIGH and iref_c-
trl_lv < 10:0 1024
Table 35. Provider Side PFET Gate Driver AC Specifications
Spec ID
Parameter
Tpu
Description
Pull-up delay
Min Typ Max
Unit
Details/Conditions
AC.pgdo_pu.1
–
10
35
µs For pull-up load of 4-nF
capacitor and 50-kΩ resistor
AC.pgdo_pu.2
AC.pgdo_pu.3
Tpd
Pull-down delay
–
–
–
–
2
8
µs
–
SRpu
Output slew rate measured from 20%
to 80% of output rising waveform.
V/µs Cload = 4 nF, Vout = 0 V to 24
V, external pull-up of 50 kΩ
AC.pgdo_pu.4
SRpd
Output slew rate measured from 80%
to 20% of output falling waveform.
–
–
–
5
8
–
V/µs Cload = 4 nF, Vout = 24 V to 0
V, external pull-up of 50 kΩ
AC.pgdo.sys_1 Tsoft_on
Provider FET turn-ON delay for soft
start
ms
–
Provider Side PFET RCP
Table 36. Provider Side PFET RCP DC Specifications
Spec ID
Parameter
Description
Min Typ Max Unit
Details/Conditions
DC.RCP.44
Vcsa_rcp
Voltage across external Rsense
between CSP/CSN for which RCP
condition detected (CSN higher than
CSP by Vcsa_rcp)
–
2
6
mV
–
–
DC.RCP.45
DC.RCP.46
Vcomp_rcp
Voltage across VBUS and CSN pins for
which RCP condition is detected
20
–
130
mV
V
Vbus_max_det Voltage on CSN pin during provider
FET ON (source) for which RCP
condition is detected (this threshold is
user programmable
5.55 5.75 5.95
This spec is for 5-V provider
BUS voltage. For higher
V
voltages, firmware changes
this threshold based on VBUS
contract voltage.
Document Number: 002-23191 Rev. *G
Page 27 of 38
EZ-PD™ CCG6
Table 37. Provider Side PFET RCP, SCP AC Specifications
Spec ID
Parameter
Description
Min Typ Max Unit
Details/Conditions
AC.RCP_SYS.1 Toff_scp
AC.RCP_SYS.1 Toff_rcp
AC.RCP_SYS.2 Ton
Provider PFET switching off after
short circuit current detect through
provider PFET
–
–
–
10
10
55
–
µs Provider FET turns off with gate
pull-up of 50 kΩ and total gate
cap of 4 nF.
Provider PFET switching off after
reverse current detect through
provider PFET
–
µs Provider FET turns off with gate
pull-up of 50 kΩ and total gate
cap of 4 nF.
Recovery time to turn-ON PFET RCP
condition is removed
80
µs
–
Table 38. VBUS Provider Transition Specifications
Spec ID
AC.tr.1
Parameter
Description
Min Typ Max Unit
Details/Conditions
Ton
VBUS Low to High (10% to 90%) for
provider FET
–
–
–
5
–
150
–
ms 0 to 5-V transition, system-level
with external PFET with gate
pull-up of 50 k and total gate
cap of 4 nF
AC.tr.2
AC.tr.3
FR_Ton
Toff
VBUS Low to High (10% to 90%) during
FR swap
50
11
µs 0 to 5-V transition, system-level
with external PFET with gate
pull-up of 50 k and total gate
cap of 4 nF
VBUS_P_CTRL High to Low (90% to
10%) using internal active pull-up
µs 5 to 0-V transition, system-level
with external PFET with gate
pull-up of 50 k and total gate
cap of 4 nF
SBU Switch
Table 39. SBU Switch DC Specifications
Spec ID Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
DC.ccg6.20sbu.1 Ron1
DC.ccg6.20sbu.2 Ron2
DC.ccg6.20sbu.3 Isb
DC.ccg6.20sbu.15 icc
On resistance of AUXP/N to
SBU1/2 switch @ 3.3-V input
–
–
–
4
3
–
7
Ω
–
–
–
On resistance of AUXP/N to
SBU1/2 switch @ 1-V input
5
Ω
Block leakage current (VPUMP
+
15
µA
VDDD + VCCD
)
Block ICC when switch fully ON
–
15
–
125
µA
–
–
DC.ccg6.20sbu.16 OVP_threshold Overvoltage protection detection
threshold above VDDIO
200
1200
mV
DC.ccg6.20sbu.17 lsx_ron_3p3
On resistance of LSTX/LSRX to
SBU1/2 switch @ 3.3-V input
–
–
–
8.5
5.5
–
17
11
Ω
Ω
Ω
–
–
–
DC.ccg6.20sbu.18 lsx_ron_1
On resistance of LSTX/LSRX to
SBU1/2 switch @ 1-V input
DC.ccg6.20sbu.19 aux_ron_flat_fs Switch On flat resistance of
AUX_P/N to SBU1/2 switch (from
2.5
0 to 3.3 V)
DC.ccg6.20sbu.20 aux_ron_flat_hs Switch On flat resistance of
–
–
0.5
Ω
–
AUX_P/N to SBU1/2 switch (from
0 to 1 V)
Document Number: 002-23191 Rev. *G
Page 28 of 38
EZ-PD™ CCG6
Table 39. SBU Switch DC Specifications (continued)
Spec ID Parameter Description
Min
Typ
Max
Unit
Details/Conditions
DC.ccg6.20sbu.21 lsx_ron_flat_fs Switch On flat resistance of
LSTX/LSRX to SBU1/2 switch
–
–
5
Ω
–
–
(from 0 to 3.3 V)
DC.ccg6.20sbu.22 lsx_ron_flat_hs Switch On flat resistance of
LSTX/LSRX to SBU1/2 switch
–
–
0.5
Ω
(from 0 to 1 V)
Table 40. SBU Switch AC Specifications
Spec ID
Parameter
Description
Min
–
Typ
–
Max
120
80
Unit
pF
Details/Conditions
AC.ccg6.20sbu.1 Con
AC.ccg6.20sbu.2 Coff
Switch On capacitance
–
Switch Off capacitance- Connector
side
–
–
pF
Guaranteed by design
AC.ccg6.20sbu.3 Off_isolation
AC.ccg6.20sbu.4 TON
Switch isolation at F = 1 MHz
SBU switch turn-on time
SBU switch turn-off time
–50
–
–
–
–
–
–
dB
µs
µs
dB
Guaranteed by design
200
400
–
–
AC.ccg6.20sbu.5 TOFF
–
–
AC.ccg6.20sbu.3_ Off_isola-
Switch isolation at F = 1 MHz, from
AUX to SBU pins
–50
Guaranteed by design
aux
tion_AC_aux
AC.ccg6.20sbu.6 Off_isola-
tion_tran_dB
Coupling on sbu1,
–40
–30
–50
–50
–30
–
–
–
–
–
–
–
–
–
–
dB
dB
dB
dB
dB
Guaranteed by design
Guaranteed by design
Guaranteed by design
Guaranteed by design
Guaranteed by design
2 terminated to 50 , switch-OFF,
1-MHz rail-to-rail toggling on
LSTX/LSRX
AC.ccg6.20sbu.6_ Off_isola-
Coupling on sbu1,
aux
tion_tran_dB_aux 2 terminated to 50 , switch-OFF,
1-MHz rail-to-rail toggling on
AUX_P/AUX_N
AC.ccg6.20sbu.7 X_talk_AC
Cross talk of Switch at
F = 1 MHz
SBU1/2 to SBU2/1 when is data
transferred from LSTX/RX
AC.ccg6.20sbu.7_ X_talk_AC_aux
aux
Cross talk of Switch at
F = 1 MHz
SBU1/2 to SBU2/1 when is data
transferred from AUXP/AUXN
AC.ccg6.20sbu.8 X_talk_tran_dB
Coupling on SBU2
(1) When Data is transferred from
LSX to SBU1
(2) Rail-to-rail data on SBU1(2),
static signal on SBU2(1)
AC.ccg6.20sbu.8_ X_talk_tran_d-
Coupling on SBU2
–30
–
–
dB
Guaranteed by design
aux
B_aux
(1) When Data is transferred from
AUX to SBU1
(2) Rail-to-rail data on SBU1(2),
static signal on SBU2(1)
Document Number: 002-23191 Rev. *G
Page 29 of 38
EZ-PD™ CCG6
DP/DM Switch
Table 41. DP/DM Switch DC Specifications
(Charger Detect Block is Disconnected from DPLUS_TOP, DMINUS_TOP, DPLUS_BOT, and DMINUS_BOT through Switch)
Spec ID
Parameter
Description
Min
Typ
Max Unit Details/Conditions
DC.ccg6.dpdm.1 RON_HS
DC.ccg6.dpdm.2 RON_FS
DC.ccg6.dpdm.5 Con_FS
DC.ccg6.dpdm.6 Con_HS
DC.ccg6.dpdm.9 ileak_pin
DC.ccg6.dpdm.10 RON_UART
DP/DM On resistance (0 to 0.5 V) - HS
mode
–
–
8
12
50
10
1
–
DP/DM On resistance (0 to 3.3 V) - FS
mode
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Switch On capacitance at 6 MHz - FS
mode
pF Guaranteed by design
Switch on capacitance at 240 MHz -
HS mode
pF
µA
–
pin leakage at DP/DM connector side
and host side
–
DP/DM On resistance for UART lines
(0 to 3.3 V)
17
0.5
4
–
DC.ccg6.dpdm.11 RON_FLAT_HS DP/DM On Flat resistance in HS mode
(0 to 0.4 V)
Guaranteed by design
Guaranteed by design
Guaranteed by design
DC.ccg6.dpdm.12 RON_FLAT_FS DP/DM On flat resistance in FS mode
(0 to 3.3 V)
DC.ccg6.dpdm.13 RON_FLAT_UA DP/DM UART On flat resistance (0 to
4
RT
3.3 V)
Table 42. DP/DM Switch AC Specifications
(Charger Detect Block is Disconnected from DPLUS_TOP, DMINUS_TOP, DPLUS_BOT, and DMINUS_BOT through Switch)
Spec ID
Parameter
Description
3-db bandwidth
Min
Typ
Max
Unit Details/Conditions
AC.ccg6.dpdm.1 BW_3dB_HS
700
–
–
MHz Guaranteed by
design
AC.ccg6.dpdm.2 BW_3dB_FS
3-db bandwidth
100
–
–
MHz Guaranteed by
design
AC.ccg6.dpdm.5 TON
AC.ccg6.dpdm.6 TOFF
DP/DM Switch turn-on time
DP/DM Switch turn-off time
–
–
–
–
200
0.4
µs
–
µs Guaranteed by
design
AC.ccg6.dpdm.7 TON_VPUMP
DP/DM charge pump startup time
–
–
–
–
–
–
200
–
µs Guaranteed by
characterization
AC.ccg6.dpdm.8 Off_isolation_HS Switch-off isolation for HS
AC.ccg6.dpdm.9 Off_isolation_FS Switch-off isolation for FS
–20
–50
dB Guaranteed by
design
–
dB Guaranteed by
design
AC.ccg6.dpdm.10 X_talk
Cross talk of Switch From FS to HS at –50
F=12 MHz
–
dB Guaranteed by
design
AC.ccg6.dpdm.11 uart_coupling
peak to peak coupling of UART signal
to DP lines. (UART signal 0 to 3.3 V)
–
20
mV Guaranteed by
design
Document Number: 002-23191 Rev. *G
Page 30 of 38
EZ-PD™ CCG6
VCONN Switch
Table 43. VCONN Switch DC Specifications
Spec ID
Parameter
Description
Min Typ Max Unit Details/Conditions
DC.ccg6.20VCONN.1 Ron
Switch ON resistance at V5V = 5 V
with 215-mA load current
–
0.7
1.3
Ω
–
–
–
DC.ccg6.20VCONN.9 IOCP
Overcurrent detection range for
CC1/CC2
550
200
–
–
mA
DC.ccg6.20VCONN.10 OVP_threshold
CC1, CC2 overvoltage protection
detection threshold above VDDD or
V5V, whichever is higher
–
1200 mV
DC.ccg6.20VCONN.11 OVP_hysteresis
DC.ccg6.20VCONN.12 OCP_hysteresis
Overvoltage detection hysteresis
50
–
200
mV Guaranteed by
design
Overcurrent detection hysteresis
20
–
–
60
mA
mV
–
–
DC.ccg6.20VCONN.14 OVP_threshold_on Overvoltage detection threshold
above V5V of CC1/2, with CC1 or
200
700
CC2 switch enabled. Same
threshold triggers reverse current
protection circuit
Table 44. VCONN Switch AC Specifications
Spec ID
Parameter
Description
Min Typ Max Unit Details/Conditions
AC.ccg6.20VCONN.1 TON
AC.ccg6.20VCONN.2 TOFF
VCONN switch turn-on time
VCONN switch turn-off time
–
–
–
–
200
3
µs
–
µs Guaranteed by design
VBUS
Table 45. VBUS Discharge Specifications
Spec ID
Parameter
Ron1
Description
Min
1500
750
500
375
300
Typ Max Unit Details/Conditions
SID.VBUS.DISC.1
SID.VBUS.DISC.2
SID.VBUS.DISC.3
SID.VBUS.DISC.4
SID.VBUS.DISC.5
20-V NMOS ON resistance
20-V NMOS ON resistance
20-V NMOS ON resistance
20-V NMOS ON resistance
20-V NMOS ON resistance
–
–
–
–
–
3000
1500
1000
750
Ω
Ω
Ω
Ω
Ω
–
–
–
–
–
Ron2
Ron3
Ron4
Ron5
600
Document Number: 002-23191 Rev. *G
Page 31 of 38
EZ-PD™ CCG6
Ordering Information
Table 46 lists the EZ-PD CCG6 part numbers and features.
Table 46. EZ-PD CCG6 Ordering Information
DeadBattery
Termination
Part Number
Application
Type-C Ports
Termination Resistor
Role
Package
CYPD6125-40LQXIT Notebooks, Desktops
CYPD6137-40LQXIT Dock
1
1
Yes
No
Rp[6], Rd[7]
Rp[6], Rd[7]
DRP
DRP
40-pin QFN
40-pin QFN
Ordering Code Definitions
X
X
XX XX
-
X
CY PD
6
1
T
I
T = Tape and Reel
Temperature Grade: I = Industrial
Pb-free
Package Type: LQ
LQ = QFN
Number of pins in the package: XX = 40
Application specific, X = 5/7
Indicates if dead battery termination is supported or not
X = 2/3
Number of Type-C Ports: 1 = 1 Port
Product Type: 6 = Sixth-generation CCG6 product family
Marketing Code: PD = Power Delivery product family
Company ID: CY = Cypress
Notes
6. Termination resistor denoting a Source.
7. Termination resistor denoting an accessory or Sink.
Document Number: 002-23191 Rev. *G
Page 32 of 38
EZ-PD™ CCG6
Packaging
Table 47. Package Characteristics
Parameter
TA
Description
Conditions
Min
–40
–40
–
Typ
25
25
–
Max
85
Unit
°C
Operating ambient temperature
Operating junction temperature
Package JA (40-pin QFN)
Package JC (40-pin QFN)
Industrial
TJ
Industrial
100
19.3
13.6
°C
TJA
TJC
–
–
°C/W
°C/W
–
–
Table 48. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time within 5 °C of Peak Temperature
40-pin QFN
260 °C
30 seconds
Table 49. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
40-pin QFN
MSL 3
Figure 8. 40-Pin QFN (6 × 6 × 0.6 mm), LR40A/LQ40A 4.6 × 4.6 E-PAD (Sawn) Package Outline, 001-80659
001-80659 *A
Document Number: 002-23191 Rev. *G
Page 33 of 38
EZ-PD™ CCG6
Table 50. Acronyms Used in this Document (continued)
Acronyms
Acronym
opamp
OCP
OVP
PCB
Description
operational amplifier
Table 50. Acronyms Used in this Document
Acronym
ADC
Description
analog-to-digital converter
overcurrent protection
overvoltage protection
printed circuit board
power delivery
API
Arm®
application programming interface
advanced RISC machine, a CPU architecture
configuration channel
PD
CC
PGA
PHY
programmable gain amplifier
physical layer
BOD
CPU
Brown out Detect
central processing unit
POR
PRES
PSoC®
PWM
RAM
RCP
RISC
RMS
RTC
power-on reset
CRC
cyclic redundancy check, an error-checking
protocol
precise power-on reset
Programmable System-on-Chip™
pulse-width modulator
random-access memory
reverse current protection
reduced-instruction-set computing
root-mean-square
CS
current sense
CSA
DFP
DP
current sense amplifier
downstream facing port
DisplayPort, digital display interface developed by
Video Electronics Standards Association
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
real-time clock
DRP
dual role power
RX
receive
EEPROM
electrically erasable programmable read-only
memory
SAR
successive approximation register
I2C serial clock
I2C serial data
EMCA
a USB cable that includes an IC that reports cable
characteristics (e.g., current rating) to the Type-C
ports
SCL
SDA
S/H
sample and hold
EMI
ESD
FPB
FS
electromagnetic interference
electrostatic discharge
flash patch and breakpoint
full-speed
SPI
Serial Peripheral Interface, a communications
protocol
SRAM
SWD
TBT
static random access memory
serial wire debug, a test protocol
GPIO
IC
general-purpose input/output
integrated circuit
Thunderbolt, hardware interface standard for
peripherals developed by Intel
IDE
integrated development environment
TX
transmit
I2C, or IIC Inter-Integrated Circuit, a communications
protocol
Type-C
a new standard with a slimmer USB connector and
a reversible cable, capable of sourcing up to
100 W of power
ILO
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
input/output, see also GPIO
low-voltage detect
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
IMO
I/O
UFP
upstream facing port
Universal Serial Bus
LVD
LVTTL
MCU
NC
USB
low-voltage transistor-transistor logic
microcontroller unit
USBIO
USB input/output, CCG6 pins used to connect to
a USB port
no connect
XRES
external reset I/O pin
NMI
NVIC
nonmaskable interrupt
nested vectored interrupt controller
Document Number: 002-23191 Rev. *G
Page 34 of 38
EZ-PD™ CCG6
Document Conventions
Units of Measure
Table 51. Units of Measure
Symbol
°C
Unit of Measure
degrees Celsius
hertz
Hz
KB
kHz
k
Mbps
MHz
M
Msps
µA
1024 bytes
kilohertz
kilo ohm
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
microsecond
microvolt
µF
µs
µV
µW
mA
m
ms
mV
nA
microwatt
milliampere
milliohm
millisecond
millivolt
nanoampere
nanosecond
ohm
ns
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
sps
V
samples per second
volt
Document Number: 002-23191 Rev. *G
Page 35 of 38
EZ-PD™ CCG6
■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
References and Links to Applications Collateral
■ AN210403 - Hardware Design Guidelines for Dual Role Port
Applications Using EZ-PD™ USB Type-C Controllers
Knowledge Base Articles
■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and
CCG5 - KBA210740
■ AN210771 - Getting Started with EZ-PD™ CCG4
■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™
CCG5 Using PSoC® Programmer and MiniProg3 - KBA96477
Reference Designs
■ EZ-PD™ CCG2 Electronically Marked Cable Assembly
■ CCGX Frequently Asked Questions (FAQs) - KBA97244
■ Handling Precautions for CY4501 CCG1 DVK - KBA210560
■ Cypress EZ-PD™ CCGx Hardware - KBA204102
■ Difference between USB Type-C and USB-PD - KBA204033
■ CCGx Programming Methods - KBA97271
(EMCA) Paddle Card Reference Design
■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution
■ CCG1 USB Type-C to DisplayPort Cable Solution
■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution
■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution
■ Getting started with Cypress USB Type-C Products -
KBA04071
■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle
Card Reference Design
■ Type-C to DisplayPort Cable Electrical Requirements
■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card
Reference Schematics
■ Dead Battery Charging Implementation in USB Type-C
Solutions - KBA97273
■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle
■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution
■ CCG2 20W Power Adapter Reference Design
■ CCG2 18W Power Adapter Reference Design
■ Termination Resistors Required for the USB Type-C Connector
– KBA97180
■ VBUS Bypass Capacitor Recommendation for Type-C Cable
and Type-C to Legacy Cable/AdapterAssemblies – KBA97270
■ Need for Regulator and Auxiliary Switch in Type-C to
DisplayPort (DP) Cable Solution - KBA97274
■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference
Design Kit
■ Need for a USB Billboard Device in Type-C Solutions –
KBA97146
Kits
■ CCG1 Devices in Type-C to Legacy Cable/AdapterAssemblies
– KBA97145
■ CY4501 CCG1 Development Kit
■ CY4502 EZ-PD™ CCG2 Development Kit
■ CY4531 EZ-PD CCG3 Evaluation Kit
■ CY4541 EZ-PD™ CCG4 Evaluation Kit
■ Cypress USB Type-C Controller Supported Solutions –
KBA97179
■ Termination Resistors for Type-C to Legacy Ports – KBA97272
■ Handling Instructions for CY4502 CCG2 Development Kit –
KBA97916
Datasheets
■ CCG1 Datasheet: USB Type-C Port Controller with Power
Delivery
■ Thunderbolt™ Cable Application Using CCG3 Devices -
KBA210976
■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode
Controller on Type-C
■ Power AdapterApplication Using CCG3 Devices - KBA210975
■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974
■ Device Flash Memory Size and Advantages - KBA210973
■ Applications of EZ-PD™ CCG5 - KBA210739
Application Notes
■ CCG2: USB Type-C Port Controller Datasheet
■ CCG3: USB Type-C Controller Datasheet
■ CCG5C: USB Type-C Controller Datasheet
■ AN96527 - Designing USB Type-C Products Using Cypress’s
CCG1 Controllers
■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™
CCG2
Document Number: 002-23191 Rev. *G
Page 36 of 38
EZ-PD™ CCG6
Document History Page
Document Title: EZ-PD™ CCG6, USB Type-C Port Controller
Document Number: 002-23191
Submission
Revision
ECN
Description of Change
Date
*B
*C
6270794
6391831
08/01/2018 Post to external web.
11/22/2018 Updated Features.
Updated CCG6 DPLUS/DMINUS Switch Block Diagram.
Updated Peripherals.
Updated RCP section.
Updated Pinouts and Application Diagrams.
Updated Ordering Information.
*D
*E
6403615
6342385
12/11/2018 Removed Preliminary status.
Updated Applications and Logic Block Diagram.
Updated Overvoltage and Undervoltage Protection on VBUS.
Updated VBUS Load Switch Controller for Provider Path.
Added a footnote for SID.GIO#35B.
Updated Provider Side PFET RCP, SCP AC Specifications.
02/19/2019 Updated Copyright information.
Updated Type-C in Features.
Updated USB 2.0 Mux.
Updated Figure 7.
Updated Table 33.
*F
6524858
7199318
04/04/2019 Updated Table 2: Updated I2C Slave values for Floating and Pulled up with
1 k.
Updated Table 36: DC.RCP.45 Max value changed from 100 mV to 130 mV.
*G
26/07/2021 Updated package diagram title for Figure 8.
Updated Sales, Solutions, and Legal Information and Copyright information.
Document Number: 002-23191 Rev. *G
Page 37 of 38
EZ-PD™ CCG6
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
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cypress.com/arm
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cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
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cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB
Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify
the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely
responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any
modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you
had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT
NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.
© Cypress Semiconductor Corporation, 2018-2021. This document is the property of Cypress Semiconductor Corporation, an Infineon Technologies company, and its affiliates ("Cypress"). This
document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other
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code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally
to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the
Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation,
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Cypress, the Cypress logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, Traveo, WICED, and ModusToolbox are trademarks or registered trademarks of Cypress or a subsidiary of
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Document Number: 002-23191 Rev. *G
Revised July 26, 2021
Page 38 of 38
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