CYPD7299-68LDXS_技术文档

CYPD7291

EZ-PD™ CCG7D Automotive USB Type-C and

Buck-boost Controller

Dual-port

General description

EZ-PD™ CCG7D is Infineon’s highly integrated dual-port USB Type-C Power Delivery (PD) solution with integrated

buck-boost controllers. It complies with the latest USB Type-C and PD specifications, and is targeted for

automotive applications such as infotainment head unit charger, rear seat chargers as well as rear seat enter-

tainment. Integration offered by CCG7D not only reduces the BOM but also provides a footprint optimized

solution for automotive charging needs. It also includes hardware-controlled protection features on the VBUS.

CCG7D supports a wide input voltage range (4 to 24 V with 40 V tolerance) and programmable switching

frequency (150 to 600 kHz) in an integrated PD solution.

CCG7D is the most programmable USB-PD solution with an on-chip 32-bit Arm® Cortex®-M0 processor, 128-KB

flash, 16-KB RAM and 32-KB ROM that leaves most flash available for user application use. It also includes various

analog and digital peripherals such as ADC, PWMs and Timers. The inclusion of a fully programmable MCU with

analog and digital peripherals allows the implementation of custom system management functions such as

power throttling, load sharing, temperature monitoring, and fault logging.

Applications

• Head unit charger

• Rear seat charger (RSC)

• Rear seat entertainment (RSE)

Features

• USB-PD

- Supports two USB-PD ports

- Supports USB-PD revision 3.1 including programmable power supply (PPS) mode

- Extended data messaging

• Type-C

- Configurable resistors RP and RD

- VBUS provider NFET gate driver

- Integrated 100-mW VCONN power supply and control

• 2x Buck-boost controller

- 150 to 600 kHz switching frequency

- 5.5 to 24 V input, 40 V tolerant

- 3.3 to 21.5 V output

- 20-mV voltage and 50-mA current steps for PPS

- Supports selectable pulse-skipping mode (PSM) and forced continuous current/conduction mode (FCCM)

- Supports soft start

- Programmable spread spectrum frequency modulation for low EMI

- Programmable phase shift across two ports to further reduce the EMI

• 2x Legacy/proprietary charging blocks

- Supports QC 2.0/3.0/4.0/5.0, Apple charging 2.4A, Samsung adaptive fast charging (AFC), USB BC 1.2

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Features

• System-level fault protection

- On-chip VBUS overvoltage protection (OVP), overcurrent protection (OCP), undervoltage protection (UVP)

- VBUS to CC short protection

- VBAT to GND protection FET gate driver

- Under-voltage lockout (UVLO)

- Supports over-temperature protection through integrated ADC circuit and internal temperature sensor

- Supports connector and board temperature measurement using external thermistors

• 32-bit MCU subsystem

- 48-MHz Arm® Cortex®-M0 CPU

- 128-KB Flash

- 16-KB SRAM

- 32-KB ROM

• Peripherals and GPIOs

- 19 GPIOs

- Two over-voltage GPIOs

- 3x 8-bit ADC

- 4x 16-bit timer/counter/PWMs (TCPWM)

• Communication interfaces

- 4x SCBs (I²C/SPI/UART/LIN)

• Clocks and oscillators

- Integrated oscillator eliminating the need for an external clock

• Power supply

- 4 to 24 V input (40-V tolerant)

- 3.3 to 21.5 V output

- Integrated LDO capable of 5 V @ 150 mA

• Packages

- 68-pin QFN, wettable flank, AEC-Q100

- Supports automotive ambient temperature range (–40°C to +105°C) with 125°C operating junction

temperature

Datasheet

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

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Logic block diagram

CCG7D: Dual Port USB Type-C PD and Buck-Boost Controller

MCU Subsystem

I/O Subsystem

Integrated Digital Blocks

CC

4x TCPWM

4x SCB

Cortex-M0

48MHz

V_CONN

(I²C, SPI, UART, LIN)

19x GPIOs

Crypto (TRNG)

Flash

(128 KB)

-

SROM

(32 KB)

USB PD Subsystem x2

Baseband MAC &

PHY

V_CONNOCP, UV

SRAM

(16 KB)

Hi-Voltage LDO

(24 V)

V_BUSto CC Short -

Circuit Protection

8-bit SAR ADC

2x V

FETs

CONN

V

_BUSOVP, OCP, SCP

NFET Load Switch

Gate Driver

System

Protection

Resources

V_BATTto GND Short-

Circuit Protection

Buck-Boost

Controller

Functional block diagram

COMP_0

BST1_0 HGT1_0 SW1_0 LGT1_0 BST2_0 HGT2_0 SW2_0 LGT2_0 CSPO_0 CSNO_0

VBUS_CTRL_0

CSPI_0 CSNI_0

Input Sense

Amplifier (CSA),

Slope

GDRV (Buck)

GDRV (Boost)

Error

Amplifier

(CV)

Error

Amplifier

(CC)

Slew Rate Control

NGATE Driver

High-Side

CSA

High-Side

Low-Side

High-Side

Low-Side

Compensation

Driver (HSDR)

Driver (LSDR)

Driver (HSDR)

Driver (LSDR)

VBUS_IN

VBUS_C

Discharge Discharge

Zero-Crossing

Detector (ZCD)

Charge

Control

Zero-Crossing

Detector (ZCD)

Charge

Control

CC

HV

regulator

(VIN → 5V)

Reference

CC1_0

V5V_0

CC2_0

BMC

Reference

and IDAC

VIN

VDDD

VCCD

VCONN

PHY

Pulse-Width

Modulator

(PWM)

Charger

Detect

DP_0

DM_0

MCU Subsystem

Cortex-M0

3x 8-bit ADC

19 GPIOs

4x TCPWM

LV

4x SCB

(I2C/SPI/

UART/LIN)

Flash

SROM

(32KB)

SRAM

(16KB)

regulator

(5V → 1.8V)

DP_1

DM_1

Charger

Detect

(128KB)

Pulse-Width

Modulator

(PWM)

CC1_1

V5V_1

CC2_1

Reference

and IDAC

BMC

VCONN

PHY

XRES

POR/RESET

CC

Reference

Zero-Crossing

Detector (ZCD)

Zero-Crossing

Detector (ZCD)

Charge Control

VBUS_IN

VBUS_C

Discharge Discharge

High-Side

Low-Side

High-Side

Low-Side

Error

Amplifier

(CV)

Error

Amplifier

(CC)

Driver (HSDR)

Driver (LSDR)

Driver (HSDR)

Driver (LSDR)

CSA, Slope

Compensation

High-Side

CSA

Slew Rate Control

NGATE Driver

GDRV (Buck)

GDRV (Boost)

COMP_1

BST1_1 HGT1_1 SW1_1 LGT1_1 BST2_1 HGT1_2 SW1_2 LGT1_2 CSPO_1 CSNO_1 VBUS_CTRL_1

CSPI_1

CSNI_1

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Table of contents

General description ...........................................................................................................................1

Applications......................................................................................................................................1

Features ...........................................................................................................................................1

Logic block diagram ..........................................................................................................................3

Functional block diagram...................................................................................................................3

Table of contents...............................................................................................................................4

1 Functional overview .......................................................................................................................5

1.1 MCU subsystem.......................................................................................................................................................5

1.2 USB-PD subsystem .................................................................................................................................................5

1.3 Buck-boost subsystem ...........................................................................................................................................8

1.4 Buck-boost controller operation regions ............................................................................................................10

1.5 Analog blocks ........................................................................................................................................................12

1.6 Integrated digital blocks.......................................................................................................................................13

1.7 I/O subsystem .......................................................................................................................................................13

1.8 System resources..................................................................................................................................................14

2 Power subsystem..........................................................................................................................15

2.1 VIN under-voltage lockout (UVLO) .......................................................................................................................16

2.2 Using external VDDD supply.................................................................................................................................16

2.3 Power modes ........................................................................................................................................................16

3 Pin list .........................................................................................................................................17

4 CCG7D programming and bootloading............................................................................................21

4.1 Programming the device flash over SWD interface.............................................................................................21

5 Applications .................................................................................................................................22

6 Electrical specifications.................................................................................................................30

6.1 Absolute maximum ratings ..................................................................................................................................30

6.2 Device-level specifications ...................................................................................................................................33

6.3 Digital peripherals.................................................................................................................................................37

6.4 System resources..................................................................................................................................................39

7 Ordering information ....................................................................................................................47

7.1 Ordering code definitions.....................................................................................................................................47

8 Packaging ....................................................................................................................................48

9 Acronyms.....................................................................................................................................51

10 Document conventions................................................................................................................53

10.1 Units of measure .................................................................................................................................................53

Revision history ..............................................................................................................................54

Datasheet

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Functional overview

1

Functional overview

MCU subsystem

CPU

1.1

1.1.1

The Cortex®-M0 in CCG7D devices is a 32-bit MCU, which is optimized for low-power operation with extensive

clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. It also

includes a hardware multiplier, which provides a 32-bit result in one cycle. It includes an interrupt controller (the

NVIC block) with 32 interrupt inputs and a wakeup interrupt controller (WIC), which can wake the processor up

from Deep Sleep mode.

1.1.2

Flash ROM and SRAM

CCG7D devices have 128-KB Flash and 32-KB ROM for non-volatile storage. ROM stores libraries for authentication

and device drivers such as I²C, SPI, and so on. That spares flash for user application. Flash provides the flexibility

to store code for any customer feature and allows firmware upgrades to meet the latest USB-PD specifications

and application needs.

The 16-KB RAM is used under software control to store the temporary status of system variables and parameters.

A supervisory ROM that contains boot and configuration routines is provided.

1.2

USB-PD subsystem

This subsystem provides the interface to the Type-C USB port. This subsystem comprises:

• USB-PD physical layer

• VCONN switches and 100 mW VCONN source

• UVP, OVP on VBUS

• Output high-side current sense amplifier (CSA) for VBUS

• VBUS discharge control

• Gate driver for VBUS provider NFET

• Charger detection block for legacy charging (for example: BC1.2, Apple charging, and so on)

• VBAT to ground short-circuit protection

• VBUS to CC short-circuit protection

1.2.1

USB-PD physical layer

The USB-PD subsystem contains the USB-PD physical layer block and supporting circuits. The USB-PD physical

layer consists of a transmitter and receiver that communicate BMC encoded data over the CC channel per the

PD 3.1 standard. All communication is half-duplex. The physical layer or PHY implements collision avoidance to

minimize communication errors on the channel.

The USB-PD block includes all termination resistors (Rp and Rd) and their switches as required by the USB Type-C

spec. Rp and Rd resistors are required to implement connection detection, plug orientation detection and for the

establishment of the USB source/sink roles. The Rp resistor is implemented as a current source.

CCG7D device family with accompanying firmware is fully complaint with revisions 3.1 and 2.0 of the USB-PD

specification. The device supports PPS operation at all valid voltages from 3.3 to 21 V.

CCG7D devices support Rp under HW control in unconnected (standby) state to minimize standby power.

CCG7D devices support USB-PD Extended Messages containing data of up to 260 bytes. The extended messages

are larger than expected by USB-PD 2.0 hardware. As per the USB-PD protocol specification, devices compliant

with USB-PD revision 3.0 and later implement a chunking mechanism; messages are limited to Revision 2.0 sizes

unless both source and sink confirm and negotiate compatibility with longer message lengths.

Datasheet

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Functional overview

1.2.2

VCONN switches

CCG7D’s internal LDO voltage regulator is capable of powering a 100 mW VCONN supply for electronically marked

cable assemblies (EMCA), VCONN-powered devices (VPD), and VCONN-powered accessories (VPA) as defined in

the USB Type-C specification. All circuitry including VCONN switches and OCP is integrated in the device. In the

event the VCONN current exceeds the VCONN OCP limit, CCG7D can be configured to shut down the Type-C port

after a certain number of user configurable retries. The port can be re-enabled after a physical disconnect.

1.2.3

VBUS UVP and OVP

VBUS undervoltage and overvoltage faults are monitored using internal resistor dividers. The fault thresholds

and response times are user configurable. Refer to the EZ-PD Configuration Utility for more details. In the event

of a UVP or OVP, CCG7D can be configured to shut down the Type-C port after a certain number of user

configurable retries. The port can be re-enabled after a physical disconnect.

1.2.4

VBUS OCP and SCP

VBUS overcurrent and short-circuit faults are monitored using internal current sense amplifiers. Similar to OVP

and UVP, the OCP and SCP fault thresholds and response times are configurable as well. Refer to the EZ-PD

Configuration Utility for more details. In the event of OCP or SCP, CCG7D can be configured to shut down the

Type-C port after a certain number of user configurable retries. The port can be re-enabled after a physical

disconnect.

1.2.5

High-side CSA for VBUS

CCG7D device family supports VBUS current measurement and control using an external resistor (5 mΩ) in series

with the VBUS path. The voltage drop across this resistor is used to measure the average output current. The

same resistor is also used to sense and precisely control the output current in the PPS current foldback mode of

operation.

1.2.6

VBUS discharge control

The chip supports high-voltage (21.5 V) VBUS discharge circuitry. Upon the detection of device disconnection,

faults, or hard resets, the chip will discharge the output VBUS terminals to vSafe5V and/or vSafe0V within the time

limits specified in the USB-PD Specification.

1.2.7

Gate driver for VBUS provider NFET

CCG7D devices have an integrated high-voltage gate driver to drive the gate of an external high-side NFET on the

VBUS provider path. The gate driver drives the load switch that controls the connection between VBUS_IN and

VBUS_C. VBUS_CTRL is the output of this gate driver. To turn off the external NFET, the gate driver drives VBUS_IN

low to 0 V. To turn on the external NFET, it drives the gate to VBUS_IN + 8 V. There is an optional slow turn-on

feature which reduces the high-current spikes on the output. For a typical gate capacitance of 3 nF, a slow turn-on

time of 2 ms to 10 ms is configurable using firmware.

1.2.8

Legacy charge detection and support

CG7D implements battery charger emulation and detection (source and sink) for USB BC.1.2, legacy Apple

charging, Qualcomm Quick Charge 2.0/3.0, and Samsung AFC protocols.

Datasheet

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

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Functional overview

1.2.9

VBAT to ground short protection

CCG7D devices can protect against high currents through the Type-C return (ground) path. A NFET and a current

sense resistor are placed in series with the ground return path from the Type-C connector as shown in Figure 1.

This resistor senses the current, and if it exceeds the firmware-configured threshold, the NFET is turned off to

interrupt the current. This protects against overcurrent conditions caused by external faults (for example, if the

Type-C connector ground is accidentally connected to the car’s battery). The current sense can be implemented

with either a single-ended connection (referenced to internal ground) or with a true differential connection (see

CSN connection in Figure 1). The differential connection provides better current measurement accuracy but uses

an extra pin that can otherwise be repurposed as a GPIO. In the event of VBAT to ground short protection, CCG7D

can be configured to shut down the series FET between the Type-C receptacle ground and the system ground.

The recovery and retry mechanism can be customized using application firmware.

PGND

CSN

(optional)

5 m

GND

CSP

GPIO

Figure 1

VBUS to ground short circuit protection

1.2.10

VBUS to CC short protection

CCG7D’s CC pins have integrated protection from accidental shorts to high-voltage VBUS and VBAT. CCG7D

devices can handle up to 24 V external voltage on its CC pins without damage. In the event an over-voltage is

detected on the CC pin, CCG7D can be configured to shut down the Type-C port completely. The port will resume

normal operation once the CC voltage detected is within normal range.

Datasheet

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

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Functional overview

1.3

Buck-boost subsystem

The buck-boost subsystem in CCG7D devices can be configured to operate in buck-boost mode, buck-only mode

or boost-only mode. While buck-boost mode requires four external switching FETs, buck-only and boost-only

modes require only two FETs. Buck-only mode is useful when CCG7D device’s port is used for USB Type-A only

applications. Figure 2 shows the buck-boost subsystem’s main external components and connections.

5 m

V_IN

V_OUT

CSR1

CSR2

VDDD

CYPD729x

Figure 2

Buck-boost schematic showing external components

Buck-boost subsystem in CCG7D devices have the following key functional blocks:

• High side (cycle-by-cycle) CSA

• High side and low side gate driver

• Pulse width modulator (PWM)

• Error amplifier (EA)

1.3.1

High side (cycle-by-cycle) CSA

CCG7D device’s buck-boost controller implements peak current control in both boost and buck modes. A

high-side CSA is used for peak current sensing through an external resistor (5 mΩ; see CSR1 in Figure 2) placed

in series with the buck control FET. This current sense amplifier has a high bandwidth and a very wide common

mode range. This current sense resistor is connected to the CSA block through pins CSPI and CSNI as shown in

Figure 2. This block implements slope compensation to avoid sub-harmonic oscillation for the internal current

loop. In addition to peak current sensing, it provides a current limit comparator for shutting off the buck-boost

converter if the current hits an upper threshold which is programmable.

1.3.2

High-side gate driver and low-side gate driver

CCG7D’s buck-boost controller provides four N-channel MOSFET gate drivers: two floating high-side gate drivers

at the HG1 and HG2 pins, and two ground referenced low-side drivers at the LG1 and LG2 pin. The high side gate

drivers drive the high side external FET with a nominal VGS of 5 V. The high-side gate driver has a programmable

drive strength to drive external FET. An external capacitor and Schottky diode form a bootstrap network to collect

and store the high voltage source (VIN + ~5 V for HG1 and VBUS + ~5 V for HG2) needed to drive the high-side FET.

The low side gate driver drives the low side external FET with a nominal VGS of 5 V using energy sourced from

CCG7D’s internal LDO regulator and stored in the capacitor between PVDD and PGND. Low-side gate driver has

programmable drive strength to drive external FET.

In addition to drive strength, the high-side gate driver and the low-side gate driver have programmable options

for deadtime control and zero-crossing levels. High-side gate driver and low-side gate driver blocks include

zero-crossing detector (ZCD) to implement discontinuous-conduction mode (DCM) mode with diode emulation.

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

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Functional overview

The gate drivers for the switching FETs function at their nominal drive voltage levels (5 V) provided the VIN voltage

is between 5.5 V and 24 V.

1.3.3

Error amplifier (EA)

CCG7D’s buck-boost controller contains two error amplifiers for output voltage and current regulation. The error

amplifier is a trans-conductance type amplifier with single compensation pin (COMP) to ground for both the

voltage and current loops. In voltage regulation, the output voltage is compared with the internal reference

voltage and the output of EA is fed to the PWM block. In current regulation, the average current is sensed by VBUS

high side current sense amplifier through the external resistor. The output of the VBUS CSA is compared with an

internal reference in error amplifier block and EA output is fed to the PWM block. CCG7D’s firmware configures

and controls the integrated programmable error amplifier circuit for achieving the required VBUS voltage output

from the power section.

1.3.4

Pulse width modulator (PWM)

CCG7D device family’s PWM block generates the control signals for the gate drivers driving the external FETs in

peak current mode control. There are many programmable options for minimum/maximum pulse width,

minimum/maximum period, frequency and pulse skip levels to optimize the system design.

CCG7D devices have two firmware-selectable operating modes to optimize efficiency and reduce losses under

light load conditions: PSM and FCCM.

1.3.5

Pulse-skipping mode (PSM)

In pulse-skipping mode, the controller reduces the total number of switching pulses without reducing the active

switching frequency by working in “bursts” of normal nominal-frequency switching interspersed with intervals

without switching. The output voltage thus increases during a switching burst and decreases during a quiet

interval. This mode results in minimal losses at the cost of higher output voltage ripple. When in this mode,

CCG7D devices monitor the voltage across the buck or boost sync FET to detect when the inductor current

reaches zero; when this occurs, the CCG7D devices switch off the buck or boost sync FET to prevent reverse

current flow from the output capacitors (i.e. diode emulation mode). Several parameters of this mode are

programmable through firmware, allowing the user to strike their own balance between light load efficiency and

output ripple.

1.3.6

Forced-continuous-conduction mode (FCCM)

In FCCM, the nominal switching frequency is maintained at all times, with the inductor current going below zero

(i.e. “backwards” or from the output to the input) for a portion of the switching cycle as necessary to maintain

the output voltage and current. This keeps the output voltage ripple to a minimum at the cost of light-load

efficiency.

Datasheet

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

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Functional overview

1.4

Buck-boost controller operation regions

The input-side CSA’s output is compared with the output of the error amplifier to determine the pulse width of

the PWM. PWM block compares the Input voltage and output voltage to determine the buck, boost, and

buck-boost regions. The switching time/period of the four gate drivers (HG1, LG1, HG2, LG2) depends upon the

region in which the block is operating as well as the mode such as DCM or FCCM. The exact Vin vs Vout thresholds

for transitions into and out of each region are adjustable in firmware including the hysteresis.

1.4.1

Buck region operation (VIN >> VBUS)

When the VIN voltage is significantly higher than the required VBUS voltage, CCG7D devices operate in the buck

region. In this region, the boost side FETs are inactivated, with the boost control FET (connected to LG2) turned

off and the boost sync FET (connected to HG2) turned on. The buck side FETs are controlled as a buck converter

with synchronous rectification as shown in Figure 3.

ON

HG1

(Buck

Control)

OFF

ON

LG1

(Buck

Sync)

OFF

ON

LG2

(Boost

Control)

OFF

ON

HG2

(Boost

Sync)

OFF

Inductor

Current

0

t

Figure 3

Buck operation waveforms

Datasheet

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Functional overview

1.4.2

Boost region operation (VIN << VBUS)

When the VIN voltage is significantly lower than the required VBUS voltage, CCG7D devices operate in the boost

region. In this region, the buck side FETs are inactivated, with the sync FET turned off and the buck control FET

turned on. The boost side FETs are controlled as a boost converter with synchronous rectification as shown in

Figure 4.

ON

HG1

(Buck

Control)

OFF

ON

LG1

(Buck

Sync)

OFF

ON

LG2

(Boost

Control)

OFF

ON

HG2

(Boost

Sync)

OFF

Inductor

Current

0

t

Figure 4

Boost operation waveforms

1.4.3

Buck-boost region 1 operation (VIN ~> VBUS)

When the VIN voltage is slightly higher than the required VBUS voltage, CCG7D devices operate in the buck-boost

region 1. In this region, the boost side works at a fixed 20% duty cycle (programmable) while the buck side (LG1

/ HG1) duty cycle is modulated to control the output voltage. All four FETs are switching every cycle in this

operating region as shown in Figure 5.

ON

HG1

(Buck

Control)

OFF

ON

LG1

(Buck

Sync)

OFF

ON

LG2

(Boost

Control)

OFF

ON

HG2

(Boost

Sync)

OFF

Inductor

Current

0

t

Figure 5

Buck-boost region 1 (VIN ~> VBUS) operation waveforms

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Functional overview

1.4.4

Buck-boost region 2 operation (VIN ~< VBUS)

When the VIN voltage is slightly lower than the required VBUS voltage, CCG7D devices operate in the buck-boost

region 2. In this region, the buck side works at a fixed 80% duty cycle (programmable) while the boost side (LG2)

duty cycle is modulated to control the output voltage. All four FETs are switching every cycle in this operating

region as shown in Figure 6.

ON

HG1

(Buck

Control)

OFF

ON

LG1

(Buck

Sync)

OFF

ON

LG2

(Boost

Control)

OFF

ON

HG2

(Boost

Sync)

OFF

Inductor

Current

0

t

Figure 6

Buck-boost region 2 (VIN ~< VBUS) operation waveforms

1.4.5

Switching frequency and spread spectrum

CCG7D devices offer programmable switching frequency between 150 kHz and 600 kHz. The controller supports

spread spectrum clocking within the operating frequency range in all operating modes. Spread spectrum is

essential for charging applications to meet EMC/EMI requirements by spreading emissions caused by switching

over a wide spectrum instead of a fixed frequency, thereby reducing the peak energy at any particular frequency.

Both the switching frequency and the spread spectrum span are firmware programmable.

1.5

Analog blocks

ADC

1.5.1

CCG7D devices family has three 8-bit SAR ADCs available for general purpose analog-to-digital conversion

applications in the chip. The ADCs can be accessed from the GPIOs through an on-chip analog mux. See Table 29

for detailed specs on the ADCs.

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Functional overview

1.6

Integrated digital blocks

1.6.1

Serial communication block (SCB)

CCG7D devices have four SCB blocks that can be configured for I²C, SPI, UART or LIN. These blocks implement full

multi-master and slave I²C interfaces capable of multi-master arbitration. This I²C implementation is compliant

with the standard NXP I2C Specification V3.0. These blocks operate at speeds of up to 1 Mbps and have flexible

buffering options to reduce interrupt overhead and latency for the CPU. The SCB blocks support 8-byte deep

FIFOs for Receive and Transmit, which, by increasing the time given for the CPU to read data, greatly reduces the

need for clock stretching caused by the CPU not having read data on time. The I²C port I/Os for SCB0 are

overvoltage tolerant (OVT). The I²C ports for SCB1-3 are not OVT tolerant.

1.6.2

Timer, counter, pulse-width modulator (TCPWM)

The TCPWM block of CCG7D devices support four timers or counters or pulse-width modulators. These timers are

available for internal timer use by firmware or for providing PWM-based functions on the GPIOs.

1.7

I/O subsystem

The CCG7D devices have 19 GPIOs including the I²C and SWD pins which can also be used as GPIOs. The GPIO

block implements the following:

• Eight output drive modes

- Input only

- Weak pull-up with strong pull-down

- Strong pull-up with weak pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up with strong pull-down

- Disabled

- Weak pull-up with weak pull-down

• Input threshold select (CMOS or LVTTL)

• Individual control of input and output disables

• Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode)

• Selectable slew rates for dV/dt related noise control.

• OVT on one pair of GPIOs

During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause

excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex

between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals such as USB

Type-C port are also fixed in order to reduce internal multiplexing complexity. Data output registers and pin state

register store, respectively, the values to be driven on the pins and the states of the pins themselves. The config-

uration of the pins can be done by the programming of registers through software for each digital I/O port.

Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt

service routine (ISR) vector associated with it.

The I/O ports can retain their state during Deep Sleep mode or remain ON. If the operation is restored using reset,

then the pins shall go the High-Z state. If operation is restored by an interrupt event, then the pin drivers shall

retain their state until firmware chooses to change it. The IOs (on data bus) do not draw current on power down.

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Functional overview

1.8

System resources

1.8.1

Watchdog timer (WDT)

CCG7D devices have a watchdog timer running from the internal low-speed oscillator (ILO). This allows watchdog

operation during Deep Sleep and generate a watchdog reset if not serviced before the timeout occurs. The

watchdog reset is recorded in the Reset Cause register.

1.8.2

Reset

CCG7D devices can be reset from a variety of sources including a Software Reset. Reset events are asynchronous

and guarantee reversion to a known state. The Reset cause is recorded in a Register, which is sticky through Reset

and allows software to determine the cause of the reset. XRES pin is the dedicated pin for reset to apply hardware

reset.

1.8.3

Clock system

CCG7D devices have a fully integrated clock with no external crystal required. CCG7D device’s clock system is

responsible for providing clocks to all sub-systems that require clocks (SCB and PD) and for switching between

different clock sources, without glitches.

The HFCLK signal can be divided down as shown to generate synchronous clocks for the digital peripherals. The

clock dividers have 8-bit, 16-bit and 16-bit fractional divide capability. The 16-bit capability allows a lot of flexi-

bility in generating fine-grained frequency values. The clock dividers generate either enabled clocks (that is, 1 in

N clocking where N is the divisor) or an approximately 50% duty cycle clock (exactly 50% for even divisors, one

clock difference in the high and low values for odd divisors).

In Figure 7, PERXYZCLK represents the clocks for different peripherals.

IMO

HFCLK

Pre-Divider

ILO

LFCLK

HFCLK

Prescaler

SYSCLK

HALFSYSCLK

/2

Peripheral

Dividers

PERXYZ_CLK

Figure 7

Clocking architecture of CCG7D devices

1.8.4

Internal main oscillator (IMO) clock source

The IMO is the primary source of internal clocking in CCG7D devices. IMO default frequency for CCG7D devices is

48 MHz 2%.

1.8.5

ILO clock source

The internal low-speed oscillator is a very low power, relatively inaccurate, oscillator, which is primarily used to

generate clocks for peripheral operation in USB suspend (Deep Sleep) mode.

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Dual-port

Power subsystem

2

Power subsystem

Figure 8 shows an overview of the power subsystem architecture for CCG7D devices. The power subsystem of

CCG7D devices operate from VIN supply which can vary from 4 V to 24 V. The VDDD pin, the output of 5 V LDO gets

input from VIN supply. The VDDD pin can also be used as a power supply for external loads up to 150 mA. CCG7D

devices have two different power modes: Active and Deep Sleep, transitions between which are managed by the

power system. The VCCD pin, the output of the core (1.8 V) regulator, is brought out for connecting a 0.1-µF

capacitor for the regulator stability only. This pin is not supported as a power supply for external load.

VBUS_IN_0 VBUS_C_0 VBUS_IN_1 VBUS_C_1

NGDO

PVDD

Buck-Boost LS

Driver_P0

Buck-Boost LS

Driver_P1

1µF

PGND

VIN

PGND

VDDD

LDO

10µF

CC1_1

CC2_1

CC2_0

CC1_0

Core Regulator

VCCD

GND

0.1µF

2 x CC

Tx/Rx

GPIOs

Core

Figure 8

Power system requirement block diagram

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Power subsystem

2.1

VIN under-voltage lockout (UVLO)

CCG7D supports UVLO to allow the device to shut down when the input voltage is below the reliable level. It

guarantees predictable behavior when the device is up and running.

2.2

Using external VDDD supply

By default, external VDDD is not supported for CCG7D devices. However, usage of external VDDD supply can be

enabled using firmware. The pre-requisite for enabling external forcing of VDDD is to always maintain Vin higher

than VDDD and the external load on VDDD pin of CCG7D devices should never be higher than prescribed load

capability of internal VDDD LDO.

2.3

Power modes

Table 1 lists the power modes of the device accessible and observable by the user.

Table 1

Mode

Power modes

Description

Power is valid and XRES is not asserted. An internal reset source is asserted or sleep controller is

sequencing the system out of reset

Power is valid and CPU is executing instructions.

Power is valid and CPU is not executing instructions. All logic that is not operating is clock gated

to save power.

RESET

ACTIVE

SLEEP

Main regulator and most hard-IP are shut off. Deep Sleep regulator powers logic, but only

low-frequency clock is available.

Power is valid and XRES is asserted. Core is powered down.

DEEP SLEEP

XRES

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Pin list

3

Pin list

Table 2

CCG7D pinout table

GPIO port

Pin#

Pin name

Description

assignment

Negative power rail of port 0 buck high side gate driver. This is also connected to one

input terminal of zero current detection of buck low side gate driver.

1

SW1_0

Connect to the switch node (inductor) on the buck (input) side. Use a short and wide

trace to minimize the inductance and resistance of this connection.

Buck low side gate driver output of Port 0.

2

3

4

5

LG1_0

PGND_0

PVDD_0

LG2_0

Connect to the buck (input) side sync (low side) FET gate. Use a wide trace to minimize

inductance of this connection.

Ground of low side gate driver of Port 0. This is also connected to one input terminal

of zero current detection (ZCD) of buck low side gate driver.

Connect directly to Port 0’s board ground plane.

Supply of low side gate driver of Port 0.

Connect to VDDD. Use 1 µF and 0.1 µF bypass capacitors as close to the CCG7D IC as

possible.

Boost low side gate driver output of Port 0.

Connect to the boost (output) side control (low side) FET gate. Use a wide trace to

minimize inductance of this connection.

Output of the buck-boost converter of Port 0. This is also connected to one input

terminal of reverse current protection (RCP) of Boost high side gate driver.

Connect to the boost sync (high side) FET’s drain. Use a dedicated (Kelvin) trace for

this connection.

6

7

VOUT_0

SW2_0

Negative power rail of Port 0 boost high side gate driver. This is also connected to one

input terminal of RCP of boost high side gate driver

Connect to the switch node (inductor) on the boost (output) side. Use a short and wide

trace to minimize the inductance and resistance of this connection.

Boost high side gate driver output of Port 0.

–

8

9

HG2_0

Connect to the boost (output) side sync (high side) FET gate. Use a wide trace to

minimize inductance of this connection.

Boosted power supply of Port 0 boost high side gate driver. Bootstrap capacitor node.

Connect Schottky diode from VDDD to BST2_0. Also, connect a bootstrap capacitor

from this pin to SW2_0.

BST2_0

EA output pin of Port 0. Connect a compensation network to GND. Contact Infineon

for assistance in designing the compensation network.

10

11

12

COMP_0

CSPO_0

CSNO_0

Positive input of output current sensing amplifier of Port 0.

Connect to positive terminal of the output current sense resistor.

Negative input of output current sensing amplifier of Port 0.

Connect to negative terminal of the output current sense resistor.

Input of feedback voltage of error amplifier of Port 0.

Connect to the VBUS node between the output current sense resistor and the VBUS

provider NFET.

13

14

15

VBUS_IN_0

VBUS_C_0

CC1_0

Type-C connector VBUS voltage of Port 0.

Connect to the Type-C connector’s VBUS pin.

Type-C connector configuration channel 1 of Port 0.

Connect directly to the CC1 pin on the port’s Type-C connector. Also connect a 390-pF

capacitor to ground.

Type-C connector configuration channel 2 of Port 0.

Connect directly to the CC2 pin on the port’s Type-C connector. Also connect a 390-pF

capacitor to ground.

16

17

18

CC2_0

VBUS NFET gate driver output of Port 0.

Connect to the provider NFET’s gate.

VBUS_CTRL_0

GPIO / negative input terminal of Port 0’s VBAT – GND protection circuit.

Connect to the negative terminal of the VBAT – GND short protection current sense

resistor.

CSN_0_GPIO0

CSP_0_GPIO1

P0.0

P0.1

GPIO/ positive input terminal of Port 0’s VBAT – GND protection circuit.

Connect to the positive terminal of the VBAT – GND short protection current sense

resistor.

19

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Pin list

Table 2

CCG7D pinout table (continued)

GPIO port

Pin#

Pin name

Description

assignment

GPIO. This GPIO is pulled-down during reset/power-up, as it is used to disable the FET

for the Vbat to GND short circuit protection for Port 0. Set the correct drive mode, if

the Vbat to GND short circuit protection is not required in the design.

20

GPIO2

P0.2

21

22

GPIO3

GPIO4

P0.3

P0.4

GPIO

USB D+ of Port 0 / GPIO: D+ for implementing BC 1.2, AFC, QC or Apple charging.

CCG7D does not support USB data transmission on this pin.

23

24

25

26

27

DP_0_GPIO5

DM_0_GPIO6

VDDD

P1.0

P1.1

–

USB D- of Port 0 / GPIO: D- for implementing BC 1.2, AFC, QC or Apple charging.

CCG7D does not support USB data transmission on this pin.

5-V LDO output. Connect a 1-µF ceramic bypass capacitor to this pin. Also, connect

this pin directly to pin 63.

USB D- of port 1/GPIO: D- for implementing BC 1.2, AFC, QC or Apple charging. CCG7D

does not support USB data transmission on this pin.

DM_1_GPIO7

DP_1_GPIO8

P1.2

P1.3

USB D+ of port 1/ GPIO: D+ for implementing BC 1.2, AFC, QC or Apple charging. CCG7D

does not support USB data transmission on this pin.

28

29

30

XRES

GPIO9

GPIO10

–

External reset – Active low. Contains a 3.5 KΩ to 8.5 KΩ internal pull-up.

P2.0

P2.1

GPIO

GPIO. This GPIO is pulled-down during reset/power-up, as it is used to disable the FET

for the Vbat to GND short circuit protection for Port 1. Set the correct drive mode, if

the Vbat to GND short circuit protection is not required in the design.

31

32

33

GPIO11

P1.4

P1.5

P1.6

GPIO / positive terminal of low-side current sense amplifier (LS CSA) of Port 1.

Connect to the positive terminal of the VBAT – GND short protection current sense

resistor.

CSP_1_GPIO12

CSN_1_GPIO13

GPIO / negative terminal of low-side CSA of Port 1.

Connect to the negative terminal of the VBAT – GND short protection current sense

resistor.

34

35

GND

Chip ground. Connect directly to the exposed pad (EPAD) and to pin 64.

VBUS NFET gate driver output of Port 1.

Connect to the provider NFET’s gate.

VBUS_CTRL_1

Type-C connector configuration channel 2 of Port 1.

Connect directly to the CC2 pin on the port’s Type-C connector. Also connect a 390-pF

capacitor to ground.

36

CC2_1

Type-C connector configuration channel 1 of Port 1.

Connect directly to the CC1 pin on the port’s Type-C connector. Also connect a 390-pF

capacitor to ground.

37

38

39

CC1_1

Type-C connector BUS voltage of Port 1.

VBUS_C_1

VBUS_IN_1

Connect to the Type-C connector’s VBUS pin.

Input of feedback voltage of error amplifier of Port 1.

Connect to the VBUS node between the output current sense resistor and the VBUS

provider NFET.

–

Negative input of output CSA of Port 1.

40

41

42

CSNO_1

CSPO_1

COMP_1

Connect to negative terminal of the output current sense resistor.

Positive input of output CSA of Port 1.

Connect to positive terminal of the output current sense resistor.

EA output pin of Port 1. Connect a compensation network to GND. Contact Infineon

for assistance in designing the compensation network.

Boosted power supply of Port 1 boost high side gate driver. Connect Schottky diode

from VDDD to BST2_1. Bootstrap capacitor node. Also, connect a bootstrap capacitor

from this pin to SW2_1.

43

44

BST2_1

HG2_1

Boost high side gate driver output of Port 1.

Connect to the boost (output) side sync (high side) FET gate. Use a wide trace to

minimize inductance of this connection.

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Pin list

Table 2

CCG7D pinout table (continued)

GPIO port

Pin#

Pin name

Description

assignment

Negative power rail of Port 1 boost high side gate driver. This is also connected to one

input terminal of RCP of boost high side gate driver.

45

46

SW2_1

Connect to the switch node (inductor) on the boost (output) side. Use a short and wide

trace to minimize the inductance and resistance of this connection.

Output of the buck-boost converter of Port 1. This is also connected to one input

terminal of RCP of boost high side gate driver.

VOUT_1

Connect to the boost sync (high side) FET’s drain. Use a dedicated (Kelvin) trace for

this connection.

Boost low side gate driver output of Port 1.

47

48

49

50

LG2_1

PVDD_1

PGND_1

LG1_1

Connect to the boost (output) side control (low side) FET gate. Use a wide trace to

minimize inductance of this connection.

Supply of low side gate driver of Port 1.

Connect to VDDD. Use a 1 µF and 0.1 µF bypass capacitors as close to the CCG7D device

as possible.

Ground of low-side gate driver of port 1. This is also connected to one input terminal

of zero current detection of buck low side gate driver.

Connect directly to Port 0’s board ground plane.

–

Buck Low side gate driver output of Port 1.

Connect to the buck (input) side sync (low side) FET gate. Use a wide trace to minimize

inductance of this connection.

Negative power rail of Port 1 buck high side gate driver. This is also connected to one

input terminal of zero current detection of buck low side gate driver.

51

SW1_1

Connect to the switch node (inductor) on the buck (input) side. Use a short and wide

trace to minimize the inductance and resistance of this connection.

Buck high side gate driver output of Port 1.

52

53

54

HG1_1

BST1_1

CSNI_1

Connect to the buck (input) side control (high side) FET gate. Use a wide trace to

minimize inductance of this connection.

Boosted power supply of Port 1 buck high side gate driver. Connect Schottky diode

from VDDD to BST1_1. Bootstrap capacitor node.

Negative input of input CSA of Port 1.

Connect to the negative terminal of the input current sense resistor. Use a dedicated

(Kelvin) connection.

Positive input of input CSA of Port 1.

55

CSPI_1

Connect to the positive terminal of the input current sense resistor. Use a dedicated

(Kelvin) connection.

56

57

58

59

60

61

GPIO14/SWD_DAT

GPIO15/SWD_CLK

GPIO16

P3.0

P3.1

P3.2

P3.3

P3.4

GPIO/SWD programming and debug data signal

GPIO/SWD programming and debug clock signal

GPIO17

GPIO

GPIO18

VIN

4 V–24 V Input supply. Connect a ceramic bypass capacitor to GND close to this pin.

1.8-V core LDO output. Connect a 0.1-µF bypass capacitor to ground. Do not connect

anything else to this pin.

62

VCCD

63

64

VDDD

GND

5-V LDO output. Connect to pin 25. Also connect a 10-µF bypass capacitor to this pin.

Chip ground. Connect to the EPAD and to pin 34.

Positive input of input CSA of Port 0. Connect to the positive terminal of the input

current sense resistor. Use a dedicated (Kelvin) connection.

65

CSPI_0

Negative input of input CSA of Port 0.

–

66

CSNI_0

Connect to the negative terminal of the input current sense resistor. Use a dedicated

(Kelvin) connection.

Boosted power supply of Port 0 buck high side gate driver. Bootstrap capacitor node.

Connect Schottky diode from VDDD to BST1_0. Also, connect a bootstrap capacitor

from this pin to SW1_0.

67

68

BST1_0

Buck high side gate driver output of Port 0.

HG1_0

EPAD

Connect to the buck (input) side control (high side) FET gate. Use a wide trace to

minimize inductance of this connection.

Exposed ground pad. Connect directly to pins 34 and 64.

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Pin list

1

2

3

4

5

6

7

8

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

SW1_1

LG1_1

PGND_1

PVDD_1

LG2_1

VOUT_1

SW2_1

HG2_1

BST2_1

COMP_1

CSPO_1

CSNO_1

SW1_0

LG1_0

PGND_0

PVDD_0

LG2_0

VOUT_0

SW2_0

HG2_0

EPAD

9

BST2_0

COMP_0

CSPO_0

CSNO_0

VBUS_IN_0

VBUS_C_0

CC1_0

10

11

12

13

14

15

16

VBUS_IN_1

VBUS_C_1

CC1_1

CC2_1

CC2_0

17

35

VBUS_CTRL_1

VBUS_CTRL_0

Figure 9

CCG7D 68-QFN pinout

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Dual-port

CCG7D programming and bootloading

4

CCG7D programming and bootloading

There are two ways to program application firmware into a CCG7D device:

1. Programming the device flash over SWD interface

2. Application firmware update over specific interfaces (CC, I2C)

Generally, the CCG7D devices are programmed over SWD interface only during development or during the

manufacturing process of the end-product. Once the end-product is manufactured, the CCG7D device’s

application firmware can be updated via the appropriate bootloader interface. Infineon strongly recommends

customers to use the EZ-PD Configuration Utility to turn off the application firmware update over CC or I2C

interface in the firmware that is updated into CCG7D’s flash before mass production. This prevents unauthorized

firmware from being updated over CC interface in the field. If you desire to retain the application firmware update

over CC/ I2C interfaces feature post-production for on-field firmware updates, contact Infineon Sales for further

guidelines.

4.1

Programming the device flash over SWD interface

The CCG7D family of devices can be programmed using the SWD interface. Infineon provides programming kits

(CY8CKIT-002 MiniProg3 Kit) called MiniProg3 and (CY8CKIT-005 MiniProg4 Kit) MiniProg4 which can be used

to program the flash as well as debug firmware. The flash is programmed by downloading the information from

a hex file. This hex file is a binary file generated as an output of building the firmware project in PSoC™ Creator

Software. Click here for more information on how to use the MiniProg3 programmer. Click here for more

information on how to use the MiniProg4 programmer. There are many third-party programmers that support

mass programming in a manufacturing environment.

As shown in the block diagram in Figure 10, the SWD_DAT and SWD_CLK pins are connected to the host

programmer’s SWDIO (data) and SWDCLK (clock) pins respectively. During SWD programming, the device can be

powered by the host programmer by connecting its VTARG (power supply to the target device) to VDDD pins of

CCG7D device. If the CCG7D device is powered using an on-board power supply, it can be programmed using the

“Reset Programming” option. For more details, refer the CYPDXXXX Programming Specifications.

3.3 V

V_DD

Host Programmer

VTARG

CYPD7XXX

VDDD

10µF

1µF

0.1µF

SWDCLK

SWDIO

XRES

SWD_CLK

SWD_DAT

XRES

V_CCD

0.1µF

GND

Figure 10

Connecting the programmer to CYPD7XXX device

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Applications

5

Applications

Figure 11 shows a typical head unit charger application block diagram using CCG7D. A head unit charger (also

known as center stack) is located prominently in the center of the dashboard or console. They are powered by

the car battery and are used for charging the mobile/tablet and for media transfer using USB data

communications. In this application, CCG7D will always be in DFP role supporting the charging of the device. It

negotiates the power with the connected device and uses the integrated buck-boost controller to supply the

required voltage and current.

The DP/DM lines of the Type-C receptacles are connected to the host processor/hub, for data connectivity to the

head unit (HU). These pins are also connected to CCG7D to support legacy charging protocol BC v1.2 CDP. The

I²C interface is used to interface with the host processor/hub, to support host processor interface (HPI)

commands, provide status to the Head Unit, and support FW updates. Note that per the Battery Charging Speci-

fication 1.2, other legacy charging protocols other than BC v1.2 CDP cannot be supported in conjunction with USB

data communication.

CCG7D measures various temperatures using external NTC thermistors. CCG7D throttles the output power based

on temperature and/or shuts off the power under critical conditions. It also monitors the battery voltage and

lowers the output power if the battery voltage is lower than the user-configured threshold. When no load is

connected to the USB Type-C port, CCG7D remains in standby mode without switching on the buck-boost

controller.

(USB PD, 3.3-21V, 5A)

5 m

V_IN

V_BUS

Battery Input

(9V-18V)

VDDD

0.1μF

68

67

1

2

5

9

7

8

6

11 12

13

17

14

VDDD

1μF

4

3

PVDD_0

PGND_0

66

CSNI_0

65

61

62

CSPI_0

VIN

18

CSN_0_GPIO0

5 m

19

20

GND

CC1

CSP_0_GPIO1

GPIO2

VCCD

0.1μF

10

COMP_0

15

16

CC1_0

CC2_0

390pF

69

64

34

GND (EPAD)

CC2

390pF

GND

AGND

HPI_SDA

HPI_SCL

HPI_INT

DP

29

30

21

22

23

24

DP_0_GPIO5

DM_0_GPIO6

GPIO9

GPIO10

GPIO3

GPIO4

DM

Host Processor

VDDD

63

25

VDDD

CYPD7291-68LDXS

0.1μF

10μF

1μF

48

49

VDDD

AGND

1

2

3

4

PVDD_1

PGND_1

0.1μF 1μF

33

XRES

28

57

XRES

CSN_1_GPIO13

5 m

SWD_CLK

GPIO15

32

31

GND

CSP_1_GPIO12

GPIO11

SWD_DAT

CHIP_EN

56

58

5

GPIO14

GPIO16

Programming Header

– not needed for final

production

CC1

CC2

37

36

P1_NTC[0]

59

60

CC1_1

CC2_1

GPIO17

GPIO18

390pF

P0_NTC[0]

42

COMP_1

27

26

DP

DP_1_GPIO8

DM_1_GPIO7

DM

55

54

CSPI_1

CSNI_1

52

53 51 50

47 43

45 44 46 41 40

VDDD

39

35

38

VDDD

0.1μF

V_BUS

V_IN

5 m

(USB PD, 3.3-21V, 5A)

Figure 11

CCG7D head unit charger application diagram

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Dual-port

Applications

Table 3

Pin #

Head unit (HU) GPIO pin mapping for application diagram in Figure 11

Pin name

Function

GPIO

HU

Port 0: CSN pin on ground side to implement VBAT

to GND short circuit protection

18

19

20

CSN_0_GPIO0

P0.0

P0_VBAT_CSN

Port 0: CSP pin on ground side to implement VBAT

to GND short circuit protection

CSP_0_GPIO1

GPIO2

P0.1

P0.2

P0_VBAT_CSP

P0_VBAT_FET

Port 0: GPIO to disable the FET for VBAT to GND short

circuit protection

21

22

GPIO3

GPIO4

HPI Interrupt

P0.3

P0.4

HPI_INT

GPIO

GPIO, available for system level function

Port 0: USB DP of Type-C port.

23

24

26

27

DP_0_GPIO5

DM_0_GPIO6

DM_1_GPIO7

DP_1_GPIO8

P1.0

P1.1

P1.2

P1.3

P0_DP

P0_DM

P1_DM

P1_DP

Supports BC 1.2, QC, Apple Charging and AFC

Port 0: USB DM of Type-C port.

Supports BC 1.2, QC, Apple Charging and AFC

Port 1: USB DM of Type-C port.

Supports BC 1.2, QC, Apple Charging and AFC

Port 1: USB DP of Type-C port.

Supports BC 1.2, QC, Apple Charging and AFC

29

30

GPIO9

HPI data (SDA)

HPI clock (SCL)

P2.0

P2.1

HPI_SDA

HPI_SCL

GPIO10

Port 1: GPIO to disable the FET for VBAT to GND short

circuit protection

31

32

33

56

GPIO11

CSP_1_GPIO12

CSN_1_GPIO13

GPIO14

P1.4

P1.5

P1.6

P3.0

P1_VBAT_FET

P1_VBAT_CSP

P1_VBAT_CSN

GPIO

Port 1: CSP pin on ground side to implement VBAT

to GND short circuit protection

Port 1: CSN pin on ground side to implement VBAT

to GND short circuit protection

Connect to the host programmer’s SWDIO (data) for

programming the CCG7D device

Connect to the host programmer’s SWDCLK (clock)

for programming the CCG7D

Chip Enable pin

57

GPIO15

P3.1

CHIP_EN

58

59

60

GPIO16

GPIO17

GPIO18

GPIO, available for system level function

Port 1: Thermistor

Port 0: Thermistor

P3.2

P3.3

P3.4

GPIO

P1_NTC[0]

P0_NTC[0]

Datasheet

23

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Applications

Figure 12 shows a typical rear seat charger application block diagram using CCG7D. This application is similar to

the head unit charger application without the hub and data communications. There is no host processor/hub in

this application. This application can be configured to support the legacy charging protocols – BC1.2 DCP,

Qualcomm QC2.0/3.0, Apple charging, and Samsung AFC.

(USB PD, 3.3-21V, 5A)

5 m

V_IN

V_BUS

Battery Input

(9V-18V)

VDDD

0.1μF

68

67

1

2

5

9

7

8

6

11

12

13

17

14

1μF

4

3

PVDD_0

PGND_0

66

CSNI_0

65

61

62

CSPI_0

VIN

18

CSN_0_GPIO0

5 m

19

20

GND

CC1

CSP_0_GPIO1

GPIO2

VCCD

0.1μF

10

COMP_0

15

16

CC1_0

CC2_0

390pF

69

64

34

GND (EPAD)

GND

CC2

390pF

AGND

29

30

21

22

DP

GPIO9

23

24

DP_0_GPIO5

DM_0_GPIO6

GPIO10

DM

GPIO3

GPIO4

63

25

VDDD

10μF

VDDD

CYPD7291-68LDXS

0.1μF

1μF

48

49

1

2

3

VDDD

AGND

PVDD_1

PGND_1

0.1μF 1μF

33

28

57

56

XRES

CSN_1_GPIO13

XRES

5 m

LIN_RX

LIN_TX

SWD_CLK

4

5

32

31

GND

GPIO15

GPIO14

CSP_1_GPIO12

GPIO11

SWD_DAT

LIN_TXR_EN

Programming Header

– not needed for final

production

58

GPIO16

CC1

CC2

37

36

P1_NTC[0]

P0_NTC[0]

59

60

CC1_1

CC2_1

GPIO17

GPIO18

390pF

42

COMP_1

27

26

DP

DP_1_GPIO8

DM_1_GPIO7

LIN_RX

DM

55

54

CSPI_1

CSNI_1

LIN

LIN_TX

Transceiver

LIN_TXR_EN

52

39

35

38

53 51 50

47 43

45 44

46 41 40

VDDD

0.1μF

V_BUS

V_IN

5 m

(USB PD, 3.3-21V, 5A)

Figure 12

CCG7D RSC application diagram

Datasheet

24

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Applications

Table 4

Pin #

RSC GPIO pin mapping for application diagram in Figure 12

Pin name

Function

GPIO

RSC

Port 0: CSN pin on ground side to implement VBAT

to GND short circuit protection

18

19

20

CSN_0_GPIO0

P0.0

P0_VBAT_CSN

Port 0: CSP pin on ground side to implement VBAT

to GND short circuit protection

CSP_0_GPIO1

GPIO2

P0.1

P0.2

P0_VBAT_CSP

P0_VBAT_FET

Port 0: GPIO to disable the FET for VBAT to GND short

circuit protection

21

22

GPIO3

GPIO4

GPIO, available for system level function

P0.3

P0.4

GPIO

Port 0: USB DP of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

23

24

26

27

DP_0_GPIO5

DM_0_GPIO6

DM_1_GPIO7

DP_1_GPIO8

P1.0

P1.1

P1.2

P1.3

P0_DP

P0_DM

P1_DM

P1_DP

Port 0: USB DM of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

Port 1: USB DM of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

Port 1: USB DP of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

29

30

GPIO9

GPIO, available for system level function

P2.0

P2.1

GPIO

GPIO10

Port 1: GPIO to disable the FET for VBAT to GND short

circuit protection

31

32

33

GPIO11

P1.4

P1.5

P1.6

P1_VBAT_FET

P1_VBAT_CSP

P1_VBAT_CSN

Port 1: CSP pin on ground side to implement VBAT

to GND short circuit protection

CSP_1_GPIO12

CSN_1_GPIO13

Port 1: CSN pin on ground side to implement VBAT

to GND short circuit protection

LIN TX pin

56

57

GPIO14

GPIO15

Connect to the host programmer’s SWDIO (data) for

programming the CCG7D device

P3.0

P3.1

LIN_TX

LIN_RX

LIN RX pin

Connect to the host programmer’s SWDCLK (clock)

for programming the CCG7D

58

59

60

GPIO16

GPIO17

GPIO18

LIN Transceiver enable

Port 1: Thermistor

Port 0: Thermistor

P3.2

P3.3

P3.4

LIN_TXR_EN

P1_NTC[0]

P0_NTC[0]

Datasheet

25

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Applications

Figure 13 shows the rear seat entertainment (RSE) application block diagram using CCG7D. In the RSE

application, one port is a dedicated charge-only port and the second port is used for charging and streaming

video content to the rear-seat monitor, using a mobile phone, PC, or a tablet. The implementation of the

charging-only port is identical to the RSC application. CCG7D supports display port alternate mode sink in the

port that supports video streaming and controls the external display port multiplexer over I²C. CCG7D also

communicates with the system’s SoC over I²C.

(USB PD, 3.3-21V, 5A)

5 m

V_IN

V_BUS

Battery Input

(9V-18V)

VDDD

0.1μF

68

67

1

2

5

9

7

8

6

11

12 13

17

14

1μF

4

3

PVDD_0

PGND_0

66

CSNI_0

65

61

62

CSPI_0

VIN

5 m

19

20

GND

CC1

CSP_0_GPIO1

GPIO2

VCCD

0.1μF

10

COMP_0

15

16

CC1_0

CC2_0

390pF

69

64

34

GND (EPAD)

GND

CC2

390pF

AGND

HPI_INT

33

CSN_1_GPIO13

Host Processor/

Billboard

DP

HPI_SDA

HPI_SCL

29

30

23

24

DP_0_GPIO5

DM_0_GPIO6

GPIO9

GPIO10

DM

I2CM_SCL

I2CM_SDA

21

22

GPIO3

GPIO4

Display Port

Mux

HPD

18

CSN_0_GPIO0

63

25

VDDD

10μF

VDDD

CYPD7299-68LDXS

0.1μF

1μF

48

49

VDDD

1

2

3

PVDD_1

PGND_1

0.1μF 1μF

AGND

XRES

28

57

56

XRES

5 m

LIN_RX

LIN_TX

SWD_CLK

4

5

32

31

GND

GPIO15

GPIO14

CSP_1_GPIO12

GPIO11

SWD_DAT

LIN_TXR_EN

58

Programming Header

– not needed for final

production

GPIO16

CC1

CC2

37

36

P1_NTC[0]

P0_NTC[0]

59

60

CC1_1

CC2_1

GPIO17

GPIO18

390pF

42

COMP_1

27

26

DP

DP_1_GPIO8

DM_1_GPIO7

LIN_RX

DM

55

54

CSPI_1

CSNI_1

LIN

LIN_TX

Transceiver

LIN_TXR_EN

52

39

35

38

53 51 50

47 43

45 44 46

41 40

VDDD

0.1μF

V_BUS

V_IN

5 m

(USB PD, 3.3-21V, 5A)

Figure 13

CCG7D RSE application diagram

Datasheet

26

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Applications

Table 5

RSE GPIO pin mapping for application diagram in Figure 13

Port 0: Display and charger port

Port 1: Charge only port

Pin #

Pin name

Function

GPIO

RSE

18

CSN_0_GPIO0

Port 0: Hot Plug Detect

P0.0

P0_HPD

Port 0: CSP pin on ground side to implement VBAT

to GND short circuit protection

19

20

21

22

CSP_0_GPIO1

GPIO2

P0.1

P0.2

P0.3

P0.4

P0_VBAT_CSP

P0_VBAT_FET

I2CM_SCL

Port 0: GPIO to disable the FET for VBAT to GND

short circuit protection

I²C Master Clock (SCL) for controlling the Display

port Mux

I²C Master Data (SDA) for controlling the Display

port Mux

GPIO3

GPIO4

I2CM_SDA

23

24

DP_0_GPIO5

DM_0_GPIO6

GPIO, available for system level function

P1.0

P1.1

GPIO

Port 1: USB DM of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

26

27

29

30

31

DM_1_GPIO7

DP_1_GPIO8

GPIO9

P1.2

P1.3

P2.0

P2.1

P1.4

P1_DM

P1_DP

Port 1: USB DP of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

HPI_SDA

[BILLBOARD]

HPI_SCL

[BILLBOARD]

HPI data (SDA)

HPI clock (SCL)

GPIO10

Port 1: GPIO to disable the FET for VBAT to GND

short circuit protection

GPIO11

P1_VBAT_FET

P1_VBAT_CSP

HPI_INT

Port 1: CSP pin on ground side to implement VBAT

to GND short circuit protection

32

33

CSP_1_GPIO12

P1.5

P1.6

CSN_1_GPIO13 HPI INT

LIN TX pin

56

57

GPIO14

Connect to the host programmer’s SWDIO (data) for

programming the CCG7D device

P3.0

P3.1

LIN_TX

LIN_RX

LIN RX pin

GPIO15

Connect to the host programmer’s SWDCLK (clock)

for programming the CCG7D

58

59

60

GPIO16

GPIO17

GPIO18

LIN Transceiver enable

Port 1: Thermistor

Port 0: Thermistor

P3.2

P3.3

P3.4

LIN_TXR_EN

P1_NTC[0]

P0_NTC[0]

Datasheet

27

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Applications

Figure 14 shows a RSC buck application block diagram using CCG7D. This application uses the integrated buck

controller to supply the required voltage and current to the connected device. This application is identical to the

Rear Seat Charger application, except that this application uses only buck topology when compared to the

buck-boost topology in the standard RSC application. In a buck application, the negotiated voltage should

always be lower than the input voltage. If the input voltage drops lower than the output voltage, then the output

voltage will not be maintained and the port will shut down. This application can also be configured to support

the legacy charging protocols – BC1.2 DCP, Qualcomm QC2.0/3.0, Apple charging, and Samsung AFC.

(USB PD, 3.3 V-11 V, 3A)

5 m

V_IN

V_BUS

Battery Input

VDDD

0. 1μF

VDDD

68

67

1

2

5

9

7

8

6

11

12 13

17

14

1μF

4

PVDD_0

PGND_0

66

CSNI_0

3

65

61

62

CSPI_0

VIN

18

CSN_0_GPIO0

5 m

19

20

GND

CC1

CSP_0_GPIO1

GPIO2

VCCD

0. 1μF

10

COMP_0

15

16

CC1_0

CC2_0

390 pF

69

64

34

GND (EPAD)

GND

CC2

390 pF

AGND

29

30

GPIO9

DP

23

24

DP_0_GPIO5

DM_0_GPIO6

GPIO10

DM

21

22

GPIO3

GPIO4

63

25

VDDD

10μF

VDDD

1μF

VDDD

0.1μF

CYPD729X- 68LQXQ

VDDD

AGND

1

2

3

0.1μF 1μF

48

PVDD_1

PGND_1

XRES

28

57

56

49

33

XRES

SWD_CLK

4

CSN_1_GPIO13

GPIO15

GPIO14

5 m

SWD_DAT

5

32

31

37

GND

CSP_1_GPIO12

GPIO11

Programming Header -

GPIO16

58

GPIO16

not needed for final production

CC1

CC2

P1_NTC[0]

P0_NTC[0]

59

60

CC1_1

GPIO17

GPIO18

390 pF

36

CC2_1

42

COMP_1

27

26

DP

DP_1_GPIO8

DM_1_GPIO7

DM

55

54

CSPI_1

CSNI_1

52

51 50

43

45

VDDD

44 46 41

40 39

35

0. 1μF

38

53

47

VDDD

0. 1μF

V_BUS

V_IN

5 m

(USB PD, 3.3-11 V, 3A)

Figure 14

CCG7D RSC buck application diagram

Datasheet

28

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Applications

Table 6

Pin #

RSC buck GPIO pin mapping for application diagram in Figure 14

Pin name

Function

GPIO

RSC

Port 0: CSN pin on ground side to implement VBAT

to GND short circuit protection

18

19

20

CSN_0_GPIO0

P0.0

P0_VBAT_CSN

Port 0: CSP pin on ground side to implement VBAT

to GND short circuit protection

CSP_0_GPIO1

GPIO2

P0.1

P0.2

P0_VBAT_CSP

P0_VBAT_FET

Port 0: GPIO to disable the FET for VBAT to GND

short circuit protection

21

22

GPIO3

GPIO4

GPIO, available for system level function

P0.3

P0.4

GPIO

Port 0: USB DP of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

23

24

26

27

DP_0_GPIO5

DM_0_GPIO6

DM_1_GPIO7

DP_1_GPIO8

P1.0

P1.1

P1.2

P1.3

P0_DP

P0_DM

P1_DM

P1_DP

Port 0: USB DM of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

Port 1: USB DM of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

Port 1: USB DP of Type-C port. Supports BC 1.2, QC,

Apple Charging and AFC

29

30

GPIO9

GPIO, available for system level function

P2.0

P2.1

GPIO

GPIO10

Port 1: GPIO to disable the FET for VBAT to GND

short circuit protection

31

32

GPIO11

P1.4

P1.5

P1_VBAT_FET

P1_VBAT_CSP

Port 1: CSP pin on ground side to implement VBAT

to GND short circuit protection

CSP_1_GPIO12

Port 1: CSN pin on ground side to implement VBAT

to GND short circuit protection

33

56

57

CSN_1_GPIO13

GPIO14

P1.6

P3.0

P3.1

P1_VBAT_CSN

SWDIO

Connect to the host programmer’s SWDIO (data) for

programming the CCG7D device

Connect to the host programmer’s SWDCLK (clock)

for programming the CCG7D

GPIO15

SWDCLK

58

59

60

GPIO16

GPIO17

GPIO18

GPIO, available for system-level function

Port 1: Thermistor

Port 0: Thermistor

P3.2

P3.3

P3.4

GPIO

P1_NTC[0]

P0_NTC[0]

Datasheet

29

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6

Electrical specifications

6.1

Table 7

Absolute maximum ratings

Absolute maximum ratings^[1]

Parameter

Description

Min

Typ

Max

Unit Details/conditions

Maximum input supply

voltage

V_{IN_MAX}

40

Maximum supply voltage

relative to V_SS

Maximum supply voltage

relative to V_SS

V_{DDD_MAX}

V_{5V_MAX}

6

–

V

–

Max V_{BUS_C}(P0/P1) voltage

relative to Vss

Max voltage on CC1 and CC2

pins

V_{BUS_C_MAX}

24

V_{CC_PIN_ABS}

V_{GPIO_ABS}

Inputs to GPIO

V_DDD+ 0.5

–0.5

–25

–

V_{GPIO_OVT_ABS}OVT GPIO voltage

I_{GPIO_ABS}Maximum current per GPIO

6

25

GPIO injection current, Max

mA

V

Absolute max, current

injected per pin

I_{GPIO_INJECTION}for V_IH> V_DDD, and Min for V_IL<

V_SS

–0.5

0.5

–

Electrostatic discharge

ESD_HBM

2000

500

All pins.

human body model

Electrostatic discharge (ESD)

Charged device model

ESD

ESD_CDM

charged device model

LU

T_J

Pin current for latch-up

Junction temperature

–100

–40

100

125

mA

°C

–

Note

1. Usage above the absolute maximum conditions listed in Table 7 may cause permanent damage to the

device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability.

The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High

Temperature Storage Life. When used below absolute maximum conditions but above normal operating

conditions, the device may not operate to specification.

Datasheet

30

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

Table 8

Pin based absolute maximum ratings

Pin #

Pin name

Absolute minimum (V)

Absolute maximum (V)

1

SW1_0

–0.7

–0.5

–0.3

–

35

[2]

2

LG1_0

PVDD + 0.5

0.3

3

PGND_0

PVDD_0

4

VDDD

[2]

5

LG2_0

–0.5

PVDD + 0.5

6

VOUT_0

SW2_0

–0.3

24

7

[2]

8

HG2_0 (wrt SW2_0)

–0.5

–

PVDD + 0.5

9

BST2_0 (wrt SW2_0)

[2]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

COMP_0

–0.5

CSPO_0

CSNO_0

–0.3

–0.5

VBUS_IN_0

VBUS_C_0

CC1_0

24

32

CC2_0

VBUS_CTRL_0

[2]

CSN_0_GPIO0

[2]

CSP_0_GPIO1

[2]

GPIO2

[2]

GPIO3

PVDD + 0.5

[2]

GPIO4

[2]

DP_0_GPIO5

[2]

DM_0_GPIO6

VDDD

–

–0.5

–

6

[2]

DM_1_GPIO7

[2]

DP_1_GPIO8

[2]

XRES

[2]

GPIO9

PVDD + 0.5

[2]

GPIO10

[2]

GPIO11

[2]

CSP_1_GPIO12

[2]

CSN_1_GPIO13

GND

–

Note

2. Max voltage cannot exceed 6 V.

3. Max absolute voltage w.r.t. GND must not exceed 40 V.

Datasheet

31

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2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

Table 8

Pin based absolute maximum ratings (continued)

Pin #

Pin name

VBUS_CTRL_1

CC2_1

Absolute minimum (V)

Absolute maximum (V)

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

32

–0.5

–0.3

CC1_1

VBUS_C_1

VBUS_IN_1

CSNO_1

24

CSPO_1

–0.3

–0.5

–

24

[1]

COMP_1

PVDD + 0.5

[1]

BST2_1 (wrt SW2_1)

[1]

HG2_1 (wrt SW2_1)

–0.5

–0.3

SW2_1

24

VOUT_1

[1]

LG2_1

–0.5

–

PVDD + 0.5

VDDD

PVDD_1

PGND_1

–0.3

–0.5

–0.7

–0.5

–

0.3

[1]

LG1_1

PVDD + 0.5

35

SW1_1

[1, 2]

HG1_1

(wrt SW1_1)

PVDD + 0.5

[1, 2]

BST1_1

CSNI_1

CSPI_1

–0.3

40

[1]

GPIO14/SWD_DAT

GPIO15/SWD_CLK

–0.5

PVDD + 0.5

[1]

GPIO16

[1]

GPIO17

[1]

GPIO18

VIN

VCCD

VDDD

GND

–0.3

–

40

–

6

–

CSPI_0

–0.3

40

CSNI_0

[1, 2]

BST1_0

(wrt SW1_0)

–

–0.5

–

PVDD + 0.5

–

[1, 2]

HG1_0

EPAD

Note

2. Max voltage cannot exceed 6 V.

3. Max absolute voltage w.r.t. GND must not exceed 40 V.

Datasheet

32

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.2

Device-level specifications

All specifications are valid for –40°C  T_A 105°C and T_J 125°C, except where noted. Specifications are valid for

3.0 V to 5.5 V except where noted.

6.2.1

DC specifications

Table 9

DC specifications (operating conditions)

Min

Typ

Max

Unit

Spec ID

SID.PWR#1

Parameter Description

Details/conditions

V

Input supply voltage

4.0

24

IN

Buck boost operating

input supply voltage

SID.PWR#1A

V

5.5

24

IN_BB

VDDD output with V 5.5

IN

SID.PWR#2

V

to 24 V,

4.6

5.5

DDD_REG

–

Max load = 150 mA

V

–

VDDD output with V

4 to 5.5 V,

IN

SID.PWR#3

V

V – 0.2

–

DDD_MIN

IN

Max load = 20 mA

SID.PWR#20 VBUS

VBUS_C_0/1 valid range

3.3

–

21.5

–

Regulated output voltage

(for Core Logic)

SID.PWR#5

SID.PWR#16

SID.PWR#17

V

1.8

100

10

CCD

External regulator voltage

bypass for VCCD

C

80

120

nF

µF

EFC_VCCD

EXC_VDDD

Power supply decoupling

capacitor for V

X5R ceramic

DDD

Bootstrap supply

SID.PWR#18

C

capacitor (BST1_0,

BST1_1, BST2_0, BST2_1)

0.1

EXV

T = 25°C, V = 12 V.

A

IN

–

CC IO IN Transmit or

Receive, no I/O sourcing

current, No VCONN load

Supply current at

0.4 MHz switching

frequency

SID.PWR#24

I

85

mA current, CPU at 24 MHz,

two PD ports active.

Buck-boost converter ON,

3-nF gate driver capaci-

tance.

DD_ACT

Deep Sleep mode

Type-C not attached,

CC enabled for wakeup.

Rp connection should be

µA enabled for both PD ports.

V

= 12 V. CC wakeup on,

IN

SID_DS1

SID_DS2

SID_DS3

I

–

110

50

–

DD_DS1

DD_DS2

Type-C not connected.

T = 25°C.

A

All faults disabled

including VBAT-GND.

USB-PD disabled.

V

= 12 V

Wake-up from GPIO.

IN

T = 25°C.

A

Type-C not attached,

CC enabled for wakeup.

Rp connection should be

enabled for both PD ports.

µA

V

= 12 V. CC wakeup on,

IN

IDD_DS3

450

Type-C not connected.

T = 25°C. All faults

A

disabled except

VBAT-GND.

Datasheet

33

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.2.2

CPU

Table 10

CPU specifications

Spec ID

Parameter Description

Min

Typ

Max Unit Details/conditions

–40°C ≤ T_A≤ +105°C,

SID.CLK#4

F_CPU

CPU input frequency

–

48

MHz

All V_DDD

–

Wakeup from Deep

Sleep mode

External reset pulse

width

SID.PWR#19 T_DEEPSLEEP

SYS.XRES#5 T_XRES

35

–

µs

5

–

Power-up to “Ready to

SYS.FES#1

T_{_PWR_RDY}

accept I²C/CC

5

25

ms

command”

6.2.3

GPIO

Table 11

GPIO DC specifications

Spec ID

Parameter Description

Min

Typ

Max

Unit Details/conditions

Input voltage HIGH

threshold

SID.GIO#9

V_{IH_CMOS}

0.7 × V_DDD

–

CMOS input

V

Input voltage LOW

threshold

Output voltage

HIGH level

SID.GIO#10 V_{IL_CMOS}

–

V_DDD– 0.6

–

0.3 × V_DDD

–

I_OH= –4 mA,

SID.GIO#7

SID.GIO#8

SID.GIO#2

SID.GIO#3

V_{OH_3V}

V_{OL_3V}

Rpu

–

–40°C ≤ T_A≤ +105°C

I_OL= 10 mA,

–40°C ≤ T_A≤ +105°C

Output voltage

LOW level

0.6

Pull-up resistor

when enabled

Pull-down resistor

when enabled

Input leakage

current (absolute

value)

3.5

5.6

8.5

2

k –40°C ≤ T_A≤ +105°C

Rpd

SID.GIO#4

I_IL

nA +25°C T_A, 3-V V_DDD

–

3

–40°C ≤ T_A≤ +105°C,

pF Capacitance on DP, DM

pins

Max pin

capacitance

SID.GIO#5

SID.GIO#6

C_{PIN_A}

C_PIN

22

7

Max pin

capacitance

–40°C ≤ T_A≤ +105°C,

ALL V_DDD, All other I/Os

pF

SID.GIO#11 V_IHTTL

SID.GIO#12 V_ILTTL

LVTTL input

2

–

0.8

V

–40°C ≤ T_A≤ +105°C

Input hysteresis,

–

SID.GIO#13 V_HYSTTL

SID.GIO#14 V_HYSCMOS

100

V_DDD> 2.7 V

–

LVTTL, V_DDD> 2.7 V

–

mV

Input hysteresis

CMOS

0.1 × V_DDD

Datasheet

34

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

Table 12

Spec ID

GPIO AC specifications

Parameter Description

Min

Typ

Max Unit Details/conditions

Rise time in Fast Strong

mode

Fall time in Fast Strong

mode

Rise time in Slow Strong

mode

SID.GIO#16 T_RISEF

SID.GIO#17 T_FALLF

SID.GIO#18 T_RISES

SID.GIO#19 T_FALLS

2

12

ns

10

60

C_load= 25 pF,

–40°C ≤ T_A≤ +105°C

Fall time in Slow Strong

mode

–

GPIO F_OUT

;

SID.GIO#20 F_{GPIO_OUT1}3.0 V V_DDD5.5 V.

16

Fast Strong mode.

GPIO F_OUT

;

SID.GIO#21 F_{GPIO_OUT2}3.0 V V_DDD5.5 V.

–

7

MHz

Slow Strong mode.

GPIO input operating

SID.GIO#22 F_{GPIO_IN}

frequency;

16

–40°C ≤ T_A≤ +105°C

3.0 V V_DDD5.5 V.

Table 13

Spec ID

GPIO OVT DC specifications

Parameter

Details/

Min

Typ Max Unit

Description

conditions

Max / Min current in

to any input or

SID.GPIO_20VT_GIO

#4

GPIO_20VT latch

up current limits

GPIO_20VT_I_LU

–140

140 mA

output, pin-to-pin,

pin-to-supply

SID.GPIO_20VT_GIO

#5

GPIO_20VTpull-up

resistor value

GPIO_20VT_RPU

GPIO_20VT_RPD

–40°C ≤ T ≤ +105°C,

A

3.5

–

8.5

kΩ

GPIO_20VT

pull-down resistor

value

All V

DDD

SID.GPIO_20VT_GIO

#6

GPIO_20VT input

leakage current

(absolute value)

SID.GPIO_20VT_GIO

#16

GPIO_20VT_IIL

+25°C T , 3-V V

2

nA

pF

A

DDD

–

–40°C ≤ T ≤ +105°C,

SID.GPIO_20VT_GIO

#17

GPIO_20VT pin

capacitance

A

GPIO_20VT_CPIN

10

All V

DDD

SID.GPIO_20VT_GIO

#33

GPIO_20VT output

voltage high level.

GPIO_20VT_Voh

I

= -4 mA

= 8 mA

VDDD – 0.6

–

OH

OL

SID.GPIO_20VT_GIO

#36

GPIO_20VT output

voltage low level.

GPIO_20VT_Vol

–

2

–

0.6

–

V

SID.GPIO_20VT_GIO

#41

GPIO_20VT LVTTL

input

GPIO_20VT_Vih_LVTTL

GPIO_20VT_Vil_LVTTL

–40°C ≤ T ≤ +105°C,

A

SID.GPIO_20VT_GIO

#42

GPIO_20VT LVTTL

input

All V

DDD

0.8

Datasheet

35

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

Table 13

Spec ID

GPIO OVT DC specifications ^(continued)

Details/

Min

Typ Max Unit

Parameter

Description

conditions

–40°C ≤ T ≤ +105°C,

SID.GPIO_20VT_GIO

#43

GPIO_20VT input

hysteresis LVTTL

A

GPIO_20VT_Vhysttl

100

–

mV

mA

All V

DDD

GPIO_20VT

V(GPIO_20VT Pin) >

SID.GPIO_20VT_GIO GPIO_20VT_I-

maximum total

sink pin current to

ground

–

95

#45

TOT_GPIO

V

DDD

Table 14

GPIO OVT AC specifications

Details/

Min

Typ Max Unit

Spec ID

Parameter

Description

conditions

GPIO_20VT rise time

in Fast Strong Mode

SID.GPIO_20VT_70

GPIO_20VT_TriseF

1

15

ns

70

GPIO_20VT fall time

in Fast Strong Mode

SID.GPIO_20VT_71

GPIO_20VT_TfallF

GPIO_20VT_TriseS

GPIO_20VT_TfallS

SID.GPIO_20VT_GIO#

46

GPIO_20VT rise time

in Slow Strong Mode

10

SID.GPIO_20VT_GIO#

47

GPIO_20VT fall time

in Slow Strong Mode

All V , C

= 25 pF

DDD load

GPIO_20VT GPIO

–

SID.GPIO_20VT_GIO# GPIO_20VT_FGPI-

48 O_OUT1

Fout; 3 V  V

 5.5

DDD

33

V.

Fast Strong mode.

GPIO_20VT GPIO

SID.GPIO_20VT_GIO# GPIO_20VT_FGPI-

50 O_OUT3

Fout; 3 VV 5.5V.

–

7

8

MHz

DDD

Slow Strong mode.

GPIO_20VT GPIO

input operating

frequency;

SID.GPIO_20VT_GIO# GPIO_20VT_FG-

All V

DDD

52

PIO_IN

3 V V

5.5 V

DDD

6.2.4

XRES

Table 15

XRES DC specifications

Details/

Spec ID

Parameter Description

Min

0.7 × V_DDD

Typ

Max

Unit

conditions

Input voltage HIGH

threshold on XRES pin

Input voltage LOW

threshold on XRES pin

Input capacitance on

XRES pin

Input voltage hysteresis

on XRES pin

SID.XRES#1 V_{IH_XRES}

SID.XRES#2 V_{IL_XRES}

SID.XRES#3 C_{IN_XRES}

SID.XRES#4 V_HYSXRES

–

V

CMOS input

–

0.3 × V_DDD

–

7

–

pF

–

0.05 × V_DDD

mV

Datasheet

36

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.3

Digital peripherals

The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.

6.3.1

Table 16

PWM for GPIO pins

PWM AC specifications

Parameter Description

Operating

Spec ID

Min

Typ

Max Unit Details/conditions

SID.TCPWM.1 TCPWM_FREQ

–

Fc

MHz Fc max = CLK_SYS

frequency

Minimum possible width of

overflow, underflow, and CC

(counter equals compare

value) outputs

Minimum time between

successive counts

Output trigger

pulse width

SID.TCPWM.3 T_PWMEXT

2/Fc

1/Fc

–

ns

Resolution of

counter

SID.TCPWM.4 T_CRES

Minimum pulse width of PWM

output

SID.TCPWM.5 PWM_RES

PWM resolution

6.3.2

I²C

Table 17

Spec ID

SID153

Fixed I²C AC specifications

Parameter Description

Min

Typ

Max

Unit Details/conditions

F_I2C1

Bit rate

–

1

Mbps –

6.3.3

UART

Table 18

Spec ID

SID162

Fixed UART AC specifications

Parameter Description

Min

–

Typ

–

Max

1

Unit Details/conditions

Mbps –

F_UART

Bit rate

6.3.4

SPI

Table 19

Fixed SPI AC specifications

Spec ID

Parameter Description

Min Typ Max Unit Details/conditions

MHz –

SPI operating frequency

(Master; 6X oversampling)

SID166

F_SPI

–

8

Table 20

Spec ID

Fixed SPI Master mode AC specifications

Parameter Description

Min Typ Max Unit Details/conditions

MOSI valid after SClock

SID167

SID168

SID169

T_DMO

–

20

0

15

–

driving edge

MISO valid before SClock

capturing edge

Full clock, late MISO

sampling

Referred to slave

capturing edge

T_DSI

–

ns

–

Previous MOSI data hold

T_HMO

time

Datasheet

37

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

Table 21

Spec ID

Fixed SPI Slave mode AC specifications

Parameter Description Min Typ

Details/

Max

–

Unit

conditions

MOSI valid before

SID170

SID171

T_DMI

T_DSO

40

–

Sclock capturing edge

MISO valid after Sclock

driving edge

48 + (3 × T_CPU

)

T_CPU= 1/F_CPU

–

MISO valid after Sclock

driving edge in Ext Clk

mode

SID171A

T_{DSO_EXT}

–

48

–

ns

Previous MISO data

hold time

SSEL valid to first SCK

Valid edge

–

SID172

T_HSO

0

SID172A

T_SSELSCK

100

6.3.5

Memory

Table 22

Flash AC specifications

Details/

Spec ID

Parameter Description

Min Typ Max Unit

conditions

Row (Block) write time

(erase and program)

SID.MEM#2 FLASH_WRITE

SID.MEM#1 FLASH_ERASE

SID.MEM#5 FLASH_ROW_PGM

20

–40°C ≤ T_A≤ +85°C,

All V_DDD

Row erase time

Row program time after

erase

15.5

ms

7

–

SID178

SID180

T_BULKERASE

T_DEVPROG

Bulk erase time (32 KB)

Total device program

time

35

7.5

–

s

25°C ≤ T_A≤ 55°C,

SID.MEM#6 FLASH__ENPB

Flash write endurance

100k

20

cycles

All V_DDD

Flash retention,

T_A≤ 55°C, 100K P/E cycles

Flash retention,

T_A≤ 85°C, 10K P/E cycles

SID182

F_RET1

F_RET2

–

years

–

SID182A

10

Datasheet

38

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.4

System resources

6.4.1

Power-on-reset (POR) with brown out

Table 23

Imprecise power-on reset (IPOR)

Spec ID

Parameter Description

Min Typ Max Unit Details/conditions

Power-on reset (POR) rising

SID185

SID186

V_RISEIPOR

V_FALLIPOR

0.80

0.70

1.50

1.4

–40°C ≤T_A≤ +105°C,

All V_DDD

trip voltage

–

V

POR falling trip voltage

Table 24

Spec ID

Precise POR

Parameter Description

Min Typ Max Unit Details/conditions

Brown-out detect (BOD) trip

SID190

SID192

V_FALLPPOR

V_FALLDPSLP

voltage in Active/Sleep

modes

1.48

1.1

1.62

1.5

–40°C ≤ T_A≤ +105°C,

All V_DDD

–

V

BOD trip voltage in Deep

Sleep mode

6.4.2

SWD interface

Table 25

SWD interface specifications

Spec ID

Parameter

Description

Min

Typ

Max Unit Details/conditions

SID.SWD#1 F_SWDCLK1

3.0 V  V_DDIO 5.5 V

–

14

MHz

SID.SWD#2 T_SWDI_SETUP

SID.SWD#3 T_SWDI_HOLD

SID.SWD#4 T_SWDO_VALID

SID.SWD#5 T_SWDO_HOLD

0.25 × T

–

T = 1/f SWDCLK

ns

–

1

0.50 × T

–

6.4.3

IMO

Table 26

IMO AC specifications

Spec ID

Parameter Description

Min Typ Max Unit Details/conditions

Frequency variation at

48 MHz (trimmed)

IMO start-up time

IMO frequency

3.0 V ≤ V_DDD< 5.5 V.

SID.CLK#13 F_IMOTOL

±2

7

%

–40°C ≤ T_A≤ 105°C

–

SID226

T_STARTIMO

F_IMO

µs

–40°C ≤ T_A≤ +105°C,

All V_DDD

SID.CLK#1

24

48 MHz

6.4.4

Internal low-speed oscillator

ILO AC specifications

Table 27

Spec ID

SID234

SID238

SID.CLK#5

Parameter Description

Min Typ Max Unit Details/conditions

T_STARTILO1

T_ILODUTY

F_ILO

ILO start-up time

ILO duty cycle

ILO frequency

–

40

20

–

50

40

2

60

ms

%

–40°C ≤ T_A≤ +105°C,

All V_DDD

80 kHz –

Datasheet

39

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.4.5

PD

Table 28

PD DC specifications

Details/

Spec ID

Parameter

Description

Min Typ Max Unit

conditions

Transmitter output High

Voltage

Transmitter output Low

Voltage

SID.DC.cc_shvt.1

SID.DC.cc_shvt.2

vSwing

1.05

–

1.2

V

vSwing_low

0.075

Transmitter output

impedance

Receiver input impedance

Source current for USB

standard advertisement

SID.DC.cc_shvt.3

SID.DC.cc_shvt.4

SID.DC.cc_shvt.5

zDriver

33

10

64

75

–



zBmcRx

Idac_std

M

96

Source current for 1.5 A at

5 V advertisement

Source current for 3 A at

5 V advertisement

SID.DC.cc_shvt.6

SID.DC.cc_shvt.7

Idac_1p5a

Idac_3a

166

304

194

356

µA

Pull down termination

SID.DC.cc_shvt.8

Rd

resistance when acting as

upstream facing port (UFP)

4.59

5.61

k

–

CC impedance to ground

when disabled

CC voltages on DFP

side-standard USB

CC voltages on DFP

side-1.5A

SID.DC.cc_shvt.10 zOPEN

108

0.15

0.35

–

SID.DC.cc_shvt.11 DFP_default_0p2

SID.DC.cc_shvt.12 DFP_1.5A_0p4

0.25

0.45

SID.DC.cc_shvt.13 DFP_3A_0p8

SID.DC.cc_shvt.14 DFP_3A_2p6

CC voltages on DFP side-3 A 0.75

CC voltages on DFP side-3 A 2.45

0.85

2.75

V

CC voltages on UFP

SID.DC.cc_shvt.15 UFP_default_0p66

SID.DC.cc_shvt.16 UFP_1.5A_1p23

0.61

0.7

side-Standard USB

CC voltages on UFP

side-1.5A

1.16

1.31

SID.DC.cc_shvt.17 Vattach_ds

SID.DC.cc_shvt.18 Rattach_ds

SID.DC.cc_shvt.19 VTX_step

Deep sleep attach threshold 0.3

0.6

50

120 mV

%

k

Deep sleep pull-up resistor

TX drive voltage step size

10

80

Datasheet

40

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.4.6

Analog-to-digital converter

ADC DC specifications

Table 29

Spec ID

SID.ADC.1

Parameter Description

Resolution ADC resolution

Min

Typ

Max Unit Details/conditions

–

8

–

Bits –

Reference voltage

SID.ADC.2

SID.ADC.3

SID.ADC.4

SID.ADC.5

SID.ADC.6

INL

Integral non-linearity

–1.5

–2.5

1.5

generated from

bandgap

Differential

non-linearity

Reference voltage

generated from V_DDD

Reference voltage

generated from

bandgap

Reference voltage

generated from V_DDD

Reference voltage

generated from deep

sleep reference

DNL

2.5

1.5

LSB

–

Gain Error

VREF_ADC1

VREF_ADC2

Gain error

–1.5

Reference voltage of

ADC

V_DDDmin

1.96

V_DDDmax

2.04

V

Reference voltage of

ADC

2.0

6.4.7

High-side CSA

Table 30

High-side CSA DC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

CSA accuracy 5 mV < Vsense <

10 mV

SID.HSCSA.1 Csa_Acc1

SID.HSCSA.2 Csa_Acc2

–15

–10

15

10

CSA accuracy 10 mV < Vsense

< 15 mV

CSA accuracy 15 mV < Vsense

< 25 mV

SID.HSCSA.3 Csa_Acc3

SID.HSCSA.4 Csa_Acc4

SID.HSCSA.7 Csa_SCP_Acc1

–5

–3

5

3

–

CSA accuracy 25 mV < Vsense

Active mode

%

CSA SCP at 6 A with 5-mΩ

sense resistor

–10

10

CSA SCP at 10 A with 5-mΩ

sense resistor

SID.HSCSA.8 Csa_SCP_Acc2

SID.HSCSA.9 Csa_OCP_1A

SID.HSCSA.10 Csa_OCP_5A

–10

10

CSA OCP at 1 A with 5-mΩ

sense resistor

104 130 156

123 130 137

CSA OCP for 5 A with 5-mΩ

sense resistor

Datasheet

41

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

Table 31

Spec ID

High-side CSA AC specifications

Parameter Description

Min Typ Max Unit Details/conditions

Delay from SCP

threshold trip to

external NFET power

gate turn off

T_{SCP_GATE}

SID.HSCSA.AC.1

SID.HSCSA.AC.2

3.5

8

1 nF NFET gate

3 nF NFET gate

–

µs

Delay from SCP

threshold trip to

external NFET power

gate turn off

T_{SCP_GATE_1}

6.4.8

UV/OV

Table 32

UV/OV Specifications

Spec ID

Parameter Description

Min Typ Max Unit Details/conditions

Overvoltage threshold

SID.UVOV.1

SID.UVOV.2

SID.UVOV.3

SID.UVOV.4

SID.UVOV.5

V_THOV1

V_THOV2

V_THUV1

V_THUV2

V_THUV3

–3

–3.2

–4

3

3.2

4

Accuracy, 4 V to 11 V

Overvoltage threshold

Accuracy, 11 V to 21.5 V

Undervoltage threshold

Accuracy, 3 V to 3.3 V

Undervoltage threshold

Accuracy, 3.3 V to 4.0 V

Undervoltage threshold

Accuracy, 4.0 V to 21.5 V

–

%

Active mode

–3.5

–3

3.5

3

6.4.9

VCONN switch

Table 33

VCONN switch DC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

VCONN output voltage

with 20 mA load current

Connector side pin

leakage current

DC.VCONN.1 VCONN_OUT

DC.VCONN.2 I_LEAK

4.5

–

5.5

10

V

–

µA

–

VCONN Over-Current

Protection Threshold

DC.VCONN.3 I_OCP

22.5 30 37.5 mA

Table 34

VCONN switch AC specifications

Parameter Description

Spec ID

Min Typ Max Unit Details/conditions

AC.VCONN.1 T_ON

AC.VCONN.2 T_OFF

VCONN switch turn-on time

VCONN switch turn-off time

600

10

–

µs

–

Datasheet

42

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.4.10

V_BUS

Table 35

V_BUSdischarge specifications

Details/

Spec ID

Parameter

R1

Description

Min

500

Typ Max Unit

conditions

20-V NMOS ON

resistance for DS = 1

20-V NMOS ON

resistance for DS = 2

20-V NMOS ON

resistance for DS = 4

20-V NMOS ON

resistance for DS = 8

SID.VBUS.DISC.1

SID.VBUS.DISC.2

SID.VBUS.DISC.3

SID.VBUS.DISC.4

SID.VBUS.DISC.5

2000

1000

R2

250

Measured at

0.5 V

R4

125

500

250

125



–

R8

62.5

31.25

20-V NMOS ON

resistance for DS = 16

R16

When VBUS is

discharged to

5 V

Errorpercentage offinal

VBUS value from setting

SID.VBUS.DISC.6

Vbus_stop_error

–

10

%

6.4.11

Table 36

Spec ID

Voltage regulation

Voltage regulation DC specifications

Parameter Description

Min Typ Max Unit Details/conditions

VBUS_IN output voltage

SID.DC.VR.1 VOUT

SID.DC.VR.2 VR

3.3

–

±3

–

21.5

±5

V

%

V

range

VBUS_IN voltage regulation

accuracy

VINSupplybelowwhichchip

will get reset

–

SID.DC.VR.3 VIN_UVLO

1.7

3.0

Table 37

Spec ID

Voltage regulator specifications

Parameter Description

Min Typ Max Unit Details/conditions

200 µs

Total startup time for the

regulator supply outputs

SID.VREG.1 T_START

–

Datasheet

43

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.4.12

Table 38

Spec ID

VBUS gate driver

VBUS gate driver DC specifications

Parameter Description

Min Typ Max Unit Details/conditions

Gate to source overdrive

GD_VGS

SID.GD.1

SID.GD.2

SID.GD.5

4.5

–

5

10

2

V

NFET driver is ON.

during ON condition

Resistance when pull-down

enabled

Applicable on VBUS_CTRL

to turn off external NFET

GD_RPD

k

–

Programmable typical gate

GD_drv

current

0.3

9.75 µA

–

Table 39

Spec ID

VBUS gate driver AC specifications

Parameter Description

Min Typ Max Unit Details/conditions

VBUS_CTRL Low to High (1 V

SID.GD.3

SID.GD.4

T_ON

to VBUS + 1 V) with 3 nF

external capacitance

2

–

5

7

10 ms V_{BUS_IN}= 5 V

VBUS_CTRL High to Low

(90% to 10%) with 3 nF

external capacitance

T_OFF

–

µs

V_{BUS_IN}= 21.5 V

6.4.13

Table 40

Spec ID

PWM.1

PWM controller

Buck-boost PWM controller specifications

Parameter

Description

Min Typ Max Unit Details/conditions

F_SW

Switching frequency

150

–

600 kHz

Spread spectrum

frequency dithering

span

Buck to buck boost ratio

Boost to buck boost

ratio

PWM.2

FSS

10

%

–

PWM.3

PWM.4

Ratio_Buck_BB

Ratio_Boost_BB

1.16

0.84

–

Datasheet

44

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.4.14

Table 41

Spec ID

NFET gate driver

Buck-boost NFET gate driver specifications

Parameter Description

Top-side gate driver

Min Typ Max Unit Details/conditions

2

DR.1

DR.2

DR.3

DR.4

R_HS_PU

on-resistance - gate pull-up

Top-side gate driver

on-resistance - gate

pull-down

1.5

R_HS_PD

R_LS_PU

R_LS_PD

Ω

Bottom-side gate driver

on-resistance - gate pull-up

Bottom-side gate driver

on-resistance - gate

pull-down

2

1.5

Dead time before high-side

rising edge

Dead time before low-side

rising edge

–

30

DR.5

DR.6

Dead_HS

Dead_LS

Top-side gate driver rise

time

25

20

25

DR.7

DR.8

DR.9

Tr_HS

Tf_HS

Tr_LS

ns

Top-side gate driver fall time

Bottom-side gate driver rise

time

Bottom-side gate driver fall

time

20

DR.10

Tf_LS

6.4.15

Table 42

Spec ID

LS-SCP

LS-SCP DC specifications

Parameter Description

Min Typ Max Unit Details/conditions

Using differential inputs

(CSN_1_GPIO12,

CSP_1_GPIO13 or

CSP_0_GPIO0,

CSN_0_GPIO1)

Using single ended inputs

(CSP_1_GPIO13 or

CSP_0_GPIO0) and internal

ground

Short circuit current

detect @ 6A

SID.LSSCP.DC.1 SCP_6A

SID.LSSCP.DC.1A SCP_6A_SE

SID.LSSCP.DC.2 SCP_10A

SID.LSSCP.DC.2A SCP_10A_SE

5.4

4.5

9

6

6.6

7.5

11

Short circuit current

detect @ 6A

A

Using differential inputs

(CSN_1_GPIO12,

CSP_1_GPIO13 or

CSP_0_GPIO0,

Short circuit current

detect @10A

10

CSN_0_GPIO1)

Using single ended inputs

(CSP_1_GPIO13 or

CSP_0_GPIO0) and internal

ground

Short circuit current

detect @10A

7.5

10 12.5

Datasheet

45

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Electrical specifications

6.4.16

Table 43

Spec ID

Thermal

Thermal specifications

Parameter Description

OTP

Min Typ Max Unit Details/conditions

120 125 130 °C

SID.OTP.1

Thermal shutdown

–

Datasheet

46

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Ordering information

7

Ordering information

Table 44 lists the CCG7D part numbers and features.

Table 44

CCG7D ordering Information

Termination

resistor

Switching

frequency

Package

type

MPN

Application

Role

Rear seat and

DFP (power

source only)

DFP power,

UFP data

CYPD7291-68LDXS

head unit charger

R_P

150 to 600 kHz 68-pin QFN

CYPD7299-68LDXS Rear seat entertainment

7.1

Ordering code definitions

-

X

X X

XX XX

PD

X

XX

X

CY

T = Tape and reel (optional)

Temperature grade:

S = Automotive grade

Lead: X = Pb-free

Package type: LD = QFN wettable flank

Number of pins in the package

Application and feature combination designation

Number of Type-C Ports: 1 = 1 Port, 2 = 2 Port

Product type: 7 = Seventh-generation product family

Marketing code: PD = Power Delivery product family

Company ID: CY = Cypress (an Infineon company)

Datasheet

47

002-28172 Rev. *N

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Packaging

8

Packaging

Table 45

Package characteristics

Parameter Description

Operating junction

Conditions

Min

Typ

Max

Unit

T_J

–40

25

125

°C

temperature

Package _JA

Package _JC

–

T_JA

T_JC

12.1

3.1

–

°C/W

Table 46

Table 47

Solder reflow peak temperature

Maximum time within 5°C

of peak temperature

Package

68-QFN

Maximum peak temperature

260°C

30 seconds

Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2

Package

MSL

68-QFN

MSL 3

Datasheet

48

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Packaging

NOTES:

DIMENSIONS

SYMBOL

e

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. N IS THE TOTAL NUMBER OF TERMINALS.

MIN.

0.30

NOM.

MAX.

0.50

0.50 BSC

68

17

0.40

3

DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED

BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS

THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE

DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.

ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.

N

ND

L

b

D2

E2

D

0.18

5.25

5.40

0.25

5.35

0.30

5.45

5.60

4

5

6

PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.

COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK

SLUG AS WELL AS THE TERMINALS.

5.50

10.00 BSC

E

A

A1

A3

R

10.00 BSC

7. JEDEC SPECIFICATION NO. REF. : N/A.

-

1.00

0.05

0.00

0.203 REF

0.20 TYP

0.35 MIN

K

002-29306 *A

Figure 15

68-QFN package outline

Datasheet

49

002-28172 Rev. *N

2023-01-31

EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Packaging

4.00 0.10

(Po)

0.30 0.05

(T)

2.00 0.10

(P2)

+0.10

-0.00

1.50

(Do)

12.00 0.10

(P1)

1.60 0.10(D1)

"A"

0.18

6.30 0.10

(Ao/BOTTOM)

R0.25

DETAIL "A" (5/1)

002-19972 **

Figure 16

Carrier Tape dimensions

Datasheet

50

002-28172 Rev. *N

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Acronyms

9

Acronyms

Table 48

Acronyms used in this document

Acronym

Description

ADC

AFC

Arm®

BOD

BMC

CC

analog-to-digital converter

Samsung Adaptive Fast Charging

advanced RISC machine, a CPU architecture

brownout detect

biphase mark coding

configuration channel

CDP

CMOS

CPU

CSA

DAC

DCM

DFP

EA

charging downstream port

Complementary Metal Oxide Semiconductor

central processing unit

current sense amplifier

digital-to-analog converter

discontinuous-conduction mode

downstream facing port

error amplifier

EMC

electromagnetic compatibility

electronically marked cable assembly, a USB cable that includes an IC that reports cable

characteristics (e.g., current rating) to the Type-C

EMCA

EMI

EPAD

ESD

electromagnetic interference

exposed pad

electrostatic discharge

FCCM

GPIO

HPI

HSDR

HSIOM

HU

forced continuous current/conduction mode

general-purpose input/output

host processor interface

high-side driver

high-speed I/O matrix

head unit

HUC

I²C, or IIC

IDAC

I/O

ILO

IMO

head unit charger

inter-integrated circuit, a communications protocol

current DAC

input/output, see also GPIO

internal low-speed oscillator

internal main oscillator

IRQ

interrupt request

ISR

interrupt service routine

low-side driver

low-voltage transistor-transistor logic

microcontroller unit

LSDR

LVTTL

MCU

NTC

negative temperature coefficient (refers to a thermistor)

Datasheet

51

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Acronyms

Table 48

Acronyms used in this document ^(continued)

Acronym

Description

OCP

OTP

OVP

PD

overcurrent protection

overtemperature protection

overvoltage protection

power delivery

POR

PPS

PSoC™

PSM

PWM

RCP

RAM

ROM

RSC

power-on reset

programmable power supply

Programmable System-on-Chip™

pulse-skipping mode

pulse-width modulator

reverse current protection

random-access memory

read-only memory

rear-seat charger

RSE

SCB

rear-seat entertainment

serial communications block

SPI

serial peripheral interface, a communications protocol

static random access memory

serial wire debug, a test protocol

timer/counter/PWM

SRAM

SWD

TCPWM

a new standard with a slimmer USB connector and a reversible cable, capable of sourcing

up to 100 W of power

Type-C

UART

UFP

UVP

USB

UVLO

VPA

VPD

WDT

WIC

Universal Asynchronous Transmitter Receiver, a communications protocol

upstream facing port

undervoltage protection

Universal Serial Bus

under-voltage lockout

VCONN-powered accessories

VCONN-powered devices

watchdog timer

wakeup interrupt controller

zero-crossing detector

ZCD

Datasheet

52

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Document conventions

10

Document conventions

10.1

Units of measure

Table 49

Units of measure

Symbol

Unit of measure

°C

Hz

degrees Celsius

hertz

KB

1024 bytes

kHz

k

Mbps

MHz

M

Msps

µA

µF

µs

µV

kilohertz

kilo ohm

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

microsecond

microvolt

µW

mA

m

ms

mV

nA

microwatt

milliampere

milliohm

millisecond

millivolt

nanoampere

nanosecond

ohm

ns



pF

picofarad

ppm

ps

s

parts per million

picosecond

second

sps

samples per second

Datasheet

53

002-28172 Rev. *N

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Revision history

Document

Date

Description of changes

revision

**

2019-08-16

Initial release.

Updated General description, Features, Logic block diagram, Functional

block diagram, and Pin list. Updated Figure 2, Figure 3, and Figure 4.

Added Table of contents, Ordering information and Ordering code defini-

tions sections.

*A

*B

2020-01-09

2020-02-06

Updated CCG7D Functional Block Diagram for Head Unit Charger section as

renamed it as Figure 11.

Updated the title of the document.

Updated General description, Applications, and Features.

Added Figure 9. CCG7D 68-QFN pinout.

Added Packaging section and Figure 15. 68-QFN package outline.

Updated General description and Features.

Added Functional overview and Power subsystem.

Updated document status from ‘Advance’ to ‘Preliminary’.

Updated Figure 9 and Figure 15.

Removed Figure 2, Figure 3, and Figure 4 in the Applications Block Diagram section

from previous revision. Renamed Application Block Diagram section to

Applications.

*C

2020-06-05

Updated Figure 11: Updated application diagram for Head Unit application.

Added application diagrams for Rear-Seat Charger and Rear-Seat Entertainment in

Figure 12 and Figure 13 respectively.

Updated Table 2 in Pin list.

Added Table 3, Table 4, and Table 5 for application specific GPIO pin mapping.

Added Electrical Specifications (Table 7 through Table 43).

Updated Packaging: Added Table 45, Table 46, and Table 47.

Updated Logic block diagram and Features.

Updated Figure 7 and Figure 8.

*D

*E

2020-06-10

2020-08-20

Added CCG7D programming and bootloading.

Updated VCONN switches, VBUS UVP and OVP, VBUS OCP and SCP, Gate

driver for VBUS provider NFET, Legacy charge detection and support,

VBAT to ground short protection, VBUS to CC short protection, USB-PD

subsystem.

Updated descriptions of pins in Table 2.

Updated Table 34 and Table 40.

Updated Functional block diagram.

Updated Pin list:

Updated Table 2.

Updated Applications

Added description.

Updated Electrical specifications

Updated Device-level specifications

Updated DC specifications

Updated Table 9.

*F

2020-09-22

Updated GPIO:

Updated Table 14.

Updated Digital peripherals

Updated PWM for GPIO pins

Updated Table 16.

Datasheet

54

002-28172 Rev. *N

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EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller

Dual-port

Revision history

Document

Date

Description of changes

revision

Added “Confidential” statement in footers across the document.

Updated Logic block diagram.

Updated Electrical specifications

Updated Absolute maximum ratings

Added Table 8.

Updated Applications

Added Figure 14.

Added Table 6.

*G

2021-04-29

Updated Device-level specifications

Updated DC specifications

Updated Table 9.

Updated System resources

Updated VBUS gate driver

Table 38.

Changed status from Preliminary to Final.

Updated Pin list

Updated Table 2.

Updated Electrical specifications

Updated Absolute maximum ratings

Updated Table 7.

Updated Device-level specifications

Updated DC specifications

Updated Table 9.

*H

2021-06-09

Updated System resources

Updated High-side CSA

Updated Table 30.

Updated Applications:

Updated Figure 13.

*I

2021-06-22

2021-07-30

Updated Ordering information

Updated part numbers.

Updated Applications

Updated Figure 11.

Updated Figure 12.

Updated Figure 13.

*J

Updated General description, Features, Functional block diagram and

Functional overview.

*K

2021-09-24

Updated MPN in Figure 13.

Updated Table 11: Added SID.GIO#11 and SID.GIO#12.

Updated Ordering information.

Migrated to Infineon template.

Updated datasheet title.

*L

2022-05-11

Updated to indicate compliance with USB-PD Revision 3.1.

Update external links.

Update list of acronyms.

*M

*N

2022-11-11

2023-01-31

Added package diagram Figure 16 (002-19972 **).

Removed “restricted” status from the datasheet.

Datasheet

55

002-28172 Rev. *N

2023-01-31

Please read the Important Notice and Warnings at the end of this document

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

WARNINGS

The information given in this document shall in no Due to technical requirements products may contain

Edition 2023-01-31

Published by

event be regarded as a guarantee of conditions or dangerous substances. For information on the types

characteristics (“Beschaffenheitsgarantie”).

in question please contact your nearest Infineon

Technologies office.

With respect to any examples, hints or any typical

Infineon Technologies AG

81726 Munich, Germany

values stated herein and/or any information Except as otherwise explicitly approved by Infineon

regarding the application of the product, Infineon Technologies in a written document signed by

Technologies hereby disclaims any and all authorized

representatives

of

Infineon

warranties and liabilities of any kind, including Technologies, Infineon Technologies’ products may

without limitation warranties of non-infringement of not be used in any applications where a failure of the

intellectual property rights of any third party.

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Do you have a question about this

document?

Email:

erratum@infineon.com

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.

Document reference

002-28172 Rev. *N


型号：	CYPD7299-68LDXS
厂家：	Infineon
描述：	EZ-PD™ CCG7D CYPD7299-68LDXS is the tray packing type option belonging to EZ-PD™ CCG7D family of Infineon’s highly integrated dual-port USB-C Power Delivery (PD) with integrated buck-boost controller for automotive in-cabin charger and video applications. 光电二极管
文件：	总56页 (文件大小：581K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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