HYB3118160BST-60 [INFINEON]
1M x 16-Bit Dynamic RAM 1k & 4k -Refresh; 1M ×16位动态RAM 1K与4K -refresh
| 型号： | HYB3118160BST-60 |
| 厂家： | 
Infineon |
| 描述： | 1M x 16-Bit Dynamic RAM 1k & 4k -Refresh |
| 文件： | 总25页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYB3116160BSJ/BST(L)-50/-60/-70
HYB3118160BSJ/BST(L)-50/-60/-70
1M x 16-Bit Dynamic RAM
(1k & 4k -Refresh)
Advanced Information
• 1 048 576 words by 16-bit organization
• 0 to 70 °C operating temperature
• Performance:
-50
50
13
25
90
35
-60
60
15
30
-70
70
20
35
tRAC
tCAC
tAA
RAS access time
ns
ns
ns
CAS access time
Access time from address
Read/Write cycle time
Fast page mode cycle time
tRC
110 130 ns
40 45 ns
tPC
• Single + 3.3 V (± 0.3 V) supply
• Low power dissipation
max. 720 active mW ( HYB3118160BSJ/BST-50)
max. 648 active mW ( HYB3118160BSJ/BST-60)
max. 576 active mW ( HYB3118160BSJ/BST-70)
max. 360 active mW ( HYB3116160BSJ/BST-50)
max. 324 active mW ( HYB3116160BSJ/BST-60)
max. 288 active mW ( HYB3116160BSJ/BST-70)
7.2 mW standby (LV-TTL)
3.6 mW standby (LV-CMOS)
720 µW standby for L-version
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh
• Fast page mode capability
• 2 CAS / 1 WE
• All inputs, outputs and clocks fully LV-TTL-compatible
• 1024 refresh cycles / 16 ms for HYB 3118160BSJ
• 4096 refresh cycles / 64 ms for HYB 3116160BSJ
• Plastic Package:
P-SOJ-42-1 400 mil
P-TSOPII-50/44-1 400mil
Semiconductor Group
1
1.96
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
The HYB 3116(8)160BSJ/BST is a 16 MBit dynamic RAM organized as 1 048 576 words by 16 bits.
The HYB 3116(8)160BSJ/BST utilizes a submicron CMOS silicon gate process technology, as well
as advanced circuit techniques to provide wide operating margins, both internally and for the system
user. Multiplexed address inputs permit the HYB 3116(8)160BSJ/BST to be packaged in standard
SOJ-42 and TSOPII-50/44 plastic package with 400mil width. These packages provide high system
bit densities and are compatible with commonly used automatic testing and insertion equipment.
System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-
performance logic device families.The HYB3116160BSTL parts have a very low power „sleep
mode“ suppported by Self Refresh.
Ordering Information
Type
Ordering Code
on request
on request
on request
on request
on request
on request
on request
on request
on request
on request
on request
on request
Package
Descriptions
HYB 3116160BSJ-50
HYB 3116160BSJ-60
HYB 3116160BSJ-70
HYB 3118160BSJ-50
HYB 3118160BSJ-60
HYB 3118160BSJ-70
HYB 3116160BST-50
HYB 3116160BST-60
HYB 3116160BST-70
HYB 3118160BST-50
HYB 3118160BST-60
HYB 3118160BST-70
P-SOJ-42 400 mil
P-SOJ-42 400 mil
P-SOJ-42 400 mil
P-SOJ-42 400 mil
P-SOJ-42 400 mil
P-SOJ-42 400 mil
P-TSOPII-50/44 400 mil
P-TSOPII-50/44 400 mil
P-TSOPII-50/44 400 mil
P-TSOPII-50/44 400 mil
P-TSOPII-50/44 400 mil
P-TSOPII-50/44 400 mil
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
Pin Names
A0 to A9
A0 to A9
A0 to A11
A0 to A7
RAS
Row Address Inputs for 1k-refresh version HYB3118160BSJ/BST
Column Addess Inputs for 1k-refresh version HYB3118160BSJ/BST
Row Address Inputs for 4k-refresh version HYB3116160BSJ/BST
Column Address Inputs for 4k-refresh version HYB3116160BSJ/BST
Row Address Strobe
OE
Output Enable
I/O1-I/O16
UCAS
LCAS
WE
Data Input/Output
Upper Column Address Strobe
Lower Column Address Strobe
Read/Write Input
VCC
Power Supply (+ 3.3 V)
Ground (0 V)
VSS
N.C.
not connected
Semiconductor Group
2
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
P-SOJ-42 (400 mil)
P-TSOPII-50/44 (400mil)
Vcc
50
49
48
47
46
45
44
43
42
41
40
Vss
1
2
3
4
5
6
7
8
Vcc
1
2
3
4
5
6
7
8
42 Vss
41 I/O16
40 I/O15
39 I/O14
38 I/O13
37 Vss
36 I/O12
35 I/O11
34 I/O10
33 I/O9
32 N.C.
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 Vss
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
N.C.
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
N.C.
N.C.
WE
9
10
11
9
N.C.
10
11
12
13
14
15
16
17
18
19
20
21
N.C.
N.C.
WE
RAS
A11/N.C.
A10.N.C.
A0
A1
A2
A3
Vcc
36
35
34
33
32
31
30
29
28
27
26
N.C.
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
15
16
17
18
19
20
21
22
23
24
25
RAS
A11/NC
A10/NC
A0
A1
A2
A3
Vcc
Vss
*) A11 and A10 are not connected for HYB3118160BSJ/BST (1k-refresh version)
Truth Table
RAS
LCAS UCAS WE
OE
I/O1-I/O8
I/O9-I/O16
Operation
H
H
H
L
H
H
H
L
H
H
H
H
H
L
H
High-Z
High-Z
Standby
L
L
L
L
L
L
L
L
H
L
High-Z
Dout
High-Z
High-Z
Dout
Refresh
Lower byte read
Upper byte read
Word read
H
L
L
High-Z
Dout
L
L
Dout
L
H
L
H
H
H
H
Din
Don't care
Din
Lower byte write
Upper byte write
Word write
H
L
L
Don't care
Din
L
L
Din
L
L
H
High-Z
High-Z
NOP
Semiconductor Group
3
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
I/O16
I/O1 I/O2
WE
&
.
UCAS
LCAS
.
Data in
Buffer
Data out
Buffer
OE
No. 2 Clock
Generator
16
16
Column
Address
Buffer(8)
8
Column
Decoder
8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
16
Sense Amplifier
I/O Gating
Controller
Refresh
Counter (12)
256
x16
12
A10
A11
Row
Address
Buffers(12)
Row
Decoder
Memory Array
4096x256x16
12
12
4096
No. 1 Clock
Generator
RAS
Block Diagram for HYB 3116160BSJ
Semiconductor Group
4
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
I/O16
I/O1 I/O2
WE
&
.
UCAS
LCAS
.
Data in
Buffer
Data out
Buffer
OE
No. 2 Clock
Generator
16
16
Column
Address
Buffer(10)
10
Column
Decoder
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
16
Sense Amplifier
I/O Gating
Controller
Refresh
Counter (10)
1024
x16
10
Row
Address
Buffers(10)
Row
Memory Array
1024x1024x16
10
10
1024
Decoder
No. 1 Clock
Generator
RAS
Block Diagram for HYB 3118160BSJ
Semiconductor Group
5
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Soldering time.............................................................................................................................10 s
Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage..................................................................................................-0.5 V to 4.6 V
Power dissipation..................................................................................................................... 1.0 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics (values in brackets for HYB3116160BSJ)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Vcc+0.5
0.8
1)
1)
1)
1)
1)
1)
1)
Input high voltage
VIH
VIL
2.0
V
Input low voltage
– 0.5
2.4
V
TTL Output high voltage (IOUT = – 2 mA)
TTL Output low voltage (IOUT = 2 mA)
CMOS Output high voltage (IOUT = – 100 µA)
CMOS Output low voltage (IOUT = 100 µA)
VOH
VOL
VOH
VOL
II(L)
–
V
–
0.4
V
Vcc-0.2
–
–
V
0.2
V
Input leakage current,any input
– 10
10
µA
(0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V)
1)
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V)
IO(L)
ICC1
– 10
10
µA
Average VCC supply current:
-50 ns version
2) 3) 4)
2) 3) 4)
2) 3) 4)
–
–
–
200(100) mA
180 (90) mA
160 (80) mA
-60 ns version
-70 ns version
(RAS, CAS, address cycling, tRC = tRC min.)
Standby VCC supply current (RAS = CAS = VIH) ICC2
–
2
mA
–
Semiconductor Group
6
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
DC Characteristics (values in brackets for HYB3116160BSJ) (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, tT = 5 ns
Parameter Symbol
Limit Values
Unit Test
Condition
min.
max.
Average VCC supply current, during RAS-only ICC3
2) 4)
2) 4)
2) 4)
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
–
–
–
200(100) mA
180 (90) mA
160 (80) mA
(RAS cycling: CAS = VIH, tRC = tRC min.)
Average VCC supply current,
ICC4
2) 3) 4)
2) 3) 4)
2) 3) 4)
during fast page mode:
-50 ns version
-60 ns version
-70 ns version
–
–
–
55 (40)
50 (35)
45 (30)
mA
mA
mA
(RAS = VIL, CAS, address cycling, tPC = tPC min.)
1)
1)
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
ICC5
ICC6
–
–
1
mA
Standby VCC supply current (L-version)
(RAS = CAS = VCC – 0.2 V)
200
µA
Average VCC supply current, during CAS-
before-RAS refresh mode: -50 ns version
-60 ns version
2) 4)
2) 4)
2) 4)
–
–
–
200(100) mA
180 (90) mA
160 (80) mA
-70 ns version
(RAS, CAS cycling, tRC = tRC min.)
Average Self Refresh Current
ICC7
_
1
mA
(CBR cycle with tRAS>TRASSmin., CAS held low,
WE=Vcc-0.2V, Address and Din=Vcc--0.2V or 0.2V)
250
µA
L-version
Capacitance
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11)
CI1
–
–
–
5
7
7
pF
pF
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2
I/O capacitance (I/O1-I/O16)
CIO
Semiconductor Group
7
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
5)6)
16F
AC Characteristics
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
common parameters
Random read or write cycle time tRC
90
30
50
13
0
–
110
40
60
15
0
–
130
50
70
20
0
–
ns
ns
ns
ns
ns
ns
ns
ns
RAS precharge time
RAS pulse width
tRP
–
–
–
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
10k
10k
–
10k
10k
–
10k
10k
–
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
8
–
10
0
–
10
0
–
0
–
–
–
10
18
13
–
15
20
15
–
15
20
15
–
37
25
45
30
50
35
RAS to column address delay
time
ns
RAS hold time
tRSH
tCSH
tCRP
tT
13
50
5
15
60
5
–
20
70
5
–
ns
ns
ns
CAS hold time
–
–
CAS to RAS precharge time
Transition time (rise and fall)
–
–
–
3
50
16
64
256
3
50
16
64
256
3
50
16
64
ns
7
Refresh period for HYB3118160 tREF
Refresh period for HYB3116160 tREF
–
–
–
ms
ms
–
–
–
Refresh period for L-versions
tREF
–
–
–
256 ms
Read Cycle
Access time from RAS
Access time from CAS
tRAC
tCAC
–
50
13
25
13
–
–
60
15
30
15
–
–
70
20
35
20
–
ns 8, 9
ns 8, 9
ns 8,10
ns
–
–
–
Access time from column address tAA
–
–
–
OE access time
tOEA
–
–
–
Column address to RAS lead time tRAL
25
0
30
0
35
0
ns
Read command setup time
Read command hold time
tRCS
tRCH
tRRH
–
–
–
ns
0
–
0
–
0
–
ns 11
ns 11
Read command hold time
referenced to RAS
0
–
0
–
0
–
Semiconductor Group
8
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
5)6)
16F
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
CAS to output in low-Z
tCLZ
tOFF
0
0
0
–
0
0
0
–
0
0
0
–
ns
8
Output buffer turn-off delay
13
13
15
15
20
20
ns 12
ns 12
Output buffer turn-off delay from tOEZ
OE
Data to OE low delay
CAS high to data delay
OE high to data delay
tDZO
tCDD
tODD
0
–
–
–
0
–
–
–
0
–
–
–
ns 13
ns 14
ns 14
13
13
15
15
20
20
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
tWCH
tWP
8
–
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
–
ns
8
ns
tWCS
0
ns 15
ns
Write command to RAS lead time tRWL
Write command to CAS lead time tCWL
13
13
0
15
15
0
20
20
0
ns
Data setup time
tDS
ns 16
ns 16
ns 13
Data hold time
tDH
10
0
10
0
15
0
Data to CAS low delay
tDZC
Read-Modify-Write Cycle
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
tRWC
tRWD
tCWD
126
68
31
43
13
–
–
–
–
–
150
80
–
–
–
–
–
180
95
–
–
–
–
–
ns
ns 15
ns 15
ns 15
ns
35
45
Column address to WE delay time tAWD
50
60
OE command hold time
tOEH
15
20
Fast Page Mode Cycle
Fast page mode cycle time
CAS precharge time
tPC
tCP
35
10
–
–
40
10
–
–
45
10
–
–
ns
ns
–
–
–
Access time from CAS precharge tCPA
30
35
40
ns
7
RAS pulse width
tRAS
50
200k 60
200k 70
200k ns
Semiconductor Group
9
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
5)6)
16F
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 5 ns
Symbol
Unit Note
Parameter
Limit Values
-60
-50
-70
min. max. min. max. min. max.
CAS precharge to RAS Delay
tRHPC
30
–
35
–
40
–
ns
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle tPRWC
time
71
–
–
80
55
–
–
95
65
–
–
ns
ns
CAS precharge to WE
tCPWD
48
CAS-before-RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
10
10
10
10
10
10
Write hold time referenced to RAS tWRH
CAS-before-RAS Counter Test Cycle
CAS precharge time
tCPT
35
–
40
–
40
–
ns
Self Refresh Cycle
RAS pulse width
RAS precharge time
CAS hold time
tRASS
tRPS
tCHS
100k _
100k _
100k _
ns 17
ns 17
ns 17
95
_
_
110
-50
_
_
130
-50
_
_
-50
Semiconductor Group
10
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 100 pF and at Voh=2.0 V (Ioh = -2mA) , Vol=0.8V (Iol=2mA).
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13)Either tDZC or tDZO must be satisfied.
14)Either tCDD or tODD must be satisfied.
15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of
the I/O pins (at access time) is indeterminate.
16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh.
Semiconductor Group
11
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRSH
tCAS
tRCD
V
IH
UCAS
LCAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
V
IH
Column
Row
Row
Address
WE
V
IL
tRCH
tRAH
tRCS
tRRH
V
IH
V
IL
tAA
tOEA
V
IH
OE
V
IL
tCDD
tDZC
tODD
tDZO
V
IH
I/O
(Inputs)
V
tCAC
tCLZ
IL
tOFF
tOEZ
V
OH
I/O
(Outputs)
Hi Z
Valid Data Out
Hi Z
V
OL
tRAC
WL1
“H” or “L”
Read Cycle
Semiconductor Group
12
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
UCAS
LCAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
Address
WE
V
IL
tCWL
tRAH
tWCS
V
tWP
IH
V
IL
tWCH
tRWL
V
IH
OE
V
IL
tDH
tDS
V
IH
I/O
(Inputs)
Valid Data In
V
IL
V
OH
I/O
(Outputs)
Hi Z
V
OL
WL2
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
13
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCSH
tCRP
tRCD
tRSH
tCAS
V
IH
UCAS
LCAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
.
V
IH
Row
Row
Column
Address
WE
V
IL
tCWL
tRWL
tWP
tRAH
V
IH
V
IL
tOEH
V
IH
OE
V
tODD
tDS
tOEZ
IL
tDH
tDZO
tDZC
V
IH
I/O
(Inputs)
Valid Data
V
IL
tCLZ
tOEA
V
OH
Hi-Z
Hi-Z
I/O
(Outputs)
V
OL
WL3
“H” or “L”
Write Cycle (OE Controlled Write)
Semiconductor Group
14
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRWC
tRAS
tRP
V
IH
RAS
tCSH
V
IL
tRSH
tCAS
tRCD
tCRP
V
IH
V
UCAS
LCAS
IL
tRAH
tCAH
tASR
tASC
tASR
V
IH
Address
Row
Column
Row
V
IL
tCWL
tRWL
tWP
tAWD
tRAD
tCWD
tRWD
V
IH
WE
OE
V
IL
tAA
tRCS
tOEH
tOEA
V
IH
V
IL
tDS
tDH
tDZO
tDZC
V
IH
Valid
Data in
I/O
(Inputs)
V
IL
tCLZ
tCAC
tODD
tOEZ
V
OH
I/O
(Outputs)
Data
Out
V
OL
tRAC
“H” or “L”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
15
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRP
tRASP
V
IH
RAS
V
IL
tRHCP
tPC
tCAS
tCP
tCAS
tRCD
tRSH
tCAS
tCRP
V
IH
UCAS
LCAS
V
IL
tCSH
tCAH
tRAH
tCAH
tCAH
tASR
tASC
tASR
tASC
tASC
V
IH
Column
Column
Row
Row
Column
Address
V
IL
tRAD
tRCS
tRCH
tRCH
tRCS
tRCS
V
IH
WE
V
IL
tRRH
tCPA
tAA
tCPA
tAA
tOEA
tAA
tOEA
tOEA
V
IH
OE
V
IL
tDZC
tDZC
tDZO
tDZC
tCDD
tODD
tDZO
tDZO
tODD
tODD
V
IH
I/O
(Inputs)
V
IL
tCAC
tCLZ
tCAC
tOFF
tCAC
tOFF
tOFF
tRAC
tOEZ
tOEZ
tOEZ
tCLZ
tCLZ
V
OH
I/O
(Outputs)
Valid
Data Out
Valid
Data Out
Valid
Data Out
V
OL
“H” or “L”
FPM1
Fast Page Mode Read Cycle
Semiconductor Group
16
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRP
tRAS
V
IH
RAS
V
IL
tRSH
tCAS
tPC
tCAS
tRCD
tCP
tCAS
tCRP
V
IH
CAS
V
IL
tRAL
tCAH
tRAH
tCAH
tCAH
tASR
tASR
tASC
tASC
tASC
V
IH
Address
Column
Column
Row
Column
Column
V
IL
tCWL
tCWL
tWCH
tWP
tRAD
tWCS
tCWL
tWCH
tWP
tRWL
tWCS
tWCS
tWCH
tWP
V
IH
WE
OE
V
IL
V
IH
V
IL
tDH
tDH
tDH
tDS
tDS
tDS
V
IH
I/O
(Inputs)
Valid
Data In
Valid
Data In
Valid
Data In
V
IL
V
OH
I/O
(Outputs)
HI-Z
V
OL
“H” or “L”
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
17
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
SAR
RP
t
t
P
RC
t
L
L
WR
WC
t
t
PW
HD
EOH
t
t
t
L
SD
D
t
H
S
AR
t
DO
EOZ
S
t
t
t
AC
t
D
W
D
WCD
t
WA
C
A
A
t
H
Z
PC
t
t
AC
PC
LC
AC
t
t
t
t
A
t
C
SAC
ZD
L
t
t
WC
t
EOH
HD
PW
t
t
t
C
W
SD
S
t
D
S
RA
RP
t
t
OD
AC
t
EOZ
t
D
t
D
D
W
WC
t
WA
t
H
Z
PC
EOA
t
t
AC
LC
t
t
A
A
t
PC
C
t
ZD
SAC
t
t
PC
t
WCL
t
PW
t
EOH
HD
t
t
SD
t
D
OEZ
t
DO
D
t
S
AC
WC
t
t
D
D
C
EOA
H
WA
WR
Z
t
t
H
t
AC
t
AC
LC
t
A
t
SC
t
t
O
SAC
t
ZD
t
C
C
S
D
ZD
AR
t
CR
t
t
CR
t
D
AR
H
t
AR
t
SAR
t
Fast Page Mode Read-Modify- Write Cycle
Semiconductor Group
18
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRC
tRAS
tRP
V
IH
RAS
V
IL
tCRP
tRPC
V
IH
CAS
V
IL
tRAH
tASR
tASR
V
IH
Address
Row
Row
V
IL
V
OH
I/O
(Outputs)
HI-Z
V
OL
“H” or “L”
WL9
RAS-Only Refresh Cycle
Semiconductor Group
19
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRC
tRP
tRP
tRAS
V
IH
RAS
V
IL
tRPC
tCP
tCSR
tCRP
tRPC
tCHR
V
IH
UCAS
LCAS
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
tOEZ
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
ODD
t
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
“H” or “L”
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
20
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRC
tRC
tRP
tRP
tRAS
tRAS
V
IH
RAS
V
IL
tRSH
tRCD
tCRP
tCHR
V
IH
UCAS
LCAS
V
tRAD
IL
tWRP
tASC
tASR
tRAH
tWRH
tCAH
tASR
V
IH
Column
Address
Row
Row
V
IL
tRRH
tRCS
V
IH
WE
OE
V
IL
tAA
tOEA
V
IH
V
IL
tDZC
tDZO
tCDD
tODD
V
IH
I/O
(Inputs)
V
IL
tCAC
tOFF
tCLZ
tOEZ
tRAC
V
OH
I/O
(Outputs)
Valid Data Out
HI-Z
V
OL
WL11
“H” or “L”
Hidden Refresh Cycle (Read)
Semiconductor Group
21
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRC
tRC
tRP
tRP
tRAS
V
tRAS
IH
RAS
V
IL
tRCD
tRSH
tCHR
tCRP
V
IH
UCAS
LCAS
tRAD
V
IL
tRAH
tASR
tASC
tCAH
tASR
V
IH
Address
WE
Row
Column
Row
V
IL
tWCS
tWRP tWRH
tWCH
tWP
V
IH
V
IL
tDS
tDH
V
IH
I/O
(Input)
Valid Data
V
IL
V
OH
I/O
(Output)
HI-Z
V
OL
“H” or “L”
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
22
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRP
tRASS
tRPS
V
IH
RAS
CAS
V
IL
tRPC
tCP
tCRP
tCHS
tCSR
V
IH
V
IL
tWRP
tWRH
V
IH
WE
OE
V
IL
V
IH
V
IL
tCDD
V
IH
I/O
(Inputs)
V
IL
ODD
t
tOEZ
V
OH
I/O
(Outputs)
HI-Z
V
OL
tOFF
WL13
“H” or “L”
CAS before RAS Self Refresh Cycle
Semiconductor Group
23
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
tRP
tRAS
Read Cycle:
RAS
V
IH
IL
V
tRSH
tCAS
tCP
tCHR
tCSR
CAS
V
IH
V
tRAL
IL
tASR
tASC tCAH
Column
tAA
V
IH
IL
Address
WE
Row
V
tWRP
tRRH
tRCH
V
IH
IL
tCAC
V
tWRH
tOEA
tRCS
V
IH
IL
OE
V
tCDD
tDZC
V
tODD
I/O
IH
IL
(Inputs)
V
tDZO
tOFF
tCLZ
tOEZ
Out
V
I/O
(Outputs)
OH
OL
Data
V
tWCS
tWRP
tRWL
tCWL
tWCH
Write Cycle:
WE
V
IH
IL
V
tWRH
V
V
IH
IL
OE
tDS
tDH
I/O
(Inputs)
V
IH
IL
Data In
V
I/O
(Outputs)
V
IH
HI-Z
V
IL
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
24
HYB3116(8)160BSJ/BST(L)-50/-60/-70
3.3V 1M x 16-DRAM
Package Outlines
Plastic Package P-SOJ-42 (400 mil)
(Small Outline J-lead, SMD)
1)
10.3
-0.3
B
0.81 m a x.
1.27
+
0.25
9.4
-
+
0.1
0.43
-
0.08
+
0.18
0.15
A 42x
25.4
11.2
-
0.18
B
42
22
21
G PJ05853
1
1)
A
27.43
-0.25
Ind e x m a rking
1) d o e s no t inc lud e p la stic o r m e ta l p ro tusio n o f 0.15 m a x p e r sid e
Plastic Package P-TSOPII-50/44 (400 mil)
(Thin Small Outline, SMD, 0.8 mm lead pitch)
Semiconductor Group
25
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