HYM322005GS-60 [INFINEON]
2M x 32-Bit Dynamic RAM Module; 2M ×32位动态RAM模块
| 型号： | HYM322005GS-60 |
| 厂家： | 
Infineon |
| 描述： | 2M x 32-Bit Dynamic RAM Module |
| 文件： | 总10页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2M × 32-Bit Dynamic RAM Module
HYM 322005S/GS-50/-60
(Hyper Page Mode - EDO Version)
• SIMM modules with 2 097 152 words by 32-bit organization
for PC main memory application
• Fast access and cycle time
50 ns access time
84 ns cycle time (-50 version)
60 ns access time
104 ns cycle time (-60 version)
• Hyper page mode - EDO capability with
20 ns cycle time (-50 version)
25 ns cycle time (-60 version)
• Single + 5 V (± 10 %) supply
• Low power dissipation
max. 2200 mW active (-50 version)
max. 1980 mW active (-60 version)
CMOS – 22 mW standby
TTL
– 44 mW standby
• CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh
• 4 decoupling capacitors mounted on substrate
• All inputs, outputs and clock fully TTL compatible
• 72 pin Single in-Line Memory Module
• Utilizes four 1M × 16 -DRAMs in SOJ-42 packages
• 1024 refresh cycles / 16 ms
• Optimized for use in byte-write non-parity applications
• Tin-Lead contact pad HYM 322005S
• Gold-Lead contact pad HYM 322005GS
• single sided module with 20.32 mm (800 mil) height
Semiconductor Group
1
9.96
HYM 322005S/GS-50/-60
2M × 32-Bit EDO-Module
The HYM 322005S/GS-50/-60 is a 8 MByte EDO - DRAM module organized as 2 097 152 words by
32-bit in a 72-pin single-in-line package comprising four HYB 5118160BSJ 1M × 16 EDO - DRAMs
in 400 mil wide SOJ-packages mounted together with four 0.2 µF ceramic decoupling capacitors on
a PC board.
Each HYB 5118165BSJ is described in the data sheet and is fully electrically tested and processed
according to Siemens standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use presence detect pins.
The common I/O feature on the HYM 322005S/GS-50/-60 dictates the use of early write cycles.
Ordering Information
Type
Ordering Code
Package
Descriptions
HYM 322005S-50
Q67100-Q2066
L-SIM-72-10
EDO - DRAM module
(access time 50 ns)
HYM 322005S-60
HYM 322005GS-50
HYM 322005GS-60
Q67100-Q2067
Q67100-Q2068
Q67100-Q2069
L-SIM-72-10
L-SIM-72-10
L-SIM-72-10
EDO - DRAM module
(access time 60 ns)
EDO - DRAM module
(access time 50 ns)
EDO - DRAM module
(access time 60 ns)
Semiconductor Group
2
HYM 322005S/GS-50/-60
2M × 32-Bit EDO-Module
Pin Names
VSS
1 DQ0
2
4
6
8
DQ16 3 DQ1
DQ17 5 DQ2
DQ18 7 DQ3
DQ19 9 VCC 10
N.C.
A1
A3
A5
N.C.
A0-A9
Address Inputs
DQ0-DQ31
CAS0 - CAS3
RAS0 - RAS3
WE
Data Input/Output
Column Address Strobe
Row Address Strobe
Read/Write Input
Power (+ 5 V)
11 A0
13 A2
15 A4
17 A6
12
14
16
18
19 DQ4 20
DQ20 21 DQ5 22
DQ21 23 DQ6 24
DQ22 25 DQ7 26
VCC
VSS
Ground
DQ23 27 A7
28
29 VCC 30
31 A9 32
N.C.
A8
PD
Presence Detect Pin
No Connection
RAS3 33 RAS2 34
N.C.
N.C.
35 N.C. 36
N.C.
VSS
37 N.C. 38
39 CAS0 40
CAS2 41 CAS3 42
CAS1 43 RAS0 44
RAS1 45 N.C. 46
Presence Detect Pins
WE
DQ8
DQ9
47 N.C. 48
49 DQ24 50
51 DQ25 52
-50
-60
DQ10 53 DQ26 54
DQ11 55 DQ27 56
DQ12 57 DQ28 58
VCC 59 DQ29 60
DQ13 61 DQ30 62
DQ14 63 DQ31 64
DQ15 65 N.C. 66
PD0
PD1
PD2
PD3
N.C.
N.C.
VSS
N.C.
N.C
N.C.
N.C.
VSS
PD0
PD2
N.C.
67 PD1 68
69 PD3 70
71 VSS 72
Pin Configuration
Semiconductor Group
3
HYM 322005S/GS-50/-60
2M × 32-Bit EDO-Module
RAS1
RAS0
CAS0
CAS1
UCAS LCAS RAS
I/O1-I/O8
UCAS LCAS RAS
I/O1-I/O8
DQ0-DQ7
I/O9-I/O16
I/O9-I/O16
OE
DQ8-DQ15
OE
D3
D1
RAS3
RAS2
CAS2
CAS3
UCAS LCAS RAS
I/O1-I/O8
UCAS LCAS RAS
I/O1-I/O8
DQ16-DQ23
DQ24-DQ31
I/O9-I/O16
OE
I/O9-I/O16
OE
D2
D4
A0 - A9
WE
D1 - D4
D1 - D4
VCC
VSS
C1 -C4
Block Diagram
Semiconductor Group
4
HYM 322005S/GS-50/-60
2M × 32-Bit EDO-Module
Absolute Maximum Ratings
Operating temperature range ......................................................................................... 0 to + 70 °C
Storage temperature range...................................................................................... – 55 to + 125 °C
Input/output voltage ........................................................................................................ – 1to + 7 V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation................................................................................................................... 2.52 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Vcc+0.5
0.8
1)
1)
1)
1)
1)
Input high voltage
VIH
VIL
2.4
– 0.5
2.4
–
V
Input low voltage
V
Output high voltage (IOUT = – 5 mA)
Output low voltage (IOUT = 4.2 mA)
VOH
VOL
II(L)
–
V
0.4
V
Input leakage current
– 10
10
µA
(0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V)
1)
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V)
IO(L)
ICC1
– 10
10
µA
Average VCC supply current:
-50 ns version
2) 3) 4)
2) 3) 4)
–
–
400
360
mA
mA
-60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
Standby VCC supply current
(RAS = CAS = VIH)
ICC2
–
8
mA
–
Average VCC supply current, during RAS-only ICC3
2) 4)
2) 4)
refresh cycles:
-50 ns version
–
–
400
360
mA
mA
-60 ns version
(RAS cycling, CAS = VI,H, tRC = tRC min.)
Average VCC supply current,during hyper page ICC4
2) 3) 4)
2) 3) 4)
mode (EDO):
-50 ns version
–
–
180
150
mA
mA
-60 ns version
(RAS = VIL, CAS, address cycling:
(tHPC = tHPC min.)
Semiconductor Group
5
HYM 322005S/GS-50/-60
2M × 32-Bit EDO-Module
DC Characteristics (contd’ )
TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
1)
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
ICC6
–
4
mA
Average VCC supply current, during CAS-
before-RAS refresh mode: -50 ns version
-60 ns version
2) 4)
2) 4)
–
–
400
360
mA
mA
(RAS, CAS cycling: tRC = tRC min.)
Capacitance
TA = 0 to 70 °C; VCC = 5 V ± 10 %; f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
35
Input capacitance (A0 to A9)
Input capacitance (RAS0, RAS2)
Input capacitance (CAS0-CAS3)
Input capacitance (WE)
CI1
CI2
CI3
CI4
CIO1
–
–
–
–
–
pF
pF
pF
pF
pF
20
20
35
I/O capacitance (DQ0-DQ31)
25
Semiconductor Group
6
HYM 322005S/GS-50/-60
2M × 32-Bit EDO-Module
5)6)
AC Characteristics
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-50 -60
min. max. min. max.
common parameters
Random read or write cycle time
RAS precharge time
tRC
84
30
50
8
–
104
40
60
10
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRP
–
–
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
10k
10k
–
10k
10k
–
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
0
8
–
10
0
–
0
–
–
8
–
10
14
12
15
50
5
–
12
10
13
40
5
37
25
45
30
–
CAS hold time
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
1
50
16
1
50
16
ns
7
tREF
–
–
ms
Read Cycle
Access time from RAS
tRAC
tCAC
tAA
–
50
13
25
–
–
60
15
30
–
ns
ns
ns
ns
ns
ns
ns
8, 9
8, 9
8,10
Access time from CAS
–
–
Access time from column address
Column address to RAS lead time
Read command setup time
Read command hold time
–
–
tRAL
tRCS
tRCH
tRRH
25
0
30
0
–
–
0
–
0
–
11
11
Read command hold time referenced to
RAS
0
–
0
–
CAS to output in low-Z
tCLZ
tOFF
0
0
–
0
0
–
ns
ns
8
Output buffer turn-off delay
13
15
12
Semiconductor Group
7
HYM 322005S/GS-50/-60
2M × 32-Bit EDO-Module
5)6)
AC Characteristics (contd’ )
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns
Symbol
Unit Note
Parameter
Limit Values
-50 -60
min. max. min. max.
Early Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
tWCH
tWP
8
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
ns
8
tWCS
tRWL
tCWL
tDS
0
ns
ns
ns
ns
ns
13
13
13
0
15
15
0
14
14
Data hold time
tDH
8
10
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
CAS precharge time
tHPC
tCP
20
8
–
25
10
–
–
ns
ns
ns
ns
–
–
Access time from CAS precharge
Output data hold time
tCPA
tCOH
tRAS
tRHCP
–
27
–
32
–
7
5
5
RAS pulse width in hyper page mode
CAS precharge to RAS Delay
50
27
200k 60
200k ns
–
32
–
ns
CAS before RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
tWRH
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
10
10
10
10
Semiconductor Group
8
HYM 322005S/GS-50/-60
2M × 32-Bit EDO-Module
Notes
1) All voltages are referenced to VSS.
Vil may undershoot to -2.0 V for pulse width of less than or equal to 4 ns. Pulse width is measured at 50%
points with amplitude measured peak to the DC reference.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle.
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of tRAC, tCAC, tAA,tCPA. tCAC is measured from tristate.
.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC
.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA
11) Either tRCH or tRRH must be satisfied for a read cycle.
.
12) tOFF (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to
output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
13) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only.
If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance)
through the entire cycle.
14) These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM 322005S/GS-50/-60
2M × 32-Bit EDO-Module
L-SIM-72-10
Module package
(single in-line memory module)
GLS58332
Semiconductor Group
10
相关型号：
©2020 ICPDF网 联系我们和版权申明