HYS72T64020GR-5-A [INFINEON]
DDR2 Registered DIMM Modules; 注册DDR2 DIMM模块
| 型号： | HYS72T64020GR-5-A |
| 厂家： | 
Infineon |
| 描述： | DDR2 Registered DIMM Modules |
| 文件： | 总24页 (文件大小：696K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V0.22,Feb. 2004
HYS72T32000GR (256 MByte)
HYS72T64001GR (512 MByte)
HYS72T64020GR (512 MByte)
DDR2 Registered DIMM Modules
Memory Products
N e v e r s t o p t h i n k i n g .
HYS72T32000GR, HYS72T64001GR
HYS72T64020GR
Preliminary Datasheet Rev. 0.22 (2.04)
Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet
256 MByte & 512 MByte Modules
PC2-3200R /-4200R /-5300R
•
240-pin Registered 8-Byte ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation
and Server main memory applications
•
•
Re-drive for all input signals using register
and PLL devices.
OCD (Off-Chip Driver Impedance
•
•
One rank 32Mb x 72, 64Mb x 72 and
two ranks 64Mb × 72 organizations
Adjustment) and ODT (On-Die Termination)
•
•
Serial Presence Detect with E2PROM
JEDEC standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with
+ 1.8 V (± 0.1 V) power supply
Low Profile Modules form factor:
133.35 mm x 30,00 mm (MO-237)
•
Based on JEDEC standard reference card
designs Raw Card “A”, “B” and “C”.
•
•
Modules built with 256 Mb DDR2 SDRAMs in
60-ball FBGA chipsize packages
Programmable CAS Latencies (3, 4 & 5),
Burst Length (4 & 8) and Burst Type.
•
•
Auto Refresh and Self Refresh
All inputs and outputs SSTL_1.8 compatible
•
Performance:
Speed Grade Indicator
-5
-3.7
DDR2-533
PC2-4200
200
-3
DDR2-667
PC2-5300
200
Unit
Component Speed Grade on Module
Module Speed Grade
DDR2-400
PC2-3200
200
Max. Clock Frequency @ CL = 3
Max. Clock Frequency@ CL = 4 & 5
MHz
MHz
200
266
333
1.0 Description
The INFINEON HYS72T32000GR, HYS72T64020GR and HYS72T64001 are low profile
Registered DIMM modules with 30,00 mm height based on DDR2 technology. DIMMs are available
in 32M x 72 (256 MByte), 2 x 32M x 72 (512 MByte) and 64M x 72 (512 MByte) organisation and
density, intended for mounting into 240 pin connector sockets.
The memory array is designed with 256Mbit Double Data Rate (DDR2) Synchronous DRAMs for
ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one
cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide
a proper voltage supply impedance over the whole frequency range of operations as number and
values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based
on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to the customer.
INFINEON Technologies
Rainer.Weidlich@Infineon.com
2
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.1 Ordering Information
Type & Partnumber
Compliance Code
Description
SDRAM
Technology
PC2-3200 (DDR2-400):
HYS72T32000GR-5-A
HYS72T64020GR-5-A
HYS72T64001GR-5-A
PC2-4200 (DDR2-533):
HYS72T32000GR-3.7-A
HYS72T64020GR-3.7-A
HYS72T64001GR-3.7-A
PC2-5300 (DDR2-667):
HYS72T32000GR-3-A
HYS72T64020GR-3-A
HYS72T64001GR-3-A
Notes:
PC2-3200R-33310-A
PC2-3200R-33310-B
PC2-3200R-33310-C
one rank 256 MB Reg. DIMM
two ranks 512 MB Reg. DIMM
one ranks 512 MB Reg.DIMM
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x4)
PC2-4200R-44410-A
PC2-4200R-44410-B
PC2-4200R-44410-C
one rank 256 MB Reg. DIMM
two ranks 512 MB Reg. DIMM
one ranks 512 MB Reg.DIMM
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x4)
PC2-5300R-44410-A
PC2-5300R-44410-B
PC2-5300R-44410-C
one rank 256 MB Reg. DIMM
two ranks 512 MB Reg. DIMM
one ranks 512 MB Reg.DIMM
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x4)
1. All part numbers end with a place code, designating the silicon die revision. Example: HYS 72T32000GR-5-A, indicating
Rev. A dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see
section 8 of this datasheet.
2. The Compliance Code is printed on the module label and describes the speed grade, f.e. “PC2-4200R-44410-C”, where
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “44410” means CAS latency = 4, trcd
latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.0 and produced on the Raw Card “C”.
1.2 Address Format
Part Number
HYS72T32000GR
HYS72T64020GR
HYS72T64001GR-
DIMM
Density
Organization
Memory
Ranks
DDR2-
SDRAMs
# of
SDRAMs
# of row/bank/
column bits
256 MB
32Mb × 72
1
2
1
(256Mb)
32Mb × 8
9
13/2/10
13/2/10
13/2/11
512 MB 2 x 32Mb × 72
512 MB 64Mb x 72
(256Mb)
32Mb × 8
18
18
(256Mb)
64Mb × 4
INFINEON Technologies
3
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.3 Components on Modules and RawCard
DIMM
Density
DRAM components
reference datasheet
PLL
Register
Raw Card
256 MB
512 MB
512 MB
HYB18T256800AC
HYB18T256800AC
HYB18T256400AC
1:10, 1.8V, CU877
1:10, 1.8V, CU877
1:10, 1.8V, CU877
1:1 25-bit 1.8V SSTU32864
1:2 14-bit 1.8V SSTU32864
1:2 14-bit 1.8V SSTU32864
A
B
C
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component
datasheet
1.4 Pin Definition and Function
Pin Name
A[12:0]
Description
Row Address Inputs
Pin Name
CB[7:0]
Description
DIMM ECC Check Bits
SDRAM low data strobes
A11, A[9:0]
A10/AP
Column Address Inputs 4)
DQS[8:0]
Column Address Input for Auto-
Precharge
DM[8:0] /
DQS[17:9]
SDRAM low data mask/
high data strobes
BA[1:0]
CK0
SDRAM Bank Selects
DQS[17:0]
SCL
SDRAM differential data strobes
Serial bus clock
Clock input
(positive line of differential pair)
CK0
Clock input
(negative line of differential pair)
SDA
Serial bus data line
RAS
Row Address Strobe
Column Address Strobe
Read/Write Input
Chip Selects 3)
SA[2:0]
VDD
slave address select
Power (+ 1.8 V)
CAS
WE
VREF
I/O reference supply
Ground
CS[1:0]
CKE[1:0]
ODT[1:0]
DQ[63:0]
VSS
Clock Enable 3)
VDDSPD
EEPROM power supply
Register and PLL control pin 2)
No connection
Active termination control lines 1) 3) RESET
Data Input/Output NC
1) Active termination only applies to DQ, DQS, DQS and DM signals
2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the
PLL will remain synchronized with the input clock
3) CS1, ODT1 and CKE1 are used on dual rank modules only
4) Column address A11 is used on modules based on x4 organised 256Mb DDR2 components only.
INFINEON Technologies
4
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.5 Pin Configuration
Symbol
VREF
VSS
PIN#
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Symbol
VSS
PIN#
61
Symbol
A4
PIN#
181
182
183
184
Symbol
VDDQ
A3
PIN#
1
2
DQ4
62
VDDQ
A2
3
DQ0
DQ5
63
A1
4
DQ1
VSS
64
VDD
VDD
5
VSS
DM0, DQS9
DQS9
VSS
KEY
KEY
6
DQS0
DQS0
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VSS
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
CK0
7
VSS
CK0
8
DQ6
VDD
VDD
9
DQ2
DQ7
NC
A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ3
VSS
VDD
VDD
VSS
DQ12
DQ13
VSS
A10/AP
BA0
BA1
DQ8
VDDQ
RAS
DQ9
VDDQ
WE
VSS
DM1, DQS10
DQS10
VSS
CS0
DQS1
DQS1
VSS
CAS
VDDQ
ODT0
NC
VDDQ
CS1
NC
RESET
NC
NC
ODT1
VDDQ
VSS
VDD
VSS
VSS
VSS
DQ14
DQ15
VSS
DQ36
DQ37
VSS
DQ10
DQ11
VSS
DQ32
DQ33
VSS
DQ20
DQ21
VSS
DM4, DQS13
DQS13
VSS
DQ16
DQ17
VSS
DQS4
DQS4
VSS
DM2, DQS11
DQS11
VSS
DQ38
DQ39
VSS
DQS2
DQS2
VSS
DQ34
DQ35
VSS
DQ22
DQ23
VSS
DQ44
DQ45
VSS
DQ18
DQ19
VSS
DQ40
DQ41
VSS
DQ28
DQ29
VSS
DM5, DQS14
DQS14
VSS
DQ24
DQ25
VSS
DQS5
DQS5
VSS
DM3, DQS12
DQS12
VSS
DQ46
DQ47
VSS
DQS3
DQS3
VSS
DQ42
DQ43
VSS
DQ30
DQ31
VSS
DQ52
DQ53
VSS
DQ26
DQ27
DQ48
DQ49
INFINEON Technologies
5
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Pin Configuration (cont’d)
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
41
VSS
CB0
CB1
VSS
DQS8
DQS8
VSS
CB2
CB3
VSS
VDDQ
CKE0
VDD
NC
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
CB4
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VSS
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NC
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
CB5
SA2
NC
VSS
NC
VSS
DM8, DQS17
DQS17
VSS
VSS
DM6, DQS15
DQS15
VSS
DQS6
DQS6
VSS
CB6
DQ54
DQ55
VSS
CB7
DQ50
DQ51
VSS
VSS
VDDQ
NC, CKE1
VDD
NC
DQ60
DQ61
VSS
DQ56
DQ57
VSS
DM7, DQS16
DQS16
VSS
NC
DQS7
DQS7
VSS
NC
VDDQ
A12
VDDQ
A11
DQ62
DQ63
VSS
A9
DQ58
DQ59
VSS
A7
VDD
A8
VDD
A5
VDDSPD
SA0
A6
SDA
SCL
SA1
1.6 Pin Locations
Front
120
240
pin
1
64
65
pin 121
185
184
Backside
240 pin Modules (MO-237)
INFINEON Technologies
6
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
1.7 Registered DIMM Input/Output Functional Description
Type Polarity
Function
Symbol
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and the falling edge of CK. An on-board DLL circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
CK0, CK0
Input Cross point
CKE high activates and CKE low deactivates internal clock signals and device input buffers
Active High and output drivers of the SDRAMs. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
Input
Input
CKE[1:0]
CS[1:0]
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations con-
Active Low
tinue. The input signals also disable all outputs (except CKE and ODT) of the register(s) on
the DIMM when both inputs are high. When both CS[1:0] are high, all register outputs (except
CK, ODT and Chip select) remain in the previous state.
Active High On-Die Termination control signals
Input
Input
ODT[1:0]
RAS, CAS,
WE
When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to
Active Low
be executed by the SDRAM.
DM[8:0]
BA[1:0]
Active High Masks write data when high, issued concurrently with input data.
Input
Input
-
Selects which internal SDRAM memory bank is activated
During Bank Activate command cycle, Address defines the row address. During a Read or
Write command cycle, Address defines the column address. In addition to the column
address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read
or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be
precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all
banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to
define which bank to precharge.
A[12:0]
-
Input
DQ[63:0],
CB[7:0]
I/O
I/O
-
Data and Check Bit Input /Output pins.
The data strobes, associated with one data byte, source with data transfer. In Write mode,
the data strobe is sourced by the controller and is centered in the data window. In Read
mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the
data window. DQS signals are complements, and timing is relative to the crosspoint of
respective DQS and DQS. If the module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed appropriately.
DQS[17:0],
DQS[17:0]
Cross point
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial
SPD EEPROM address range
-
-
-
-
Input
I/O
SA[2:0]
SDA
This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor
maybe connected from the SDA bus line to VDDSPD on the system planar to act as a pull-
up.
This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from
the SCL bus line to VDDSPD on the system planar to act as a pull-up.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL.
When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the
register(s) will be set to low level. The PLL will remain synchronized with the input clock.
Input
Input
SCL
RESET
VDD, VSS
Supply
Supply
-
-
Power and ground for the DDR SDRAM input buffers and core logic.
Reference voltage for the SSTL-18 inputs.
V
REF
Serial EEPROM positive power supply, wired to a separated power pin at the connector
which supports from 1.7 Volt to 3.6 Volt.
Supply
-
V
DDSPD
Note: CS1, ODT1 and CKE1 are used on dual rank modules only.
INFINEON Technologies
7
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
2.0 Block Diagrams (cont’d)
2.1 One Rank 32M x 72 (256 MByte) DDR2 SDRAM DIMM Module (x8 components)
HYS72T32000GR on Raw Card A
RS0
DQS0
DQS4
DQS0
DM0/DQS9
DQS4
DM4/DQS13
NU/
DM/
NU/
DM/
CS DQS DQS
CS DQS DQS
DQS9
RDQS RDQS
DQS13
RDQS
RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS5
DQS1
DQS5
DM5/DQS14
DQS1
DM1/DQS10
NU/
DM/
NU/
DM/
CS DQS DQS
CS DQS DQS
DQS10
DQS14
RDQS RDQS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS6
DQS0
DM2/DQS11
DQS6
DM6/DQS15
NU/
DM/
NU/
DM/
DQS
DQS DQS
CS DQS
D2
CS
DQS11
DQS15
RDQS RDQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS3
DQS7
DQS3
DM3/DQS12
DQS7
DM7/DQS16
NU/
DM/
CS DQS DQS
NU/
DM/
CS DQS DQS
DQS12
RDQS RDQS
DQS16
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
DQS8
DQS8
DM8/DQS17
V
Serial PD
DDSPD
NU/
DM/
Serial PD
CS DQS DQS
DQS17
RDQS
RDQS
SCL
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
V
V
DD, DDQ
VREF
SDA
D0 - D8
D0 - D8
D8
WP A0
A1 A2
V
SS
SA0 SA1
SA2
D0 - D8
1:1
RS0 -> C S : SDRAMs D0-D8
RBA0 -RBA1-> BA 0-BA1 : SDRAMs D0-D8
RA0 -RA 12-> A0 -A12: SDRA Ms D0 -D8
CK0
CK 0
PCK0-PCK6,PCK8,PCK9
PCK8,PCK9
CK : SDRAMs D0-D8
CK : SDRAMs D0-D8
CS0 *
R
E
G
I
P
L
L
BA0-BA1
PCK0-PCK6,
A0 -A12
S
T
E
R
RAS
CAS
WE
CKE0
ODT0
RESET
PCK7
PCK 7
RRAS -> RAS : SDRAMs D0- D8
RCAS -> C AS: SDRAMs D0-D8
RW E -> WE: SDRAMs D0-D8
PCK7
-> CK : Register
PCK7 > CK : Register
OE
RESET
RCK E0 -> CKE : SDR A
D0-D8
RODT0 -> ODT 0: SDRAMs D0-D8
Notes:
RST
1. DQ-to-I/O wiring may be changed within a byte
2. Unless otherwise noted, resistor values are 22 Ohms
*) CS0 connects to DCS and VDD connects to CSR on the Registers
INFINEON Technologies
8
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Block Diagrams (cont’d)
2.2 64M x 72 (512 MByte) two rank DDR2 SDRAM DIMM Modules (x8 components)
HYS72T64020GR on Raw Card B
RS1
RS0
DQS0
DQS4
DQS0
DM0/DQS9
DQS4
DM4/DQS13
NU/
DM/
NU/
DM/
NU/
DM/
NU/
DM/
CS DQS DQS
CS
DQS DQS
CS DQS DQS
CS DQS DQS
DQS9
DQS13
RDQS RDQS
RDQS RDQS
RDQS RDQS
RDQS RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D9
D0
D4
D13
DQS5
DQS1
DQS5
DM5/DQS14
DQS1
DM1/DQS10
NU/
DM/
NU/
DM/
NU/
DM/
NU/
DM/
CS DQS DQS
D14
DQS
CS DQS DQS
CS
DQS DQS
CS DQS
D5
DQS14
RDQS RDQS
DQS10
RDQS
RDQS RDQS
RDQS RDQS
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
D10
D1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS6
DQS0
DM2/DQS11
DQS6
DM6/DQS15
NU/
DM/
NU/
DM/
NU/
DM/
DQS DQS
NU/
DM/
CS
CS DQS DQS
D15
CS DQS DQS
D2
CS DQS DQS
DQS15
RDQS RDQS
DQS11
RDQS RDQS
RDQS
RDQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D11
D6
DQS3
DQS7
DQS3
DM3/DQS12
DQS7
DM7/DQS16
NU/
DM/
NU/
DM/
NU/
DM/
CS
DQS DQS
CS DQS DQS
D12
NU/
DM/
DQS
DQS
CS DQS
D16
CS DQS
D7
DQS12
RDQS RDQS
RDQS
RDQS
DQS16
RDQS RDQS
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DQS8
DQS8
DM0/DQS17
V
Serial PD
DDSPD
NU/
DM/
NU/
DM/
CS DQS
D17
DQS
CS DQS DQS
DQS17
RDQS RDQS
RDQS RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
V
V
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DD, DDQ
D0 - D17
D0 - D17
VREF
D8
V
SS
D0 - D17
Serial PD
SCL
SDA
1:2
WP A0
SA0 SA1
A1 A2
RS0 -> C S : SDRAMs D0-D8
RS1 -> C S : SDRAMs D9-D17
A0-BA1 : SDRAMs D0-D17
RBA0 -RBA1-> B
RA0 -RA 12-> A0 -A12: SDRA Ms D0-D17
RRAS -> RAS : SDRAMs D0-D17
RCAS -> C AS: SDRAMs
RW E -> WE: SDRAMs
SDRAMs D0-D8
SDRAMs D9-D17
RODT0 -> ODT : SDRAMs
CS0 *
CS1 *
R
E
G
I
SA2
BA 0-BA1
A0 -A12
S
T
E
R
CK 0
CK 0
PCK0-PCK6, PCK8,PCK9
PCK0-PCK6, PCK8,PCK9
CK
: SDRAMs D0-D17
CK : SDRAMs D0-D17
RAS
CAS
WE
P
L
L
D0-D17
D0-D17
:
CKE0
RCK E0 -> CKE
RCK E1 -> CKE
:
:
PCK7 -> CK Register
PCK7
CKE1
ODT0
ODT1
RESET
OE
> CK
: Register
D0-D8
RODT1 -> ODT :SDRAMs D9-D17
RESET
RST
DQ-to-I/O wiring may be changed within a byte
PCK7
DQ/DQS/DQS, adress and control resistors are 22 Ohms
PCK 7
*) CS0 connects to CRS, CS1 connects to CSR on a Register. CS1 connects to DCS and CS0 connects to CSR on another Register.
RESET, PCK7 and PCK7 connect to bother Registers. Other signals connect to one of two Registers.
INFINEON Technologies
9
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Block Diagrams (cont’d)
2.3 One Rank 64M x 72 (512 MByte) DDR2 SDRAM DIMM Modules (x4 components)
HYS72T64001GR on Raw Card C
VSS
RS0
DQS0
DQS9
DQS9
DQS0
DM
DM
CS DQS DQS
D0
CS DQS DQS
D9
DQ0
DQ1
DQ2
DQ4
DQ5
DQ6
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ3
DQ7
DQS1
DQS0
DQS10
DQS10
DM
DM
CS DQS DQS
D1
CS DQS DQS
D10
DQ8
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ10
DQ11
DQS2
DQS2
DQS11
DQS11
DM
DM
DQS
CS DQS
D2
CS
DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D11
DQS12
DQS12
DQS3
DQS3
DM
DM
CS DQS DQS
D3
CS DQS DQS
D12
DQ24
DQ25
DQ26
DQ28
DQ29
DQ30
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ27
DQ31
DQS13
DQS13
DQS4
DQS4
DM
DM
DQS
CS DQS
D4
CS
DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D13
DQS5
DQS5
DQS14
DQS14
DM
DM
CS DQS DQS
D5
CS DQS DQS
D14
DQ40
DQ41
DQ42
DQ44
DQ45
DQ46
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ43
DQ47
DQS15
DQS15
DQS6
DQS6
DM
DM
CS DQS DQS
D6
CS DQS DQS
D15
DQ48
DQ49
DQ50
DQ52
DQ53
DQ54
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ51
DQ55
DQS7
DQS7
DQS16
DQS16
DM
DM
CS DQS DQS
D7
CS DQS DQS
D16
DQ56
DQ57
DQ58
DQ60
DQ61
DQ62
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ59
DQ63
DQS8
DQS8
DQS17
DQS17
DM
DM
DQS
CS DQS
D8
CS
DQS DQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D17
V
Serial PD
Serial PD
DDSPD
1:2
SCL
D0-D17
RS0 -> C S : SDRAMs
A 0-BA1 : SDRAMs
CS0 *
R
E
G
I
SDA
V
V
BA0-BA1
RBA0 -RBA1-> B
DD, DDQ
VREF
D0 - D17
D0 - D17
WP A0
A1 A2
A0 -A12
D0-D17
RA0 -RA12-> A0 -A 12: SDR AMs
S
T
E
R
RAS
CAS
WE
D0-D17
D0-D17
RRA S -> RAS : SDRAMs
RCAS -> C AS: SDRAMs
RW E -> WE: SDRAMs
SA0 SA1 SA2
V
SS
D0 - D17
D0-D17
CKE0
RCKE0 -> CKE
:
D0-D17
SDRAMs
D0-D17
: SDRAMs
P
L
L
CK 0
CK 0
PCK0-PCK6, PCK8,PCK9
PCK0-PCK6, PCK8,PCK9
CK
: SDRAMs D0-D17
CK : SDRAMs D0-D17
ODT0
RESET
PCK7
PCK 7
RODT0 ->
ODT
RST
: Register
PCK7 -> CK
PCK7 > CK : Register
RESET
OE
*) CS0 connects to DCS of Register 1 and CSR of Register 2,
CSR of Register 1 and DCS of Register 2 connects to VDD
**) RESET, PCK7 and PCK7 connet to both Registers.
Other signals connect to one of two Registers.
DQ-to-I/O wiring may be changed within per nibble
Unless otherwise noted, resistor values are 22 Ohms
INFINEON Technologies
10
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
3.0 Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
2.3
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
Voltage on VDD Q relative to VSS
Storage temperature range
VIN, VOUT
VDD
– 0.5
– 1.0
– 0.5
-55
V
V
2.3
VDDQ
2.3
TSTG
+100
oC
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
3.1 Operating Temperature Range
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
TOPR
0
0
+55
+95
oC
TCASE
oC
1 - 4
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For
measurement conditions, please refer to the JEDEC document JESD51-2.
2. Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below
85oC case temperature before initiating self-refresh operation.
3.2 Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit
Notes
min.
1.7
nom.
max.
1.9
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
EEPROM Supply Voltage
DC Input Logic High
VDD
1.8
V
V
-
VDDQ
VREF
VDDSPD
VIH (DC)
VIL (DC)
IL
1.7
1.8
1.9
1)
2)
0.49 x VDDQ
1.7
0.5 x VDDQ
0.51 x VDDQ
3.6
V
–
–
–
–
V
VREF + 0.125
– 0.30
– 5
VDDQ + 0.3
VREF – 0.125
5
V
DC Input Logic Low
V
In / Output Leakage Current
µA
3)
1
2
3
Under all conditions, VDDQ must be less than or equal to VDD
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations in VDDQ
For any pin on the DIMM connector under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V.
.
INFINEON Technologies
11
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
4.0 IDD Specifications and Conditions
4.1 256MByte Registered Module HYS72T32000GR (one rank, nine components x8)
256 MByte HYS72T32000GR
Symbol Parameter / Condition
IDD0
Operating Current
IDD1
PC2-3200 “-5” PC2-4200 “-3.7” PC2-5300 “-3”
max.
700
745
286
502
430
367
286
520
790
880
970
304
36
max.
828
873
369
657
558
477
369
648
963
1098
1098
387
36
max.
957
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Operating Current
1002
453
Precharge PD Standby Current
IDD2P
IDD2N Precharge Standby Current
822
IDD2Q Precharge Quiet Standby Current
687
Active PD Standby Current
IDD3P(0)
597
IDD3P(1) LP Active PD Standby Current
IDD3N Active Standby Current
867
777
Operating Current Burst Read
IDD4R
1137
1317
1227
471
IDD4W Operating Current Burst Write
IDD5B Auto-Refresh Current (tRFCmin.)
Auto-Refresh Current (tREFI)
Self-Refresh Current
Operating Current
IDD5D
IDD6
IDD7
36
1375
1548
1722
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
4.2 512 MByte Registered Module HYS72T64020GR (two ranks, eighteen components x8)
512 MByte HYS72T64020GR
Symbol Parameter / Condition
IDD0
Operating Current
Operating Current
PC2-3200 “-5” PC2-4200 “-3.7” PC2-5300 “-3”
max.
854
899
440
872
728
602
440
908
944
1034
1126
476
72
max.
1021
1066
562
max.
1190
1235
686
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1, 2
1, 2
1, 3
1, 3
1, 3
1, 3
1, 3
1, 3
1, 2
1, 2
1, 2
1, 3
1, 3
1, 2
IDD1
IDD2P Precharge PD Standby Current
IDD2N Precharge Standby Current
1138
940
1424
1154
974
Precharge Quiet Standby Current
IDD2Q
IDD3P(0) Active PD Standby Current
IDD3P(1) LP Active PD Standby Current
778
562
686
Active Standby Current
IDD3N
1120
1156
1291
1291
598
1334
1370
1550
1460
722
IDD4R Operating Current Burst Read
IDD4W Operating Current Burst Write
Auto-Refresh Current (tRFCmin.)
IDD5B
IDD5D Auto-Refresh Current (tREFI)
IDD6
IDD7
Self-Refresh Current
Operating Current
72
72
1529
1741
1955
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD current mode
INFINEON Technologies
12
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
4.3 512 Mbyte Registered Module HYS72T64001GR (one rank, eighteen components x4)
512 MByte HYS72T64001GR
Symbol Parameter / Condition
IDD0
Operating Current
Operating Current
PC2-3200 “-5” PC2-4200 “-3.7” PC2-5300 “-3”
max.
1268
1358
440
max.
1480
1570
562
max.
1694
1784
686
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IDD1
IDD2P Precharge PD Standby Current
IDD2N Precharge Standby Current
872
1138
940
1424
1154
974
Precharge Quiet Standby Current
IDD2Q
728
IDD3P(0) Active PD Standby Current
IDD3P(1) LP Active PD Standby Current
602
778
440
562
686
Active Standby Current
IDD3N
908
1120
1750
2020
2020
598
1334
2054
2414
2234
722
IDD4R Operating Current Burst Read
IDD4W Operating Current Burst Write
1448
1628
1808
476
Auto-Refresh Current (tRFCmin.)
IDD5B
IDD5D Auto-Refresh Current (tREFI)
IDD6
IDD7
Self-Refresh Current
Operating Current
72
72
72
2618
2920
3224
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Currents includes Registers and PLL.
INFINEON Technologies
13
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
4.4 IDD Measurement Conditions
Symbol
Parameter/Condition
Operating Current - One bank Active - Precharge
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), CKE is HIGH, CS is high between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
IDD1
IDD2P
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD),tRCD = tRCD(IDD),AL = 0, CL = CL(IDD);
CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are
SWITCHING.
Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCK(IDD);
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD);
IDD2N
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD);
IDD2Q
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Active Power-Down Current: All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are STA-
IDD3P(0)
IDD3P(1)
IDD3N
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
Active Power-Down Current: All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are STA-
BLE, Data bus inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current: All banks open; tCK = tCK(IDD); tRAS = tRASmax(IDD); tRP = tRP(IDD),CKE is HIGH; CS is high
between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CL(IDD); tCK = tCK(IDD);
tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA.
IDD4R
Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD);
tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Auto-Refresh Current: tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is
IDD5B
IDD5D
IDD6
HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Auto-Refresh Current: tCK = tCK(IDD), Refresh command every tRFC = tREFI interval, CKE is LOW and CS
is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current: CKE ≤ 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max.
All Bank Interleave Read Current:
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL=CL(IDD), AL = tRCD(IDD) -1*tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is high between valid commands, Address bus
inputs are STABLE during DESELECTS; Data bus is SWITCHING.
2. Timing pattern:
IDD7
- DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
- DDR2 -533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
- DDR2 -667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Notes:
1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
2. Definitions for IDD:
LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min.
STABLE is defined as inputs are stable at a HIGH or LOW level.
FLOATING is defined as inputs are VREF = VDDQ / 2.
SWITCHING is defined as:
inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and
inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or
strobes.
3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module level
the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
4. RESET signal is high for all currents, except for IDD6 “Self Refresh”.
5. All current measurements includes Register and PLL current consumption.
INFINEON Technologies
14
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
4.5 IDD Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
-5
-3.7
PC2-4200
-3
Unit
PC2-3200
PC2-5300
Parameter
Symbol
3-3-3
3
4-4-4
4
4-4-4
4
CAS Latency
CL(IDD)
tCK(IDD)
tCK
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
5
3.75
15
3
Active to Read or Write delay
tRCD(IDD)
tRC(IDD)
15
12
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
60
60
57
tRRD(IDD)
tRASmin(IDD)
tRASmax(IDD)
tRP(IDD)
7.5
45
7.5
45
7.5
45
Active to Precharge Command
70000
15
70000
15
70000
12
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command
period
tRFC(IDD)
tREFI
75
75
75
ns
µs
Average periodic Refresh interval
7.8
7.8
7.8
4.5 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The cur-
rent consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long
a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State
Unit
min.
5
typ.
6
max.
7.5
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 0, A2 = 1
mA/DQ
mA/DQ
mA/DQ
Enabled ODT current per DQ
IODTO
IODTT
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are FLOATING
2.5
10
3
3.75
15
12
Active ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; worst case of Data Bus inputs
are STABLE or SWITCHING.
A6 = 1, A2 = 0
5
6
7.5
mA/DQ
note: For power consumption calculations the ODT duty cycle has to be taken into account
INFINEON Technologies
15
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
5.0 Electrical Characteristics & AC Timings
5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only)
-5
-3.7
-3
DDR2 -400
DDR2 -533
DDR2 -667
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
DQ output access time from CK / CK
DQS output access time from CK / CK
CK, CK high-level width
CK, CK low-level width
Clock Half Period
− 600
− 500
0.45
+ 600
-500
−450
0.45
0.45
+500
-450
+450
+400
0.55
0.55
ps
ps
tCK
tCK
tAC
tDQSCK
tCH
+ 500
0.55
0.55
+450
0.55
0.55
-400
0.45
0.45
0.45
tCL
min. (tCL, tCH)
min. (tCL, tCH)
min. (tCL, tCH)
tHP
CL = 3
5000
5000
600
8000
8000
-
5000
3750
600
8000
8000
-
5000
3000
tbd.
8000
8000
-
ps
ps
ps
tCK Clock cycle time
CL = 4 & 5
Address and control input setup time
Address and control input hold time
tIS
tIH
600
400
400
0.6
0.35
-
-
600
350
350
0.6
0.35
-
-
tbd.
300
300
0.6
0.35
-
-
-
-
-
-
ps
ps
ps
tCK
tCK
tDS DQ and DM input setup time
-
-
tDH DQ and DM input hold time
-
-
tIPW Control and Addr. input pulse width (each input)
tDIPW DQ and DM input pulse width (each input)
tHZ Data-out high-impedance time from CK / CK
tLZ(DQ) DQ low-impedance from CK / CK
tLZ(DQS) DQS low-impedance from CK / CK
-
-
-
-
tACmax
tACmax
tACmax ps
2*tACmin tACmax 2*tACmin tACmax 2*tACmin tACmax ps
tACmin
-
tACmax
350
tACmin
-
tACmax
300
tACmin
-
tACmax ps
DQS-DQ skew
tDQSQ
250
ps
ps
(for DQS & associated DQ signals)
Data hold skew factor
-
450
-
-
400
-
-
350
-
tQHS
tQH
Data Output hold time from DQS
tHP-tQHS
tHP-tQHS
tHP-tQHS
WL
WL
WL
WL
WL
WL
Write command to 1st DQS latching transition
DQS input low (high) pulse width (write cycle)
tCK
tCK
tCK
tDQSS
tDQSL,H
tDSS
-0.25
+0.25
-0.25
+0.25
-0.25
+0.25
0.35
0.2
-
-
0.35
0.2
-
-
0.35
0.2
-
-
DQS falling edge to CLK setup time
(write cycle)
DQS falling edge hold time from CLK
(write cycle)
tDSH
0.2
-
0.2
-
0.2
-
tCK
Mode register set command cycle time
Write preamble
2
-
-
2
-
-
2
-
-
tCK
tCK
tCK
tCK
tCK
ns
tMRD
tWPRE
tWPST
tRPRE
tRPST
tRAS
0.25
0.40
0.9
0.25
0.40
0.9
0.35
0.40
0.9
Write postamble
0.60
1.1
0.60
70000
-
0.60
1.1
0.60
70000
-
0.60
1.1
0.60
70000
-
Read preamble
Read postamble
0.40
45
0.40
45
0.40
45
Active to Precharge command
Active to Active/Auto-refresh command period
60
60
57
ns
tRC
Auto-refresh to Active/Auto-refresh command
period
75
-
75
-
75
-
ns
tRFC
INFINEON Technologies
16
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
-5
-3.7
-3
DDR2 -400
DDR2 -533
DDR2 -667
Symbol
Parameter
Unit
Min
15
Max
Min
15
Max
Min
Max
Active to Read or Write delay (with and without
Auto-Precharge) delay
-
-
12
-
-
-
ns
ns
ns
tRCD
tRP Precharge command period
15
-
-
15
-
-
12
Active bank A to Active bank B command
(1k page size)
tRRD
7.5
7.5
7.5
tCCD CAS A to CAS B Command Period
tWR Write recovery time
2
-
-
-
-
-
2
15
-
-
-
-
-
2
15
-
-
-
-
-
tCK
ns
tCK
ns
ns
15
tDAL Auto precharge write recovery + precharge time WR+tRP
WR+tRP
7.5
WR+tRP
7.5
tWTR Internal write to read command delay
10
tRTP Internal read to precharge command delay
7.5
7.5
7.5
Exit power down to any valid command
tXARD
2
6 - AL
2
-
-
-
2
6 - AL
2
-
-
-
2
6 - AL
2
-
-
-
tCK
tCK
tCK
(other than NOP or Deselect)
Exit active power-down mode to read command
(slew exit, lower power)
tXARDS
Exit precharge power-down to any valid com-
mand (other than NOP or Deselect)
tXP
tXSRD Exit Self-Refresh to read command
tXSNR Exit Self-Refresh to non-read command
tCKE CKE minimum high and low pulse width
tOIT OCD drive mode output delay
200
-
-
200
-
-
200
-
-
tCK
ns
tCK
ns
tRFC + 10
tRFC + 10
tRFC + 10
3
0
-
3
0
-
3
0
-
12
12
12
Minimum time clocks remain ON after CKE
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tDELAY
-
-
-
ns
µs
asynchronously drops low
0oC - 85oC
-
-
7.8
3.9
-
-
7.8
3.9
-
-
7.8
3.9
Average Periodic
tREFI
Refresh Interval
85oC - 95oC
1. For details and notes see the relevant INFINEON component datasheet
2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code
for these parameters.
5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition
min.
2
max.
2
Units
ODT turn-on delay
tAOND
tAON
tCK
DDR2-400/533
DDR2-667
tAC(min)
tAC(min)
tAC(min) + 2 ns
tAC(max) + 1 ns
tAC(max) + 0.7 ns
2 tCK + tAC(max) + 1 ns
ODT turn-on
ns
tAONPD ODT turn-on (Power-Down Modes)
tAOFD ODT turn-off delay
ns
tCK
ns
2.5
2.5
tAOF
ODT turn-off
tAC(min)
tAC(max) + 0.6 ns
tAOFPD ODT turn-off delay (Power-Down Modes)
tANPD ODT to Power Down Mode Entry Latency
tAXPD ODT Power Down Exit Latency
tAC(min) + 2 ns
2.5 tCK + tAC(max) + 1 ns ns
3
8
-
-
tCK
tCK
INFINEON Technologies
17
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
6.0 Serial Presence Detect Codes for Registered DIMM Modules
Byte# Description
Note:
Speed
Grade
SPD Entry
Value
Hex Value
“-5 ” := DDR2-3200 (DDR2-400)
“-3.7” := DDR2-4200 (DDR2-533)
“-3 ” := DDR2-5300 (DDR2-667)
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes
all
all
128
256
80
08
08
0D
0A
61
48
00
05
50
3D
30
60
50
45
02
82
08
08
00
0C
04
38
00
01
00
01
50
3D
30
60
50
45
50
60
3C
30
1E
3C
30
2D
40
Total Bytes in Serial PD
Memory Type
all
DDR2-SDRAM
13
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks, Package and Height
Module Data Width
all
all
10 / 11
1 / 2
0A
60
0B
60
all
all
x72
Not used
all
not used
SSTL_1.8
5 ns
Module Interface Levels
Min. Clock Cycle Time at CAS Latency = 5
all
-5
-3.7
-3
3.7 ns
3 ns
10
SDRAM Access Time from Clock at CL = 5
-5
0.6 ns
0.5 ns
0.45 ns
ECC
-3.7
-3
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM Configuration Type
Refresh Rate/Type
all
all
7.8 µs / SR
x8, x4
SDRAM Width, Primary
Error Checking SDRAM Data Width
Not used
all
08
08
04
04
all
x8, x4
all
not used
4 & 8
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
Not used
all
all
4
all
5, 4, 3
not used
Reg. DIMM
see note 1
incl. weak driver
5 ns
all
DIMM Type Information
SDRAM Module Attributes
SDRAM Device Attributes: General
Min. Clock Cycle Time at CAS Latency = 4
all
all
all
-5
-3.7
-3
3.7 ns
3 ns
24
SDRAM Access Time from Clock at CL = 4
-5
0.6 ns
0.5 ns
0.45 ns
5 ns
-3.7
-3
25
26
27
Min. Clock Cycle Time at CAS Latency = 3
SDRAM Access Time from Clock at CL = 3
Minimum Row Precharge Time (tRP)
all
all
0.6 ns
15 ns
-5 & -3.7
-3
12 ns
28
29
Minimum Row Act. to Row Act. Delay (tRRD)
Minimum RAS to CAS Delay (tRCD)
all
7.5 ns
15 ns
-5 & -3.7
-3
12 ns
30
31
Minimum RAS Pulse Width (tRAS)
Module Density (per rank)
all
45 ns
all
40
80
INFINEON Technologies
18
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
Byte# Description
Note:
Speed
Grade
SPD Entry
Value
Hex Value
“-5 ” := DDR2-3200 (DDR2-400)
“-3.7” := DDR2-4200 (DDR2-533)
“-3 ” := DDR2-5300 (DDR2-667)
32
33
34
35
Address and Command Setup Time (tIS)
Address and Command Hold Time (tIH)
Data Input Setup Time (tDS)
-5
-3.7
-3
0.60 ns
0.50 ns
0.45 ns
0.60ns
0.50 ns
0.45ns
0.40 ns
0.35 ns
0.30 ns
0.40 ns
0.35 ns
0.30 ns
15 ns
60
50
45
60
50
45
40
35
30
40
35
30
3C
28
1E
1E
00
00
3C
39
4B
80
23
1E
19
2D
28
23
0F
00
10
7E
tbd.
tbd.
C1
00
XX
XX
XX
XX
XX
FF
-5
-3.7
-3
-5
-3.7
-3
Data Input Hold Time (tDH)
-5
-3.7
-3
36
37
Write Recovery Time (tWR)
all
Internal Write to Read Command delay (tWTR)
-5
10 ns
-3.7 & -3
all
7.5 ns
38
39
40
41
Internal Read to Precharge delay (tRTP)
Not used
7.5 ns
not used
Extension of Byte 41 tRC and Byte 42 tRFC
Minimum Core Cycle Time (tRC)
all
-5 & -3.7
-3
60 ns
57 ns
42
43
44
Min. Auto Refresh Command Cycle Time (tRFC)
Maximum Clock Cycle Time tck
all
75 ns
all
8 ns
Max. DQS-DQ Skew (tDQSQmax.)
-5
0.35 ns
0.30 ns
0.25 ns
0.45 ns
0.40 ns
0.35 ns
15.0 µs
see note 1
Revision 1.0
-3.7
-3
45
Read Data Hold Skew Factor (tQHS)
PLL Relock Time
-5
-3.7
-3
46
47-61 Reserved for “Delta Temperature in SPD”
62
63
SPD Revision
Checksum for Bytes 0 - 62
-5
-3.7
-3
7D
tbd.
tbd.
B6
tbd.
tbd.
64
Manufacturers JEDEC ID Code
INFINEON
not used
65-71 Not used
72
Module Assembly Location
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Date
95-98 Module Serial Number
99-127 Manufacturer’s Specific Data
128-255 Open for Customer use
Year/Week Code
Serial Number
blank
blank
Note 1 : Will be used for future SPD Code Revisions. For details of “Delta Temperature in SPD” see JEDEC ballot JC-
42.5 Item # 1468.
INFINEON Technologies
19
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
7.0 Package Outline
7.1 Raw Card A
Module Package
DDR2 Registered DIMM Modules Raw Card A
one physical rank, 9 components x8 organised
+ 0.15
-
133.35
2.7 max.
Front View
4.0
PLL
120
pin 1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Backside View
185
pin 121
240
184
3
3
Detail of Contacts B
5.0
Detail of Contacts A
0.75R
0.8 -+ 0.05
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
INFINEON Technologies
20
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
7.2 Raw Card B
Module Package
DDR2 Registered DIMM Modules Raw Card B
two one physical rank, 18 components x8 organised
+ 0.15
-
133.35
4.0 m ax.
Front View
4.0
PLL
120
pin
1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Backside View
pin 121
240
185
184
3
3
D etail of C ontacts
A
Detail of C ontacts
5.0
B
0.75R
+ 0.05
-
0.8
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
INFINEON Technologies
21
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
7.3 Raw Card C
Module Package
DDR2 Registered DIMM Modules Raw Card C
one physical rank, 18 components x4 organised
+ 0.15
-
133.35
4.0 m ax.
Front View
4.0
PLL
120
pin
1
64
65
+ 0.1
-
1.27
63,0
5,175
5,175
55,0
PCB warpage 0.40
5.0
Backside View
pin 121
240
185
184
3
3
D etail of C ontacts
A
Detail of C ontacts
5.0
B
0.75R
+ 0.05
-
0.8
1.0
1.5
2.5
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
INFINEON Technologies
22
2.04
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
8.0 Nomenclature (Modules & Components)
8.1 DDR2 DIMM Modules
1
2
3
4
5
6
7
8
9
10
11
H Y S 6 4
T
6 4
0
2
0
G
R
- 5
-A
Example:
0 = standard
1
2
INFINEON Prefix
HYS for DIMM Modules
7
8
Product Variations
Package
2 = dual die package
64 = Non-ECC Modules
72 = ECC Modules
G= BGA components
Module Data Width
R = Registered DIMMs
U = Unbuffered DIMMs
DL = Small Outline DIMMs
T = DDR2
DRAM Technology
Module Type
3
4
9
32 = 32 Mb
-5 = PC2-3200 (DDR2-400)
-3.7 = PC2-4200 (DDR2-533)
-3 = PC2-5300 (DDR2-667)
64 = 64 Mb
Memory Density per I/O
Raw Card Generation
10 Speed Grade
128 = 128 Mb
256 = 256 Mb
A = 1st Generation
B = 2nd Generation
C = 3rd Generation
5
6
0 = first generation
11 Die Revision
Multiplying “Memory Density per I/O” with “Module Data Width”
and dividing by 8 for Non-ECC and 9 for ECC modules gives the
overall module memory density in MBytes.
Number of Memory
Ranks
0 = One Rank
2 = Two Ranks
8.2 DDR2 Memory Components
1
2
3
4
5
6
7
8
9
H Y B 1 8
T
2 5 6 4 0
0
A
C
- 5
Example:
INFINEON
HYB for DRAM Components
18 = 1.8 V Power Supply
Product Variations
Die Revision
0 = standard
1
2
6
7
Component Prefix
A = 1st Generation
B = 2nd Generation
C = 3rd Generation
C = BGA package
F = BGA package (lead and
halogen free)
-5 =...DDR2-400
-3.7 =.DDR2-533
-3 =...DDR2-667
Power Supply Voltage
DRAM Technology
Memory Density
3
4
5
T = DDR2
8
Package Type
Speed Grade
256 = 256 Mb
512 = 512 Mb
1G = 1024Mb
40 = x4, 4 data in/outputs
80 = x8, 8 data in/outputs
16 = x16, 16 data in/outputs
9
Memory Organisation
INFINEON Technologies
23
2.04
相关型号：
©2020 ICPDF网 联系我们和版权申明