IAUS300N08S5N014T [INFINEON]
The IAUS300N08S5N014T is a 1.4 mΩ, topside-cooled 80 V MOSFET coming in the TOLT package with Infineon’s leading OptiMOS™-5 technology. Next to others the device is designed for 48V applications. Alongside the 48V auxiliary applications, the device is primarily used in the the DC-DC converter and the main battery switch.;
| 型号： | IAUS300N08S5N014T |
| 厂家： | 
Infineon |
| 描述： | The IAUS300N08S5N014T is a 1.4 mΩ, topside-cooled 80 V MOSFET coming in the TOLT package with Infineon’s leading OptiMOS™-5 technology. Next to others the device is designed for 48V applications. Alongside the 48V auxiliary applications, the device is primarily used in the the DC-DC converter and the main battery switch. |
| 文件： | 总10页 (文件大小：1019K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IAUS300N08S5N014T
OptiMOS™-5 Power-Transistor
Product Summary
VDS
RDS(on)
ID
80
1.4
300
V
mW
A
Features
• OptiMOS™ power MOSFET for automotive applications
PG-HDSOP-16-2
• N-channel – Enhancement mode – Normal Level
• Extended qualification beyond AEC-Q101
• Enhanced electrical testing
• Robust design
• MSL1 up to 260°C peak reflow
• 175°C operating temperature
• Green product (RoHS compliant)
• 100% Avalanche tested
Type
Package
Marking
PG-HDSOP-16-2
5N08014
IAUS300N08S5N014T
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol
Conditions
Unit
VGS=10 V, Chip
limitation1,2)
VGS=10V, DC
current3)
T a=85 °C, VGS=10 V,
R thJA on 2s2p2,4)
I D
Continuous drain current
327
300
108
A
Pulsed drain current2)
I D,pulse
EAS
I AS
T C=25 °C, t p= 100 µs
1186
600
Avalanche energy, single pulse2)
Avalanche current, single pulse
Gate source voltage
I D=150 A
mJ
A
-
300
VGS
Ptot
-
±20
V
T C=25 °C
Power dissipation
300
W
°C
T j, T stg
-
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
-
-
-55 ... +175
55/175/56
Rev. 1.0
page 1
2020-10-01
IAUS300N08S5N014T
Values
typ.
Parameter
Symbol
Conditions
Unit
min.
max.
Thermal characteristics2)
Top
-
-
-
-
0.5
K/W
R thJC
Thermal resistance, junction - case
Bottom (Pin 1-7)
Bottom (Pin 9-16)
9
3
-
-
Top
-
-
2.8
40
-
-
Thermal resistance, junction -
ambient4)
R thJA
Bottom (through PCB)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
VGS=0 V,
I D=1 mA
V(BR)DSS
Drain-source breakdown voltage
Gate threshold voltage
80
2.2
-
-
3
-
3.8
1
V
VGS(th) VDS=VGS, I D=230 µA
VDS=80 V, VGS=0 V,
T j=25 °C
I DSS
Zero gate voltage drain current
0.1
µA
VDS=40 V, VGS=0 V,
T j=85 °C2)
-
1
20
I GSS
VGS=20 V, VDS=0 V
Gate-source leakage current
-
-
-
-
-
100 nA
RDS(on) VGS=6 V, I D=75 A
VGS=10 V, I D=100 A
Drain-source on-state resistance
1.6
1.2
1.3
2.1
1.4
-
mΩ
Gate resistance2)
R G
-
W
Rev. 1.0
page 2
2020-10-01
IAUS300N08S5N014T
Values
typ.
Parameter
Symbol
Conditions
Unit
min.
max.
Dynamic characteristics2)
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
C iss
C oss
Crss
t d(on)
t r
-
-
-
-
-
-
-
10137
1626
71
13178 pF
2114
VGS=0 V, VDS=40 V,
f =1 MHz
106
25
-
-
-
-
ns
15
VDD=40 V, VGS=10 V,
I D=100 A, R G=3.5 W
t d(off)
t f
Turn-off delay time
Fall time
52
46
Gate Charge Characteristics2)
Gate to source charge
Gate to drain charge
Gate charge total
Q gs
-
-
-
-
46
30
60
47
187
-
nC
Q gd
VDD=40 V, I D=100 A,
VGS=0 to 10 V
Q g
144
4.5
Vplateau
Gate plateau voltage
V
A
Reverse Diode
Diode continous forward current2)
Diode pulse current2)
I S
T C=25 °C
-
-
-
-
300
I S,pulse
T C=25 °C, t p= 100 µs
2000
VGS=0 V, I F=100 A,
T j=25 °C
VSD
Diode forward voltage
-
0.9
1.2
V
Reverse recovery time2)
t rr
-
-
83
-
-
ns
VR=40 V, I F=50A,
diF/dt =100 A/µs
Reverse recovery charge2)
Q rr
156
nC
1) Practically the current is limited by the overall system design including the customer-specific PCB.
2) The parameter is not subject to production testing – specified by design.
3) Current is limited by the bondwires.
4) Device on a four-layer 2s2p FR4 PCB with topside cooling. Thermal insulation material is 100 µm thick and has a
conductivity of 0.7 W/mK. Top surface of heat sink is fixed at ambient temperature. Bottom surface of PCB is left at
free convection. Values may vary depending on the customer-specific design.
Rev. 1.0
page 3
2020-10-01
IAUS300N08S5N014T
1 Power dissipation
2 Drain current
Ptot = f(T C); VGS ≥ 6 V
I D = f(T C); VGS ≥ 6 V
350
Chip limit
300
250
200
150
100
50
300
250
200
150
100
50
DC current
0
0
0
50
100
150
200
0
50
100
150
200
TC [°C]
TC [°C]
3 Safe operating area
4 Max. transient thermal impedance
Z thJC = f(t p)
I D = f(VDS); T C = 25 °C; D = 0
parameter: t p
parameter: D =t p/T
100
10000
1000
100
10
0.5
1 µs
10 µs
10-1
100 µs
0.1
1 ms
0.05
0.01
10-2
single pulse
10-3
1
0.1
1
10
100
10-6
10-5
10-4
10-3
10-2
10-1
100
VDS [V]
tp [s]
Rev. 1.0
page 4
2020-10-01
IAUS300N08S5N014T
5 Typ. output characteristics
I D = f(VDS); T j = 25 °C
parameter: VGS
6 Typ. drain-source on-state resistance
R DS(on) = f(I D); T j = 25 °C
parameter: VGS
4
1200
4.5 V
5 V
8.5 V
10 V
7 V
3.5
3
1000
800
600
400
200
0
6 V
2.5
2
6 V
5 V
1.5
1
7 V
8 V
10 V
0
100
200
300
0
1
2
3
4
5
6
7
ID [A]
VDS [V]
7 Typ. transfer characteristics
I D = f(VGS); VDS = 6V
parameter: T j
8 Typ. drain-source on-state resistance
R DS(on) = f(T j)
parameter: I D , VGS
1200
1000
800
600
400
200
0
3
25 °C
-55 °C
2.5
175 °C
VGS = 6V,
ID=75 A
2
1.5
VGS =10 V, ID
=100 A
1
0.5
-60
-20
20
60
100
140
180
2.5
3.5
4.5
5.5
6.5
7.5
Tj [°C]
VGS [V]
Rev. 1.0
page 5
2020-10-01
IAUS300N08S5N014T
9 Typ. gate threshold voltage
VGS(th) = f(T j); VGS = VDS
parameter: I D
10 Typ. capacitances
C = f(VDS); VGS = 0 V; f = 1 MHz
105
4
3.5
3
Ciss
104
103
102
2300 µA
Coss
230 µA
2.5
2
1.5
1
Crss
0
10
20
30
40
50
60
70
80
-60
-20
20
60
100
140
180
Tj [°C]
VDS [V]
11 Typical forward diode characteristics
I F = f(VSD
12 Typ. avalanche characteristics
I AS = f(t AV
)
)
parameter: T j
parameter: T j(start)
104
1000
103
102
101
25 °C
100 °C
100
150 °C
25 °C
175 °C
10
100
0
1
1
0.2
0.4
0.6
0.8
1
1.2
1.4
10
100
1000
VSD [V]
tAV [µs]
Rev. 1.0
page 6
2020-10-01
IAUS300N08S5N014T
13 Typical avalanche energy
EAS = f(T j)
14 Drain-source breakdown voltage
VBR(DSS) = f(T j); I D_typ = 1 mA
parameter: I D
88
86
84
82
80
78
76
1200
75 A
900
150 A
600
300 A
300
0
-60
-20
20
60
100
140
180
25
75
125
175
Tj [°C]
Tj [°C]
15 Typ. gate charge
16 Gate charge waveforms
VGS = f(Q gate); I D = 100 A pulsed
parameter: VDD
10
9
8
7
6
5
4
3
2
1
0
VGS
16 V
Qg
40 V
64 V
Qgate
Qgd
Qgs
0
50
100
150
Qgate [nC]
Rev. 1.0
page 7
2020-10-01
IAUS300N08S5N014T
Package Outline
Footprint
Packaging
Rev. 1.0
page 8
2020-10-01
IAUS300N08S5N014T
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 2020
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein, any typical values stated
herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties
of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact
the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the
express written approval of Infineon Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body or to support and/or maintain and sustain and/or protect human life.
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Rev. 1.0
page 9
2020-10-01
IAUS300N08S5N014T
Revision History
Version
Date
Changes
Final Datasheet
Version 1.0
01.10.2020
Rev. 1.0
page 10
2020-10-01
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