IPB160N04S3-H2 [INFINEON]

OptiMOS-T Power-Transistor; 的OptiMOS -T电源晶体管
IPB160N04S3-H2
型号: IPB160N04S3-H2
厂家: Infineon    Infineon
描述:

OptiMOS-T Power-Transistor
的OptiMOS -T电源晶体管

晶体 晶体管 功率场效应晶体管 脉冲
文件: 总9页 (文件大小:193K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
IPB160N04S3-H2  
OptiMOS®-T Power-Transistor  
Product Summary  
VDS  
R DS(on)  
I D  
40  
2.1  
160  
V
m  
A
Features  
• N-channel - Enhancement mode  
PG-TO263-7-3  
• Automotive AEC Q101 qualified  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Green package (RoHS compliant)  
• Ultra low Rds(on)  
• 100% Avalanche tested  
Type  
Package  
Marking  
IPB160N04S3-H2  
PG-TO263-7-3  
3QN04H2  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
T C=25°C, VGS=10V1)  
I D  
Continuous drain current  
160  
157  
A
T C=100 °C,  
V
GS=10 V2)  
Pulsed drain current2)  
I D,pulse  
EAS  
T C=25 °C  
I D=80 A  
640  
898  
Avalanche energy, single pulse  
Gate source voltage  
mJ  
V
VGS  
±20  
Ptot  
T C=25 °C  
Power dissipation  
214  
W
°C  
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... +175  
55/175/56  
Rev. 1.0  
page 1  
2007-04-16  
IPB160N04S3-H2  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
R thJA  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
0.7  
62  
40  
K/W  
minimal footprint  
6 cm2 cooling area3)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS  
VGS(th)  
V
V
GS=0 V, I D= 1 mA  
Drain-source breakdown voltage  
Gate threshold voltage  
40  
-
-
V
DS=VGS, I D=150 µA  
2.1  
3.0  
4.0  
V
DS=40 V, VGS=0 V,  
I DSS  
Zero gate voltage drain current  
-
-
-
-
1
µA  
T j=25 °C  
V
DS=40 V, VGS=0 V,  
100  
T j=125 °C2)  
I GSS  
V
V
GS=20 V, VDS=0 V  
GS=10 V, I D=80 A  
Gate-source leakage current  
-
-
-
100 nA  
RDS(on)  
Drain-source on-state resistance  
1.6  
2.1  
m  
Rev. 1.0  
page 2  
2007-04-16  
IPB160N04S3-H2  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
7400  
2000  
310  
30  
9600 pF  
2600  
V
GS=0 V, VDS=25 V,  
f =1 MHz  
465  
-
-
-
-
ns  
16  
V
DD=20 V, VGS=10 V,  
I D=80 A, R G=3.3 Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
46  
17  
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
38  
25  
50  
45  
145  
-
nC  
Q gd  
V
V
DD=32 V, I D=80 A,  
GS=0 to 10 V  
Q g  
110  
5.2  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current2)  
I S  
-
-
-
-
160  
640  
T C=25 °C  
I S,pulse  
V
GS=0 V, I F=80 A,  
VSD  
Diode forward voltage  
-
0.85  
1.3  
V
T j=25 °C  
Reverse recovery time2)  
Reverse recovery charge2)  
t rr  
-
-
60  
95  
-
-
ns  
VR=20 V, I F=50A,  
diF/dt =100 A/µs  
Q rr  
nC  
1) Current is limited by bondwire; with an R thJC = 0.7 K/W the chip is able to carry 221 A at 25°C. For detailed  
information see Application Note ANPS071E at www.infineon.com/optimos  
2) Defined by design. Not subject to production test.  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.0  
page 3  
2007-04-16  
IPB160N04S3-H2  
1 Power dissipation  
2 Drain current  
P
tot = f(T C); VGS 6 V  
I D = f(T C); VGS 6 V  
250  
180  
160  
140  
120  
100  
80  
200  
150  
100  
50  
60  
40  
20  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
Z
parameter: D =t p/T  
100  
1000  
100  
10  
1 µs  
0.5  
10 µs  
100 µs  
10-1  
0.1  
0.05  
1 ms  
0.01  
10-2  
single pulse  
10-3  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
t
p [s]  
V
DS [V]  
Rev. 1.0  
page 4  
2007-04-16  
IPB160N04S3-H2  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
DS(on) = (I D); T j = 25 °C  
R
parameter: VGS  
14  
10 V  
6 V  
5.5 V  
6.5 V  
7 V  
600  
7 V  
12  
10  
8
500  
400  
300  
200  
100  
0
6.5 V  
6
6 V  
4
5.5 V  
5 V  
2
10 V  
0
0
100  
200  
300  
D [A]  
400  
500  
600  
0
2
4
6
V
DS [V]  
I
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R
DS(on) = f(T j); I D = 80 A; VGS = 10 V  
3
600  
500  
400  
300  
2.5  
2
200  
1.5  
1
175 °C  
100  
25 °C  
-55 °C  
0
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
2
3
4
5
6
7
8
V
GS [V]  
Rev. 1.0  
page 5  
2007-04-16  
IPB160N04S3-H2  
9 Typ. gate threshold voltage  
GS(th) = f(T j); VGS = VDS  
10 Typ. capacitances  
V
C = f(VDS); VGS = 0 V; f = 1 MHz  
parameter: I D  
105  
104  
103  
4
3.5  
3
1500µA  
Ciss  
150µA  
2.5  
2
Coss  
1.5  
Crss  
1
0
5
10  
15  
20  
25  
30  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
V
DS [V]  
11 Typical forward diode characteristicis  
12 Typ. avalanche characteristics  
AS = f(t AV  
IF = f(VSD)  
I
)
parameter: T j  
parameter: Tj(start)  
103  
1000  
102  
100  
10  
25°C  
100°C  
150°C  
25 °C  
175 °C  
101  
100  
1
1
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
10  
100  
1000  
V
SD [V]  
t
AV [µs]  
Rev. 1.0  
page 6  
2007-04-16  
IPB160N04S3-H2  
13 Typical avalanche energy  
AS = f(T j)  
14 Drain-source breakdown voltage  
E
V
BR(DSS) = f(T j); I D = 1 mA  
parameter: I D  
52  
4000  
3500  
48  
44  
40  
36  
32  
20 A  
3000  
2500  
2000  
40 A  
1500  
1000  
80 A  
500  
0
-60  
-20  
20  
60  
100  
140  
180  
25  
75  
125  
175  
T j [°C]  
T j [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
V
GS = f(Q gate); I D = 80 A pulsed  
parameter: VDD  
12  
VGS  
10  
8
Qg  
8 V  
32 V  
6
4
Qgate  
2
Qgd  
Qgs  
0
0
20  
40  
60  
80  
100  
120  
Q
gate [nC]  
Rev. 1.0  
page 7  
2007-04-16  
IPB160N04S3-H2  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2007  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein,  
any typical values stated herein and/or any information regarding the application of the device,  
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including  
without limitation warranties of noninfringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices please  
contact your nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information  
on the types in question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably  
be expected to cause the failure of that life-support device or system, or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be  
implanted in the human body, or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be  
endangered.  
Rev. 1.0  
page 8  
2007-04-16  
IPB160N04S3-H2  
Revision History  
Version  
Date  
Changes  
Rev. 1.0  
page 9  
2007-04-16  

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